172 results on '"Haendler, S."'
Search Results
52. Low frequency noise temperature measurements in SiGe:C heterojunction bipolar transistors.
53. Impact of dynamic variability on the operation of CMOS inverter
54. Low frequency noise measurements of advanced BiCMOS SiGeC Heterojunction Bipolar Transistors used for mm-Wave to terahertz applications
55. Evolution of low frequency noise and noise variability through CMOS bulk technology nodes
56. Switching energy efficiency optimization for advanced CPU thanks to UTBB technology
57. Characterization and Modeling of Back Bias Impacts on Remote-Coulomb-Limited Mobility in UTBB-FDSOI Devices
58. Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs
59. Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates
60. 28nm FDSOI technology platform for high-speed low-voltage digital applications
61. Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology
62. Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances
63. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
64. Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors
65. Low-Frequency Noise Investigation and Noise Variability Analysis in High- $k$/Metal Gate 32-nm CMOS Transistors
66. Improvement of 1/f noise in advanced 0.13 µm BiCMOS SiGe:C Heterojunction Bipolar Transistors
67. Low power UTBOX and back plane (BP) FDSOI technology for 32nm node and below
68. Oxide defects generation modeling and impact on BD understanding
69. Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below
70. Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
71. First CMOS integration of ultra thin body and BOX (UTB2) structures on bulk direct silicon bonded (DSB) wafer with multi-surface orientations
72. Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
73. Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
74. FDSOI devices with thin BOX and ground plane integration for 32nm node and below
75. Process Architecture for Spatial and Temporal Variability Improvement of SRAM Circuits at the 45nm Node
76. Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications
77. FDSOI devices with thin BOX and ground plane integration for 32nm node and below
78. RF Power NLDMOS Technology Transfer Strategy from the 130nm to the 65nm node on thin SOI
79. Thermal resistance reduction in power MOSFETs integrated in a 65nm SOI technology
80. Silicon characterization of standby leakage reduction techniques in a 0.13μm Low Power Partially-Depleted Silicon-On-Insulator Technology
81. Shrinking from 0.25 down to 0.12 μm SOI CMOS technology node: a contribution to low-frequency noise in partially depleted N-MOSFETs
82. ON THE 1/f NOISE IN 0.15 μm FULLY DEPLETED SOI/MOS TRANSISTORS
83. ON THE 1/F NOISE IN FULLY DEPLETED SOI TRANSISTORS
84. On the Noise in Dynamic Threshold (DT) MOS/SOI Transistors.
85. Thorough Investigation of Kink-Related Excess Noise in Deep Submicron SOI N-MOSFETs on Unibond Substrate
86. Low-Frequency Noise Investigation and Noise Variability Analysis in High- k/Metal Gate 32-nm CMOS Transistors.
87. <atl>Reliability of ultra-thin film deep submicron SIMOX nMOSFETs
88. Self-heating Eeffects in SOI NLDEMOS Power Devices.
89. Is SOI CMOS a promising technology for SOCs in high frequency range?
90. Comparative low frequency noise analysis in various SOI devices: floating body, body-tied, DTMOS with and without current limiter
91. Silicon characterization of standby leakage reduction techniques in a 0.13μm Low Power Partially-Depleted Silicon-On-Insulator Technology
92. 0.25 μm SOI technologies performance for low-power radio-frequency applications
93. FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs.
94. Optimizing the salicide thickness for improving 130 nm PD SOI performances.
95. A comparative approach of low frequency noise in 0.25 and 0.12 μm Partially and Fully Depleted SOI N-MOSFETs.
96. Comparative low frequency noise analysis in various SOI devices: floating body, body-tied, DTMOS with and without current limiter.
97. Oxide defects generation modeling and impact on BD understanding.
98. Design-in reliability approach for Hot Carrier injection modeling in the context of AMS/RF applications.
99. Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors.
100. 0.25 μm SOI technologies performance for low-power radio-frequency applications.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.