75 results on '"Han, Jaeduk"'
Search Results
52. Design and Automatic Generation of High-Speed Circuits for Wireline Communications
53. A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance
54. A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit
55. A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET
56. A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET
57. Multi-frame super-resolution utilizing spatially adaptive regularization for ToF camera
58. An Automated SerDes Frontend Generator Verified With a 16-nm Instance Achieving 15 Gb/s at 1.96 pJ/bit
59. A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET
60. A Low Cost AC Direct LED Driver with Reduced Flicker Using Triac
61. A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET
62. Permuted Coordinate-Wise Optimizations Applied to Lp-Regularized Image Deconvolution
63. An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit
64. BAG2: A process-portable framework for generator-based AMS circuit design
65. A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
66. Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology
67. A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET
68. 6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET
69. 6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology
70. Non-blind Image Deconvolution using Sampling without Replacement
71. A Supply-Scalable Serializing Transmitter with Controllable Output Swing and Equalization for Next Generation Standards
72. Saturation Improvement Algorithm with Contrast Enhancement for Color Images Considering Channel Correlation
73. A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
74. A 60Gb/s 173mW receiver frontend in 65nm CMOS technology
75. Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.