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51. Experimental Comparison of Adaptive vs. Static Thumbnail Displays

Author

Choe, Pilsung, Kim, Chulwoo, Lehto, Mark R., Allebach, Jan, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Jacko, Julie A., editor

Published
2007
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53. A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications

Author

Kim, Hyunjin, Park, Changhun, Park, Inho, Park, Taehyeong, Park, Seungwoo, and Kim, Chulwoo

Abstract

This article presents a four-phase time-based switched-capacitor low-dropout (SCLDO) regulator that regulates an output load voltage ( $V_{\text {OUT}}$ ) of 0.35–0.95 V with an input voltage ( $V_{\text {IN}}$ ) of 0.45–1 V. The regulator employs a four-phase time quantizer, which enables high proportional gain control and short transient response time with relatively low quiescent current. In addition, the proposed SCLDO employs a 9.6-pF coupling capacitor ( $C_{\text {C}}$ ) that is connected to the gate voltage of the pass transistor and $V_{\text {OUT}}$ node, thereby reducing the $V_{\text {OUT}}$ voltage drop during the load transition. Because the SCLDO utilizes capacitor components when charging and discharging $C_{\text {C}}$ , it provides robustness to process and temperature variations even at low- $V_{\text {IN}}$ conditions. Therefore, the proposed time-based SCLDO achieved a $V_{\text {OUT}}$ settling time of 4.4 ns at $V_{\text {IN}}$ = 1 V and 13 ns at $V_{\text {IN}}$ = 0.5 V condition. Fabricated in a 28-nm CMOS process, the proposed time-based SCLDO achieves a maximum $I_{\text {OUT}}$ of 400 mA and a figure of merit (FoM) of 3.0 fs, with an active area of 0.021 mm2.

Published
2024
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54. Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing

Author

Han, Youngsun, Kim, Seon Wook, Kim, Chulwoo, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Yang, Laurence T., editor, Zhou, Xingshe, editor, Zhao, Wei, editor, Wu, Zhaohui, editor, Zhu, Yian, editor, and Lin, Man, editor

Published
2005
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55. Mutant Srsf2 Diminishes Jak2V617F-Induced Erythrocytosis in Mice and Is Associated with Lower Hemoglobin in Patients with Chronic Phase JAK2-Mutant MPN

Author

Marneth, Anna E, primary, Jutzi, Jonas S., additional, Kim, Chulwoo J., additional, Laurore, Charles, additional, Tishena, Anastasia, additional, Kramer, Frederike, additional, Rocha, Azucena V., additional, Wazir, Mohammed, additional, Weeks, Lachelle D., additional, How, Joan, additional, Stahl, Maximilian F., additional, Luskin, Marlise R., additional, Lindsley, R. Coleman, additional, Pozdnyakova, Olga, additional, Graubert, Timothy A., additional, and Mullally, Ann, additional

Published
2022
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75. An Automotive 12 V-to-1.2 V Integrated Switched-Capacitor DC–DC Converter for Improved Load Transient Response

Author

Park, Inho, Kim, Hyunjin, Park, Taehyeong, Jeong, Junwon, and Kim, Chulwoo

Abstract

This letter presents a 12 V-to-1.2 V switched-capacitor dc–dc converter, which has a voltage conversion ratio of 1/10 with an input voltage of 12 V, for automotive applications. The power stage comprises an eight-phase ladder converter and a 16-phase 3-to-1 converter. All power switches are designed using 5-V isolated complementary metal-oxide-semiconductor (CMOS) transistors. To improve the load transient response, the bias current for the charge pump of the 3-to-1 converter is adjusted via a dynamic amplifier. The charge pump for the ladder converter is assisted by the feedback loop of the 3-to-1 converter so that it responds fast to the light-to-heavy load transition. The proposed phase-shedding control reduces the overshoot when the load current increases. The proposed work is fabricated in a 180-nm BCD process. For a load step of 60 mA, the light-to-heavy and heavy-to-light responses are improved by 47.28% and 52.50%, respectively. The maximum end-to-end efficiency is measured as 57.80%.

Published
2023
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96. A low-power programmable DLL-based clock generator with wide-range antiharmonic lock

Author

Koo, Jabeom, Ok, Sunghwa, and Kim, Chulwoo

Subjects
Complementary metal oxide semiconductors -- Design and construction, Electric circuits -- Design and construction, Circuit design -- Methods, Circuit designer, Integrated circuit design, Business, Computers and office automation industries, Electronics, Electronics and electrical industries
Abstract

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-[Mu]m CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 [mm.sup.2] and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones. Index Terms--Antiharmonic lock, frequency multiplier.

Published
2009

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