Search

Polarized Stress Imaging is an excellent method for monitoring bulk stress distribution in silicon wafers. In this study, the correlation of bulk Si stress and lithography defects are shown using Semilab’s Polarized Stress Imager (PSI) system. 300 mm diameter samples with 7 nm advanced node FinFET devices were investigated with PSI optical imaging metrology tool and AMAT’s UVision wafer inspection tool. Two sets of samples were analyzed after shallow trench isolation etch and after gate etch. Results show that stress imaging can detect process deviations that lead to high defectivity and may have uses in failure analysis to pinpoint root causes of failures.

In this work, SiGe Fin formation technique using shallow trench isolation (STI) first or STI last strategy for the high mobility channel FinFET device is systematically investigated. A 20 nm width and 35 nm height high crystalline quality of the Si0.7Ge0.3 Fin formation for STI first scheme is demonstrated by utilizing a new developed Si Fin etching, Si Fin recess and SiGe selective epitaxial growth process. For the STI last strategy, a novel chemical mechanical planarization (CMP) treated three-layer SiGe strain relaxed buffer (SRB) is successfully fabricated and a 50 nm high crystal quality and atomically smooth surface Si0.5Ge0.5 layer on this SRB is attained. Moreover, a spike annealing is employed to avoid the Si0.5Ge0.5 Fin oxidation during STI densification with an acceptable STI etching rate. However, both a spike annealing and a lower temperature of traditional furnace at 850 °C or 750 °C suffer micro-trench issue during the Fin reveal process. Therefore, a new developed process, named as STI recess first, is developed to resolve both thermal instability and micro-trench issue at the same time. A minor Si0.5Ge0.5 Fin loss with a sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for STI last scheme is realized by utilizing this new developed STI recess first process.

This paper addresses the opportunities and challenges of wet and dry selective etches in the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for the advanced logic devices. For the GAA device fabrication, a quintessential challenge is a controlled isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the exposed materials. In this paper, the significance of the unit process modules in the GAA device integration: shallow trench isolation (STI), inner spacer formation, replacement metal gate (RMG) and self-aligned interconnect in the middle-of-line (MOL) and the back-end-of-line (BEOL), will be discussed.

The lateral double-diffusion MOS with split shallow trench isolation structure (split-STI LDMOS) in the drift region has been investigated under two hot-carrier stresses including the maximum bulk current stress ( ${I}_{\text {bulkmax}}$ ) and maximum operating gate stress ( ${V}_{\text {gmax}}$ ). For the ${I}_{\text {bulkmax}}$ stress condition, the main damage point causing the degradation of ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is found at the STI corner closest to the source with the interface state generation. In addition, the hot hole injection is found at the edge of the shrinking poly-gate region. For the ${V}_{\text {gmax}}$ stress condition, the main damage point causing the degradation of ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is found at the two STI corners with interface state generation. Due to the more serious degradation of ${R}_{ \mathrm{\scriptscriptstyle ON}}$ , the ${I}_{\text {bulkmax}}$ stress condition is regarded as the worst-case stress condition. The novel structure with the H-shape STI in the drift region is proposed. It is demonstrated that the H-shape STI structure is effectively helpful to alleviate the hot-carrier degradation without altering the tradeoff between the OFF-state breakdown voltage and specific ON-resistance.

This work aimed to quantify the influence of the deposited dose at the hybrid detector ASIC on the resulting image quality. Low ( 932 ± 4 Gy) and high ( 6310 ± 24 Gy) dose experiments were performed by irradiating a Medipix3RX single chip detector with the polychromatic beam from the Brazilian Synchrotron X-ray Imaging beamline. It was possible to evaluate subtle effects by using a noise component model based on estimating the quantum, electronic and structural noise contributions. Visible effects were quantified by analyzing the evolution of the histogram of the pixel counts at the irradiated area. The dose threshold for subtle damages was 388 ± 3 Gy deposited in the gate oxide and shallow trench isolation oxide layers, while visible damages were observed for doses higher than 2635 ± 15 Gy. A recovery of the damaged pixels with time was noticed and quantified, reaching the half-life time at 1.84 ± 0.02 h after irradiation. These results encourage periodical maintenance procedures, for example through a new equalization matrix generation, which proved to be a possible tool for recovering the detector performance.

The impact of the total ionizing dose (TID) on a low energy proton single event upset (SEU) in a 65-nm static random access memory (SRAM) is investigated based on a low energy proton accelerator. The body potential of the P-well is elevated due to charge depletion along the sidewall of shallow trench isolation (STI) induced by TID irradiation. The radiation-induced narrow channel effect causes a decrease in the area and the thickness of the SEU sensitive volume (SV), further resulting in the low energy proton SEU cross section being lowered in 65-nm SRAM with an external independent power supply of the memory array. The impact of the TID on the low energy proton SEU cross section is dependent on test patterns written to the memory array during TID irradiation and SEU testing. The low energy proton SEU cross section is the highest when the complement test pattern is written to the SRAM memory array during TID irradiation and SEU testing compared with the same and half complement patterns.

Shallow Trench Isolation (STI) and Stepped Oxide (SO) -based N-type LDMOS are simultaneously studied for the first time for low-voltage power device in this paper. Ultra-low specific on-resistance (Rsp) can be obtained in both STI- and SO-based LDMOS by scaling channel length (LCH) as well as by using the optimized drift implant. It was indicated that, to some extent, scaling LCH effectively reduces the Rsp without sacrificing breakdown voltage (BV). This is mainly ascribed to the enhanced conducting capability of channel and to the shorter cell pitch. Moreover, drift region was also studied and selected to obtain ultra-low Rsp at no cost of BV. Furthermore, scaling of gate oxide and field oxide are also demonstrated to obtain the best BV-Rsp tradeoff. Finally, it was observed that, for low-voltage LDMOS, STI-based cell exhibits slightly better BV-Rsp tradeoff, compared with SO-based LDMOS due to the shorter cell pitch. However, much better ON-state IDS-VDS characteristics can be achieved in SO-based LDMOS at small expense of Rsp. It was revealed that Rsp of 4.3 mΩ mm2 with a BV of 29.3 V are measured in our planar SO-LDMOS. This Rsp is much lower than earlier published values.

We investigated the total ionizing dose (TID) influence on the single-event multiple-cell upsets (MCUs) in 65-nm 6-T static random-access memory and found that MCU sensitivity of the device is enhanced by TID. MCU caused by particle strike in pMOSFET (p-hits) or nMOSFET (n-hits) is distinguished by the MCU pattern. Analysis of MCU pattern shows that both p-hits MCU and n-hits MCU are enhanced by TID, and they have different mechanisms. Enhancement of n-hits MCU is due to the positive threshold voltage shift ( $\Delta V$ th) of the pull-up pMOSFET, while p-hits MCU is strengthened by the increase in the equivalent resistance of p-well contacts caused by oxide-trapped charges (Not) trapped in the shallow trench isolation.

Soft error effects due to the alpha particle and terrestrial neutron strike are investigated in a saddle fin DRAM using the 3D TCAD simulation. The strike location and angle dependency are investigated, and the worst-case incidence condition is studied. As the strike time is relevant for the error pattern, the strike during the write period is found to have minor effect, but the strike during the hold period shows data corruption. The inter-active disturbance is effectively suppressed due to the shallow trench isolation, but the inter-active ionizing radiation disturbance can be a potential risk as the capacitance of the storage capacitor continues to reduce with the DRAM technology scaling.

Mixed signal on-chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with sufficient ruggedness against ionizing radiation and single event burnout. We report on a novel hardening by design approach for radiation tolerant integrated RF NLDMOS transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease TID induced leakage currents the shallow trench isolation (STI) of MOS transistors was replaced by narrow junction isolated regions. For a significant increase of the SEB onset voltage a cascode arrangement consisting of an isolated NMOS and NLDMOS was chosen. The floating NMOS-drain/NLDMOS-source node in the cascode arrangement is always reverse biased which efficiently avoids a turn-on of the parasitic npn bipolar transistor . The rad-hard isolated NMOS/NLDMOS cascode features a breakdown voltage BVDS > 50 V, a maximum cut off frequency f T = 5 GHz and a maximum oscillation frequency f MAX = 14 GHz. In comparison with standard NLDMOS transistors the isolated NMOS/NLDMOS cascode device shows an increase of the SEB onset voltage from 14V to 30V at a linear energy transfer LET of 67.7 MeVcm2/mg and a negligible increase of source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.

Latch up (LU), an inherent destructive phenomenon owning to P-N-P-N structure in bulk Complementary Metal-Oxide -Silicon (CMOS) circuits, is highly sensitive to pulsed irradiation. A criterion for LU is concluded, and the impact of total ionizing dose (TID) on LU criterion is discussed. In the progress of accumulating TID, generated oxide trapped charges and interface states enhance surface recombination in the base of the parasitic bipolar junction transistor (PBJT), leading to increase of the base recombination current; and the trapped charges in the shallow trench isolation (STI) can also increase leakage current. In spite of hindering effect of the base recombination in PBJTs to LU, the STI leakage current plays a dominant role to gain sensitivity of LU. Experimental results confirm the fact that TID can lower the dose rate threshold for LU. For instance, the threshold in the device with doses 150 krad(Si) is nearly 50% lower than that in the pristine device. Simulations in SPICE and Sentaurus are conducted, and the results agree with that of experiments.

This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of ${n}$ MOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual ${n}$ MOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. We introduce a semiempirical physics-based approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based Enz–Krummenaker–Vittoz (EKV) MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices.

In this paper, we have devised on shallow trench isolation (STI) design considering leakage current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ tendency is considered in terms of the interface trap density ( ${D}_{\textsf {it}}$ ) difference depending on the STI material type and STI thickness. In the case of Bulk FinFET, the STI design for each of high performance (HP) and low power (LP) is presented. On the other hand, in the case of SOI FinFET and VFET, STI designs which do not distinguish HP/LP are presented. Max lattice temperature ( ${T}_{\textsf {L,max}}$ )/thermal resistance ( ${R}_{\textsf {th}}$ )/on current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) degradation rate according to STI design in each structure are also analyzed. Finally, we compare the hot carrier injection (HCI)/bias temperature instability (BTI) lifetime as a function of the device temperature which is varied depending on STI design. In conclusion, our proposed STI design effectively reduces the self-heating effect in each structure and increases the HCI/BTI lifetime accordingly.

In this paper, a dual-gate laterally double-diffused metal–oxide–semiconductor (DG-LDMOS) device with shallow trench isolation (STI) and sinker at the source side has been proposed. STI and sinker help to provide isolation and reduce the leakage current, respectively, in the device. This is an improvement over a single-gate (SG) LDMOS device when only one gate is used and no STI and sinker are there. The study of both the devices has been carried out using the ATLAS SILVACO simulator. In the simulation studies, all the dimensions and doping parameters of both devices have been kept the same except gate length and channel doping. The distance between two gates of DG-LDMOS device has been kept smaller. This has been done to overcome the island and overlapping issues. The simulation studies have shown a significant improvement in DG-LDMOS device parameters in comparison to the SG-LDMOS device. The DG-LDMOS device provides high breakdown voltage, low ON-resistance, high $f_{\sf {T}}$ and $f_{\sf {max}}$ , low drain-induced barrier lowering, and better output conductance as compared to conventional SG-LDMOS device. These features make the DG-LDMOS device an excellent candidate for RF applications.

In this paper, a 5 nm FinFET flow was built using the SEMulator3D® virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated using a built-in drift-diffusion solver. Our analysis has confirmed that larger footings, lower fin heights and larger imbalance fin heights will generate more severe DIBL problems and lead to higher off-state leakage. STI recess with an optimal trenching profile can increase on-state current and reduce off-state leakage.

In 19nm Flash memory process, the aspect ratio of shallow trench isolation (STI) become large and it gets difficult to fill STI Oxide by conventional CVD film. Perhydro-Polysilazance (PSZ) deposition process because of its good filling ability has been evaluated for better STI fill instead of conventional CVD. But this new process can cause cracks because of its high temperature process. Crack defect is inspected by dark field inspection (DFI) tool of KLA. Transmission electron microscope (TEM) is used to study the profile of wafer edge film. The experiment proved that the crack defect is generally decided by STI Etch profile, annealing temperature of rise and drop and the thickness of PSZ DEP. In this paper, solution of to avoid the crack defect are studied.

In this paper, we obtained interface trap density through source-drain CP (charge pumping) current, instead of conventional substrate CP current in MOSFETs and LDMOS. We observed that interface density is same for both source drain CP current and substrate CP current when LOCOS (local oxidation of Silicon) field oxide is used to separate substrate (body) and source in different channel MOSFETs. However, source-drain CP current is higher than substrate CP current when modern STI (shallow trench isolation) is used to separate the substrate and source in different channel MOSFETs. The difference between I ds and I sub is independent on I base voltage. Furthermore, we showed that the source-drain CP current is a useful method for interface traps in LDMOS. We observed that interface traps density is higher in drift region than in channel region in LDMOS.

When a novel dry-etch tool was introduced for the shallow trench isolation (STI) process, it resulted in poorer overlay performance downstream. The patterned wafer geometry (PWG™) tool was utilized to investigate the observed difference in results between the new tool and the POR tool. By using metrics representing process-induced local shape and/or stress, a post-STI oxide fill rapid thermal process (RTP) was identified as the process step where the difference between the dry-etch tools was magnified. An experiment based on RTP temperature and ramp rate was conducted and the effect was evaluated using both GEN4–a predicted shape overlay metric derived from PWG shape measurement–and overlay measurements. Both GEN4 and overlay results indicated that high RTP temperature and low ramp rate could compensate for the process effects introduced by the new etch tool. The strong correlation between GEN4 and overlay also suggested that GEN4 may be a suitable upstream predictor of process-induced overlay excursion in such a case.

This article investigates the total ionizing dose (TID) degradation mechanisms of 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs with several channel lengths are irradiated up to 1 Grad(SiO2) and then annealed for 24 h at 100 degrees C. Irradiated devices show significant degradation in transconductance and OFF-state leakage currents with slight subthreshold stretch-out and negligible threshold voltage shifts. At doses up to 10 Mrad(SiO2), the TID response is dominated by positive trapped charges in the shallow trench isolation (STI). At ultrahigh doses approaching 1 Grad(SiO2), dc static measurements suggest generation of trapped charge at the STI/Si interface and/or at the corner between the STI and the gate dielectric. The TID sensitivity depends on the bias condition and channel length. Halo implantations fortuitously increase the radiation tolerance of short-channel FinFETs due to the increased channel doping caused by the overlap of the source and the drain halos. The worst degradation is found when a high electric field is applied to the gate during irradiation.

Hot-carrier injection causes characteristics change of semiconductor devices. In this work, off-state breakdown voltage (BVdss) degradation of shallow trench isolation (STI) based PchLDMOS under drain avalanche hot-carrier (DAHC) stress has been investigated. We found that the cause of the degradation was a trapped charge at the bottom area of STI rather than STI corner. The mechanism of BVdss degradation was clarified and a tolerant LDMOS structure is proposed.

The results of modeling elements AND and OR as part of the triple majority gate are presented when switching inputs and simultaneously collecting charge from the particle track. The simulation performed using 3D TCAD physical models of CMOS transistors according to the design rule of 65 nm bulk technology with shallow trench isolation of transistor groups for tracks with linear energy transfer of 60 MeV∙cm2/mg. It was found that the beginning of switching elements AND and OR at the inputs practically does not affect the dependence of transient processes of the formation of noise pulses at the output of the element when collecting the charge from the track. The noise pulse shifted in time by a time interval equal to the time offset of the track relative to the moment of switching element inputs. Collecting the charge from the track leads to switching an element in advance of the input signals changing, either, to an additional switching delay (from -91 ps to 620 ps). At the same time, the duration of the noise pulse remains almost unchanged for the each specific track input point into the common area of the transistor location regardless of the moment of formation of the track.

Modelling results for noise pulses forming by logical elements are presented when collecting charge from the single particle tracks with wide range of the linear energy transfer of 10–90 MeV∙cm2/mg. This performs using 3D CAD physical models of CMOS transistors designed on 65 nm bulk technology with shallow trench isolation of transistor groups. The main positive thing that happens when collecting the charge at the linear energy transfer more 40 MeV∙cm2/mg from the track in the group of NMOS transistors belonging to element OR and in the group of PMOS transistors belonging to element AND is holding these transistors in the mode when all transistors are collecting charges. This forms a delay of noise pulses on the outputs of elements and decreases its duration.

It has been recognized that SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture and simplified approach to memory bitmapping [1]. As SRAM transistors are aggressively scaled down, isolation leakage become an important reliability concern shallow trench isolation (STI) continues to scale down. This isolation leakage has to be considered to improve SRAM yield and performance. In FinFET technology, SRAM isolation is mainly dominated by NW CD and STI depth, while single device isolation is mainly impacted by AA to AA space and AA to well space. In this paper, NAA-NAA/NAA-NW/PAA-PAA/PAA-PW four types of isolation are tested to study the NW CD impact to SRAM isolation. STI depth +10 nm and STI depth +20 nm two splits are designed to research its impact to SRAM AA-well isolation. At last, AA to AA space and AA to well space influence to single device is analyzed.

Polysilazane (PSZ) curing has been introduced for 19nm NAND Flash to ensure void free Shallow Trench Isolation (STI) gap fill. PSZ film was converted into oxide mainly depending on temperature and water vapor. The high temperature PSZ curing would give rise to Si dislocation and PSZ crack. However, lowering curing temperature would lead to an insufficient conversion of PSZ film and even generate voids. As a result, wet oxidation was utilized between curing 1 and curing 2 to improve conversion rate of PSZ film. The TEM images showed good gap fill performance of PSZ curing by using low temperature/wet oxidation method.

A lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with ultra-shallow trench isolation (USTI) is proposed in this work. The degradation of device induced by hot-carrier injection (HCI) in n-type LDMOS transistors in the drift region is fully investigated. It revealed that improvement of the relationship between the breakdown and specific on-resistance can be obtained without sacrificing of HCI degradation. Additionally, the physical mechanism behind the results is also analyzed from the technology computer-aided-design (TCAD) simulation.

Shallow trench isolation chemical mechanical polishing (STI CMP) technology has been widely applied in the fabrication of ultra large scale integrated (ULSI). In STI CMP, the defect, topography control, thickness uniformity and so on are all so critical, especially, scratch defect is the major problem. Pad, disk, agglomerated slurry particles and incoming particles are the main sources of the tiny scratch. In this paper, we conducted a detailed study on the influence of one-step AA pull back process on the bevel region of wafer, which led to the introduction of incoming particles and ultimately led to the increase of STI CMP scratch. It was find that by adding a brush bevel process before STI CMP can reduce the scratch by 66%.

We investigated MOSFET shallow trench isolation (STI) process with SIN liner and found no “double hump” effect in the Id-Vg curves and solution leakage. Furthermore, the yield was good in the memory. In the STI corners, a sharp angle was jacked up by SIN. Although the yield result was very good, it was still a hidden danger and could affect GOX. We utilized the high-density plasma chemical vapor deposition (HDP-CVD) process to clip a certain number of SiN liners. From the experiment results, we found that SiN liner and sidewall oxidation significantly improved the time-dependent dielectric breakdown (TDDB).as a result of test, new technology does not generate hot carrier injection (HCI) effects.

Single photon avalanche diodes (SPADs) manufactured through the standard CMOS process have a major advantage in reducing the cost and expendability in comparison with the SPAD made with the custom process. SPAD is a single photon sensitive diode using the avalanche phenomenon and operated in Geiger-mode which applies a voltage higher than the breakdown voltage of the device. Therefore, SPAD is exposed to a higher voltage than other devices and has a high electric field in the multiplication region. In SPAD operating with such a high electric field, the guard ring prevents edge breakdown and serves to focus the electric field on the intended multiplication region. Therefore, the optimized guard ring structure is required for the high efficiency SPAD designs. The deep virtual guard ring is designed to cope with deeper multiplication regions formed by deep n-well and p-well, thus providing higher photon detection probability (PDP) and enhanced response at a longer wavelength. In this paper, the four possible Silicon-based SPAD candidates of different deep virtual guard rings formed by the combination of shallow trench isolation (STI) and p-substrate layer fabricated through standard CMOS process are investigated and their electric characteristics of the SPAD, such as the current-voltage (I-V) characteristic, and optical characteristics, such as dark count rate (DCR), and PDP, are measured. In addition, TCAD simulations are used to verify the characteristic variation by analyzing the electric field profiles. Based on the results, the optimized structure of the SPAD with the deep virtual guard ring can be proposed.

Dark current (DC) limits the optical performance of CMOS image sensors. The main sources of the DC in a modern submicrometer process are the defects induced by the shallow trench isolation fabrication process steps. In this brief, we present a pixel layout technique to reduce the impact of these defects by removing the trench-oxide between the two adjacent edges of neighboring photodiodes (PDs). This isolation scheme relies only on the p-well layer and provides the further advantage of requiring less area. Hence, a larger PD can be designed, leading to an increased pixel fill factor. Experimental results show that this approach reduces the DC by 21% and increases the linear full well capacity by approximately 9%.

Total ionizing dose (TID) mechanisms are investigated in 28-nm MOSFETs via dc static and low-frequency noise measurements. nMOSFETs and pMOSFETs are irradiated up to 1 Grad(SiO2) and annealed at high temperatures. TID sensitivity depends on the channel length, the channel width, and the bias condition. Halo implantations improve the radiation tolerance of shorter-channel transistors. Worst case bias for TID-induced degradation is found with high electric field applied to the gate during irradiation, due to increased charge trapping in the upper corner of the shallow trench isolation (STI) and in the gate oxide. DC and low-frequency noise measurements show that, at doses up to similar to 100 Mrad(SiO2), radiation-induced degradation is primarily due to the positive charge buildup in the STI oxides. At ultrahigh doses approaching 1 Grad(SiO2), TID degradation is influenced by charge buildup in the gate oxide and traps at or near the gate/dielectric interface and/or along the STI sidewalls. Worst case degradation is found in narrower and longer-channel devices, due to the enhanced charge buildup in the STI oxide and along its interfaces.

This paper presents an approach for analyzing stress in 2-D and 3-D integrated circuits (ICs) due to postmanufacturing thermal mismatch. For both 2D-ICs and 3D-ICs, shallow trench isolation (STI) induces thermal residual stress in active silicon. For 3D-ICs, through-silicon vias (TSVs) act as an additional source of stress. Together, the sources of stress cause changes in the delay and power of the circuit. We develop an analytical model based on inclusion theory in micromechanics to accurately estimate the stresses and strains induced in the active region by surrounding STI in a layout. The TSV-induced stress depends on the location of the transistor with respect to the TSVs. Therefore, these stresses result in placement-dependent variations in the transistor mobilities and threshold voltages of the active devices, and we propagate these effects to circuit-level performance. At the transistor level, the stress state is translated into mobility and threshold voltage variations using piezoresistivity and band deformation potential models, respectively. At the gate level, the computed changes in transistor electrical parameters are used to predict gate-level delay and leakage power changes for single-fingered and multifingered layout styles, which are subsequently used to predict circuit-level delay and leakage power for a given placement.

A novel Lateral Double-diffused MOS (LDMOS) with an H-shape shallow-trench-isolation (STI) structure is experimentally proposed in this brief. The H-shaped STI can enhance the dielectric reduced-surface-field effect to the n-drift region from multiple directions, making the n-drift deplete more adequately. In this manner, the peak electrical field and the impact ionization rate along the device surface under high drain voltage are clearly decreased, while an additional short current path near the device surface can still be retained. As a result, when the 52-V breakdown voltage is kept, a competitive specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ) of 23.9 $\text{m}\Omega \cdot \text {mm}^{\textsf {2}}$ is experimentally achieved using a 0.18- $\mu \text{m}$ BCD process, representing a decrease of 10.5% and 15.9% compared with the conventional split-STI LDMOS and full-STI LDMOS, respectively. The idea can also be generalized to more advanced process nodes.

The n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) produced in the widely used CMOS bulk process takes radiation damage by the total ionizing dose (TID) effects in radiation environments, so the radiation-tolerant properties of semiconductor integrated-circuits (ICs) used in high-radiation environments is a critical issue. The formation method of the isolation oxide module (IOM), which induces the radiation-induced leakage currents, differs depending on the chip density of the CMOS bulk process. In this paper, we designed and fabricated I-gate n-MOSFETs for bulk process and analyzed the radiation-tolerant characteristics according to IOM. The I-gate n-MOSFET chips are fabricated using the shallow trench isolation (STI) 0.18um and local oxidation of silicon (LOCOS) 0.35um processes of the CMOS bulk process. Tests and evaluation of the TID effects on the chips are carried out by irradiating a total cumulative dose up to 2 Mrad(Si). As the results, in the standard n-MOSFET, the leakage currents of the LOCOS and STI processes are 27.7uA and 16.4uA, and in I-gate n-MOSEFT, are 1.1uA and 0.7uA. The leakage currents of standard n-MOSFET increased by about 25 times before and after irradiation, but the electric characteristics of I-gate n-MOSFET is maintained regardless of the process. Therefore, the process versatility of the I-gate n-MOSFET with the radiation-tolerant performance has been verified.

The electrical characteristics of bulk nFinFETs after total-ionizing-dose (TID) irradiation were experimentally evaluated with respect to the process variation (PV). The inconsistent transfer characteristics, particularly the different threshold voltage shifts under an identical bias condition and irradiation dose, were investigated through technology computer aided design (TCAD) simulation, considering the shallow trench isolation (STI) footing and the asymmetrical sidewall. The influence that the bias condition had, as an important factor including ON, OFF, and transmission gate (TG), is included in this paper to better illustrate the PV dependence. The HfO 2 high-ĸ metal gate, the STI, and the PV dependent geometry were some of the influences that occurred within the degradation of electrical performances as the TID increased. A radiation-hardness strategy was proposed in order to improve the electrical properties of the FinFET devices in the radiation environments.

The total ionizing dose response of bulk nFinFETs with multiple gate lengths and multiple fins is investigated for on-state bias condition. Experiments and Technology Computer Aided Design simulations were performed to analyze the effect of the trapped charges in the gate oxide and shallow trench isolation (STI) oxide on the threshold voltage and transconductance of the devices. The increases in the threshold voltage and transconductance are observed after X-ray irradiation. The positive shift of the threshold voltage is caused by the net negative charges trapped in the gate oxide. The simulation results show that the trapped holes in the STI oxide reduce the electric field and increase the electron mobility in channel near the fin bottom, which is the major contribution to the increased transconductance. An interesting phenomenon was also observed that the threshold voltage continues to increase during the annealing process, whereas the transconductance decreases. These results suggest that there may also be a small amount of trapped holes in gate oxide during irradiation, and those trapped holes are compensated by electrons transporting from the silicon during the anneal, leading to further positive shift of the threshold voltage. Moreover, the decrease in transconductance is mainly introduced by the neutralization of the trapped holes at STI/silicon interface.

Nanoscale complementary metal–oxide–semiconductor (CMOS) circuit design extensively employs multifinger layout technique to alleviate the performance degrading parasitic and mismatch effects that are typically observed with single-finger layout. However, a continuous increase in the number of fingers accompanied by a simultaneous decrease in their finger width could lead to the penalty of a higher degree of variation in the MOSFET's small-signal parameters. It is due to the heightened shallow trench isolation (STI) stress that gets developed in such devices. The optimisation of circuit performance with the arbitrarily fixed number and width of fingers would be ambiguous. In this work, an analysis of current–voltage ( I – V ) characteristics of a MOSFET as a function of number of fingers has been proposed. It was found that both the drain current and gate transconductance get affected by the number of fingers. The authors proposed a Miller-compensated two-stage [operational transconductance amplifier (OTA)] and common source amplifier by considering STI effect. It is also found that the parameters of the proposed design matched well with the set of desired specifications. Also, the area of multifinger MOSFET OTA is lowered by up to 60% relative to that from the conventional. All post-layout simulations were performed using standard UMC 65 nm CMOS technology.

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.

Two radiation hardening processes for shallow trench isolation (STI), i.e., Si+ implantation and STI oxide nitridation are investigated, including the impact on nominal electrical characteristics and radiation hardness. The total ionizing dose effects of the nMOS devices are proved to be sensitive to the STI radiation hardening process conditions. There are optimum process conditions to achieve the best effectiveness of radiation hardening. Then, a 130-nm radiation-hardened PDSOI technology has been developed. The radiation hardness is verified by static random access memories with small storage capacities.

It has demonstrated to exploit various layout effects of advanced strained engineering to enhanced the performance of nano-scaled transistors. In actual fabrications, the gate framework usually protrudes out to the channel area even over the spuriously diffused active region, over the soft shallow trench isolation region. The foregoing device feature is interesting and critical when enhancing and managing mobility gain are taken into account by used mechanics and induced strained silicon technology in narrow scale channel widths devices. Thus, a silicon-based 22 nm p-type MOSFET combined stressors of a source/drain Si75Ge25 alloy and a -2 GPa compressive contact etch stop layer with different protrudent gate widths to investigate this issue. The fabricated oriented stress simulation extracted stress component within the device channel to estimate and analyze the performance of mobility gain and stress contours for the concerned nanoscale device.