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Line width roughness (LWR) is one of the most critical performance indexes for low k1 ArF immersion Lithography. Several factors are impacting LWR performance during Lithography process, such as structures, anti-reflective coating (ARC), photoresist, baking condition, illumination condition and track process. However, the structures and ARCs are strongly related to integration and Etch processes. The illumination conditions, including mask bias, are decided by simulation software but the track condition usually follows the pervious node at initial step normally. Therefore, it sometimes shows poor results because of the difference of the under-layer condition. For example, it has been uncovered that LWR and local CD uniformity (LCDU) became worse while structure changed to Carbon-DARC-Resist (CDR) from Multi-Layer Resist (MLR). Generally, photoresist evaluation with baking condition optimization is a typical way to improve LWR performance. The photoresist formulation contains photosensitive polymers, photoacid generators (PAGs), quenchers, additives, and solvents. Based on photoresist's point of view, the first two are the most important factors of LWR performance control. Several designs of experiments (DOEs) were planned with polymers, PAGs, and PEB conditions. The target is to achieve LWR of CDR under the result of MLR. In this paper, Polymer DOE1 and its statistical analyses have finished. Compared to de-composition efficiency of each unit, small protection unit and PEB effect are the most important factors, and bulky protection unit shows less influence for LWR improvement. Small protection unit is more important than bulky protection unit, and high Ea monomers of both are good for LWR. Based on previous experiences, we have chosen the acid diffusion length / amount of PAG and PEB temperature for PAG DOE2 plan. Higher PEB is the most effective to LWR. Shorter diffusion length PAG with fewer loading amounts is better for MEEF and EL by DOE2 result. The final DOE3 is combined by optimized polymers by DOE1 and optimized PAG by DOE2. The polymer is used DOE1 Tr2, DOE1 Tr4, and estimated new polymer by DOE1 result, and the PAG is chosen shorter diffusion PAG-O with the split of loading amount and PEB temperature. Based on the statistical analyses of DOE3 result, higher PEB temperature is still the most effective to LWR, and new polymer and DOE1 Tr2 polymer are better for LWR reduction. However, higher PEB temperature would suffer a little bit of DOF, EL, and MEEF. In order to achieve the lower LWR, it needs to use DOE1 Tr2 polymer with higher PEB, but insufficient DOE and MEEF would get at the same time. New polymer by DOE1 combined fewer PAG-O loading amount with lower PEB could get slower sensitivity for all Litho index's requirements. Through DOE works, we found out the volume of protection unit and PEB were key factors for good LWR. However, these factors are trades off DOF, EL, and MEEF against LWR, and they need to optimize for the best balanced Litho performances.

As the feature sizes continue to shrink, more overlay metrology data are needed to meet tighter overlay specifications which ensure high device yield. This study investigates the advantages of process corrections to overlay errors using various reduced measurement wafer schemes, and the improvement in yield that is realized using optimized overlay correction models. The capacitor layer of a 4x node DRAM product is chosen for verifying the sampling schemes in the experiment, because overlay errors of this layer are sensitive to device yield. The test wafers are split into five groups; four groups are sampled using various schemes and overlay correction models, and one group has a programmed overlay error. The post-correction overlay residuals in full wafer, baseline sampling and optimized sampling agree closely with predictions that are based on raw measurements. A scheme with iHOPC (intrafield high order process correction) partial third-order terms with a CPE (correction per exposure) function provides the best overlay performance. The averaged device yields of reduced sampling schemes are comparable with those of the full wafer scheme, however the reduction of the number of measurements that is made in optimized sampling reduce the metrology tool time by 26% from that required using the current scheme of factory. Therefore, the cost of metrology can be further reduced by applying the proposed optimized sampling map in the routine operations of fab.

As lithography moves into lower k1imaging, traditional illumination "source" shapes may perform marginally in resolving complex layouts. Subsequently hot-spots or warm-spots can result, leading to yield loss in production. Typically, lithographers solve such problems by modifying the local layout instead of optimizing the DOE (diffractive optical element) illumination shape. FlexRayTMcan easily implement freeform source shapes and allows a high degree of freedom in source optimization. Therefore, it becomes practical to use pixelated freeform sources to resolve hot spots or warm spots. In this paper, we investigate the use of freeform source optimization (SO) on a critical dynamic random access memory (DRAM) layer with warm spots to verify the effectiveness of a SO only flow using Tachyon SMO. In order to improve the warm spots without changing baseline performance for other patterns, we optimized not only the warm spot patterns of concern but also the critical reference patterns. Since the optimization minimizes EPE (edge placement error) and maximizes imaging quality for all enclosed patterns, the final optimized source shape performs similar to the baseline source for the base patterns while improving the performance of the warm spot pattern areas. Although the SO source is similar in shape to the baseline source, the optimized source provides enhanced depth of focus (DoF) for all warm spot patterns without suffering degradation in the normalized image log-slope (NILS) performance. Evaluation of the optimized SO source shows no obvious negative impact on modeled CDs across an array of L/S pattern combinations which cover all the pitches appearing in the periphery. Finally, the optimized source is demonstrated using ASML's FlexRayTMfor on-wafer evaluation. According to the observations from on-wafer experiments, consistent results to simulation are verified. Overall DoF for the identified warm spot patterns is definitely improved and no obvious pattern shape changes are found, as well. From the positive demonstration in simulation and on-wafer verification, the vast flexibility of the freeform source enables the SO flow with more powerful capability to improve local hot spot or warm spot problems without negatively impacting the other patterns.

It is known that different overlay mark designs will have different responses to process setup conditions. An overlay mark optimized for the 45nm technology node might not be suitable for wafers using 30nm or 20nm process technologies due to changes in lithography and process conditions. As overlay control specifications become tighter and tighter, the process engineer requires metrics beyond precision, tool-induced shift (TIS) and TIS variability to determine the optimal target design. In this paper, the authors demonstrate a novel, comprehensive methodology which employs source of variance (SOV) to help engineers select the best overlay marks to meet overlay control requirements.

As is well recognized, source mask optimization (SMO) is a highly effective means of extending the lifetime of a certain photolithography generation without an expensive upgrade to the next generation optical system. More than an academic theory, source optimization first found practical applications in the debut of the pixel-like programmable illuminator in 2009 for producing near freeform illumination. Based on programmed illumination, related studies have demonstrated a nearly identical optical performance to that generated by the conventionally adopted diffractive optical element (DOE) device without the prolonged manufacturing time and relatively high cost of stocking up various DOEs. By using a commercially available pixel-like programmable illuminator from ASML, i.e. the FlexRay, this study investigates the effectiveness of FlexRay in enhancing image contrast and common process window. Before wafer exposure, full SMO and source-only (SO) optimization are implemented by Tachyon SMO software to select the optimum illumination source. Wafer exposure is performed by ASML XT:1950i scanner equipped with a FlexRay illuminator on a critical layer of DRAM process with known hotspots of resist peeling. Pupil information is collected by a sensor embedded in the scanner to confirm the produced source shape against the programmed source and the optically simulated CD. When the FlexRay illuminator is used, experimental results indicate that lithography hotspots are eliminated and depth of focus is improved by as much as 50% in comparison with those from a traditional AERIAL illuminator. Regular focus-exposure matrix (FEM) and the subsequent critical defects scanning reveal that the common process window of the tight-pitched array and the periphery can be enhanced simultaneously with no hotspot identified. Therefore, a programmed source is undoubtedly invaluable in terms of additional manufacturing flexibility and lower cost of ownership when attempting to improve product yield in high volume production.