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International audience; To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

International audience

As device integration density increases exponentially as predicted by Moore’s law, power consumption becomes a bottleneck for system scaling where leakage power of on-chip cache occupies a large fraction of the total power budget. Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate to replace static random access memory (SRAM) as an on-chip last level cache (LLC) due to its ultralow leakage power, high integration density, and nonvolatility. Moreover, with the prevalence of edge computing and Internet-of-Things (IoT) applications, it can be beneficial to build a total nonvolatile cache hierarchy, including the L1 cache. However, building an L1 cache with STT-MRAM still faces severe challenges particularly because reducing its relatively high write latency by increasing write voltage can accelerate oxide breakdown of the MTJ device and threaten the L1 cache lifetime significantly due to intensive accesses. In our previous work, we proposed a dynamic overwriting voltage adjustment (DOVA) technique to deal with this challenge. In this article, we improve this technique by a DOVA promotion (DOVA PRO) technique for the STT-MRAM L1 cache, considering the cache write endurance and performance simultaneously. A high write voltage is used for performance-critical cache lines, while a low write voltage is used for other cache lines to approach an optimal tradeoff between reliability and performance. Experimental results show that the proposed technique DOVA PRO can improve cache performance by 23.5%, on average, compared to the DOVA technique. In the meantime, the average degradation of cache lifetime remains almost unchanged compared with the DOVA technique on average. Furthermore, DOVA PRO can support flexible configurations to achieve various optimization targets, such as higher performance or a longer lifetime.

This study investigates the response of synchronous dynamic random access memories to energetic electrons and especially the possibility of electrons to cause stuck bits in these memories. Three different memories with different node sizes (63, 72, and 110 nm) were tested. Electrons with energies between 6 and 200 MeV were used at RADiation Effects Facility (RADEF) in Jyvaskyla, Finland, and at Very energetic Electron facility for Space Planetary Exploration missions in harsh Radiative environments (VESPER) in The European Organization for Nuclear Research (CERN), Switzerland. Photon irradiation was also performed in Jyvaskyla. In these irradiation tests, stuck bits originating from electron-induced single-event effects (SEEs) were found, as well as single bit-flips from single electrons. To the best knowledge of the authors, this is the first time that stuck bits from single-electron events have been reported in the literature. It is argued in the article that the single-event bit-flips and stuck bits are caused by the same damage mechanism, which would be large displacement damage clusters, and that the two different fault modes represent different amounts of damage to the memory cell. After a large particle fluence, a rapid increase in the error rate was observed, originating from the accumulation of smaller displacement damage clusters in the memory cells. The 110-nm memory was a candidate component to fly on the European Space Agency (ESA) JUpiter ICy moons Explorer (JUICE) mission, so the SEE cross section as a function of electron energy was compared to the expected electron environment encountered by JUICE to estimate the error rates during the mission.

International audience; Optoelectronic components are the most sensitive devices of systems exposed to radiation environments. Displacement damage (DD) effects can severely degrade the performances of such devices, which are extensively used in critical electronic systems installed in particle accelerators or nuclear power plants. This work investigates the use of application-specific radiation spectra for damage estimations in operation instead of mono-energetic proton or neutron irradiations. An analysis of the characteristics of the Large Hadron Collider (LHC) radiation environment in terms of DD is presented in this work along with the demonstration of the ability of the CERN High Energy Accelerator Mixed Field (CHARM) facility of CERN to reproduce them. Then, a set of optocouplers made of gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs) are tested under these environments, and the results are compared to proton and neutron irradiations.

International audience; First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

International audience; Selecting the ideal trade-off between reliability improvement and cost (i.e., area, timing and power overhead) associated with a fault tolerant architecture generally requires an extensive Design Space Exploration. In this paper, we present a feasibility study that addresses the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Four different selective hardening methods have been investigated and compared: i) a full duplication scheme, ii) a reduced duplication scheme based on a structural susceptibility analysis, iii) a reduced duplication scheme based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication scheme that uses an approximate version of the arithmetic circuit. Experimental results performed on adder and multiplier case studies demonstrate the interest of using approximate structures in a duplication scheme since they provide much better error detection capability than other selective hardening methods with lower area and power overheads. Note that all experiments have been done without considering the area and power overhead due to the comparators. This may slightly biased the results from a quantitative point of view, although it does not jeopardize the main conclusion about the interest of using approximate structures as duplication scheme. Moreover, validations using a gate-level fault injection campaign have shown that approximate structures offer a better reliability level compared to the other considered duplication scenarios.

International audience; Convolutional Neural Networks (CNNs) are currently one of the most widely used predictive models in machine learning. Recent studies have demonstrated that hardware faults induced by radiation fields, including cosmic rays, may significantly impact the CNN inference leading to wrong predictions. Therefore, ensuring the reliability of CNNs is crucial, especially for safety-critical systems. In the literature, several works propose reliability assessments of CNNs mainly based on statistically injected faults. This work presents a software emulator capable of injecting real faults retrieved from radiation tests. Specifically, from the device characterisation of a DRAM memory, we extracted event rates and fault models. The software emulator can reproduce their incidence and access their effect on CNN applications with a reliability assessment precision close to the physical one. Radiation-based physical injections and emulator-based injections are performed on three CNNs (LeNet-5) exploiting different data representations. Their outcomes are compared, and the software results evidence that the emulator is able to reproduce the faulty behaviours observed during the radiation tests for the targeted CNNs. This approach leads to a more concise use of radiation experiments since the extracted fault models can be reused to explore different scenarios (e.g., impact on a different application).

International audience; The field of radiation effects in electronics research includes unknowns for every new device, node size, and technical development. In this study, static and dynamic test methods were used to define the response of a self-refresh DRAM under neutron irradiation. The neutron-induced effects were investigated and characterised by event cross sections, soft-error rate, and bitmaps evaluations, leading to an identification of permanent and temporary stuck cells, single-bit upsets, and block errors. Block errors were identified in different patterns with dependency in the addressing order, leading to up to two thousand faulty words per event, representing a real threat from a user perspective, especially in critical applications. An analysis of the damaged cells’ retention time was performed, showing a difference in the efficiency of the self-refresh mechanism and a read operation. Also, a correlation of the fault mechanism that generates both single-bit upsets and stuck bits is proposed. Post- irradiation high-temperature annealing procedures were applied, showing a recovery behaviour on the damaged cells.

International audience; Error Vector Magnitude (EVM) or alternately Offset Error Vector Magnitude (OEVM) is one of the most important performance to verify for RF circuits such as ZigBee transmitters in order to ensure that the quality of the generated modulated-signal complies with the requirements of the wireless communication standard. The conventional solution to measure this performance relies on the use of an Automatic Test Equipment (ATE) equipped with expensive RF channels. This paper presents a low-cost solution that permits to realize EVM measurement using only a standard digital ATE. The approach is based on 1-bit under-sampled acquisition of the RF modulatedsignal by a digital tester channel associated with a specificallytailored processing algorithm. This algorithm involves many different steps that are detailed in this paper, including phase and amplitude fluctuation extraction, RF signal reconstruction, symbol clock recovery, symbol bits detection and synthesis of reference data for EVM calculation. The proposed digital test solution is first evaluated through lab hardware experiments and then validated with EVM measurements on an industrial ATE.

International audience; Multi-Level Cell (MLC) technology can greatly reduce Resistive RAM (RRAM) die sizes to achieve a breakthrough in cost structure. In this paper, a novel design scheme is proposed to realize reliable and uniform MLC RRAM operation without the need of any read verification. MLC is implemented based on a strict control of the cell programming currents of 1T-1R HfO 2 -based RRAM cells. Specifically, a self-adaptive write termination circuit is proposed to control the RRAM RESET current. Eight different resistance states are obtained by varying the compliance current which is defined as the minimal current allowed by the termination circuit in the RESET direction.

International audience; In the last years, the adoption of Artificial Neural Networks (ANNs) in safety-critical applications has required an in-depth study of their reliability. For this reason, the research community has shown a growing interest in understanding the robustness of artificial computing models to hardware faults. Indeed, several recent studies have demonstrated that hardware faults induced by an external perturbation or due to silicon wear out and aging effects can significantly impact the ANN inference leading to wrong predictions. This work classifies and analyses the principal reliability assessment methodologies based on Fault Injection at different abstraction levels and with different procedures. Some of the most representative academic and industrial works proposed in the literature are described and the principal advantages, and drawbacks are highlighted.

International audience; This paper presents a benchmarking methodology to analyse the failure mechanisms of FPGAs under radiation, using comparative results on the radiation sensitivity of parallel multipliers with different implementations. Atmospheric neutron beam test results of Artix7, Spartan7 and IGLOO2 FPGAs are presented and validated against fault injection campaigns.

International audience; RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation with- out the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell program- ming current of 1T-1R HfO2-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 μs, respectively.

International audience; The globalized supply chain in the semiconductor industry raises several security concerns such as IC overproduction, intellectual property piracy and design tampering. Logic locking has emerged as a Design-for-Trust countermeasure to address these issues. Original logic locking proposals provide a high degree of output corruption-i.e., errors on circuit outputsunless it is unlocked with the correct key. This is a prerequisite for making a manufactured circuit unusable without the designer's intervention. Since the introduction of SAT-based attacks-highly efficient attacks for retrieving the correct key from an oracle and the corresponding locked design-resulting design-based countermeasures have compromised output corruption for the benefit of better resilience against such attacks. Our proposed logic locking scheme, referred to as SKG-Lock, aims to thwart SAT-based attacks while maintaining significant output corruption. The proposed provable SAT-resilience scheme is based on the novel concept of decoy key-inputs. Compared with recent related works, SKG-Lock provides higher output corruption, while having high resistance to evaluated attacks.

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.