428 results on '"TEST (TEST)"'
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52. test headline
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Test, Test
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Architecture and design industries ,Retail industry - Abstract
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53. test
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Test, Test, primary
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- 2016
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54. Test
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Test
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55. test
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56. Fortführung der Wissenschaftsplattform http://forschung.oekolandbau.de
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test, test and test, test
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Ziel des Projekts ist die Verbesserung der Forschungskommunikation und des Wissenstransfers im ökologischen Landbau. Neben der laufenden Aktualisierung der Wissenschaftsplattform (http://forschung.oekolandbau.de) als nationale Informationsdrehscheibe zur Forschung im ökologischen Landbau liegt ein Schwerpunkt auf der Archivierung, Bekanntmachung und Aufbereitung von Forschungsergebnissen, die im Rahmen des Bundesprogramms Ökologischer Landbau (BÖL) erarbeitet wurden. Dazu werden alle Schlussberichte zu F&E-Vorhaben aus dem BÖL in der Datenbank Organic Eprints archiviert und über eine Nachricht auf der Wissenschaftsplattform bekannt gemacht. Ausgewählte praxisrelevante Schlussberichte werden zur Einbindung in das Zentrale Internetportal www.oekolandbau.de aufbereitet. Die Betreuung der Datenbank Organic Eprints umfasst unter anderem die Bereitstellung einer Helpline (Mail, Telefon) sowie die Qualitätssicherung von Einträgen. Die Projektergebnisse werden kontinuierlich über das Internet sowie über einen monatlich erscheinenden Newsletter zur Verfügung gestellt.
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57. Notes for Contributors
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Test, Test Test, primary
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58. JOLANTA PALIDAUSKAITĖ
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Test, Test Test, primary
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59. Kronika
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Test, Test Test, primary
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60. Notes on Contributors
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Test, Test Test, primary
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61. Requirements for the Articles to be Published in ‘Social Sciences’
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Test, Test Test, primary
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62. Editorial Note
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Test, Test Test, primary
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63. Requirements for the preparation of an article
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Test, Test Test, primary
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64. Chronicle
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Test, Test Test, primary
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65. Requirements for the Article to be Published, Requirements for the Electronic From of an Article
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Test, Test Test, primary
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66. Information about article authors
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67. test
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68. Test
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69. Abstract Test
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70. test
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Test, Test, primary
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- 2009
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71. test
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test, test, primary, Lewczuk, J, additional, Ziolkowsk, D, additional, and Bulicki, Ł, additional
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- 2007
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72. Test 2
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Test, Test
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Testing ,Business ,Business, general - Abstract
Test 2. The quick brown fox jumped over the lazy dog. The quick brown fox jumped over the lazy dog. The quick brown fox jumped over the lazy dog. The quick brown fox jumped over the lazy dog.
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- 1999
73. test
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Test, Test, primary
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74. Test
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Test, Test and Test, Test
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- 1990
75. tes
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test, test, primary
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- 1996
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76. An Ecological Perspective on Assessment and Treatment of Aphasia
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test, test, LaPointe, Leonard L., test, test, and LaPointe, Leonard L.
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TBA
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- 1989
77. Zippy
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test, test
78. Zippy
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test, test and test, test
79. Zippy
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test, test and test, test
80. WITHDRAWN: TEST
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TEST, TEST, primary
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- 1922
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81. test
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test, test, primary
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82. Notes for Contributors
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Test, Test test, primary
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83. TEST title
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84. Test Test Test Yah.
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Test, Test
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Test Test Test ..PAT.-Unpublished Manuscript [ABSTRACT FROM AUTHOR]
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- 2010
85. Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications
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Tianming Ni, Xiaoqing Wen, Aoran Cao, Patrick Girard, Zhelong Xu, Jie Cui, Aibin Yan, Anhui University [Hefei], Anhui Polytechnic University, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and Kyushu Institute of Technology
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Cost effectiveness ,Computer science ,Clock gating ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,soft error ,7. Clean energy ,law.invention ,double-node-upset ,Reliability (semiconductor) ,law ,0202 electrical engineering, electronic engineering, information engineering ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,Flip-flop ,business.industry ,020208 electrical & electronic engineering ,Transistor ,Electrical engineering ,Radiation hardening ,020206 networking & telecommunications ,Power (physics) ,latch design ,Inverter ,Node (circuits) ,business ,flipflop design ,Hardware_LOGICDESIGN - Abstract
International audience; To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.
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- 2021
86. Space Radiation Effects in Electronics
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Dilillo, Luigi, Bosser, Alexandre Louis, Javanainen, Arto, Virtanen, Ari, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
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[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,ComputingMilieux_MISCELLANEOUS - Abstract
International audience
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- 2022
87. DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect
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Xiaochen Guo, Yuanqing Cheng, Patrick Girard, Chengcheng Lu, Jiacheng Ni, Jinbo Chen, School of Electronics and Information Engineering, Beihang University, 100191 Beijing, China, Beihang University (BUAA), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and School of Integrated Circuit Science and Technology [Beihang Univ] (SME BUAA)
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CPU cache ,Computer science ,02 engineering and technology ,Power budget ,Bottleneck ,automatic write-back ,0202 electrical engineering, electronic engineering, information engineering ,Breakdown voltage ,Static random-access memory ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Electrical and Electronic Engineering ,signature improvement ,Magnetoresistive random-access memory ,Hardware_MEMORYSTRUCTURES ,business.industry ,physical unclonable function (PUF) ,020202 computer hardware & architecture ,ComputingMilieux_MANAGEMENTOFCOMPUTINGANDINFORMATIONSYSTEMS ,13. Climate action ,Hardware and Architecture ,Embedded system ,hardware security ,Cache ,Spin-Transfer Torque magnetic Cell (STT-mCell) ,business ,Software ,Voltage - Abstract
As device integration density increases exponentially as predicted by Moore’s law, power consumption becomes a bottleneck for system scaling where leakage power of on-chip cache occupies a large fraction of the total power budget. Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate to replace static random access memory (SRAM) as an on-chip last level cache (LLC) due to its ultralow leakage power, high integration density, and nonvolatility. Moreover, with the prevalence of edge computing and Internet-of-Things (IoT) applications, it can be beneficial to build a total nonvolatile cache hierarchy, including the L1 cache. However, building an L1 cache with STT-MRAM still faces severe challenges particularly because reducing its relatively high write latency by increasing write voltage can accelerate oxide breakdown of the MTJ device and threaten the L1 cache lifetime significantly due to intensive accesses. In our previous work, we proposed a dynamic overwriting voltage adjustment (DOVA) technique to deal with this challenge. In this article, we improve this technique by a DOVA promotion (DOVA PRO) technique for the STT-MRAM L1 cache, considering the cache write endurance and performance simultaneously. A high write voltage is used for performance-critical cache lines, while a low write voltage is used for other cache lines to approach an optimal tradeoff between reliability and performance. Experimental results show that the proposed technique DOVA PRO can improve cache performance by 23.5%, on average, compared to the DOVA technique. In the meantime, the average degradation of cache lifetime remains almost unchanged compared with the DOVA technique on average. Furthermore, DOVA PRO can support flexible configurations to achieve various optimization targets, such as higher performance or a longer lifetime.
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- 2021
88. Electron-Induced Upsets and Stuck Bits in SDRAMs in the Jovian Environment
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Lucas Matana Luza, Arto Javanainen, Wilfrid Farabolini, Antonio Gilardi, Christian Poivey, Luigi Dilillo, Daniel Soderstrom, Heikki Kettunen, Andrea Coronetti, University of Jyväskylä (JYU), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), European Organization for Nuclear Research (CERN), Dipartimento di Ingegneria Elettrica e delle Tecnologie dell'Informazione [Napoli] (DIETI), Università degli studi di Napoli Federico II, European Space Agency (ESA), European Project: 721624,RADSAGA, Department of Physics [Jyväskylä Univ] (JYU), CERN [Genève], Dilillo, Luigi, Test and dEpendability of microelectronic integrated SysTems (TEST), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), University of Naples Federico II = Università degli studi di Napoli Federico II, and Agence Spatiale Européenne = European Space Agency (ESA)
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Nuclear and High Energy Physics ,[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,käyttömuistit ,Hardware_PERFORMANCEANDRELIABILITY ,Electron ,Radiation ,elektronit ,01 natural sciences ,Jovian ,elektroniikkakomponentit ,Electron radiation ,Jupiter ,electron radiation ,0103 physical sciences ,Radiative transfer ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Electrical and Electronic Engineering ,avaruustekniikka ,Physics ,Hardware_MEMORYSTRUCTURES ,Large Hadron Collider ,010308 nuclear & particles physics ,ionisoiva säteily ,stuck bits ,[SPI.TRON] Engineering Sciences [physics]/Electronics ,[INFO.INFO-ES] Computer Science [cs]/Embedded Systems ,total ionizing dose ,[SPI.TRON]Engineering Sciences [physics]/Electronics ,Computational physics ,säteilyfysiikka ,Nuclear Energy and Engineering ,radiation effects ,single event upsets ,[INFO.INFO-ES]Computer Science [cs]/Embedded Systems ,Node (circuits) ,Random access - Abstract
This study investigates the response of synchronous dynamic random access memories to energetic electrons and especially the possibility of electrons to cause stuck bits in these memories. Three different memories with different node sizes (63, 72, and 110 nm) were tested. Electrons with energies between 6 and 200 MeV were used at RADiation Effects Facility (RADEF) in Jyvaskyla, Finland, and at Very energetic Electron facility for Space Planetary Exploration missions in harsh Radiative environments (VESPER) in The European Organization for Nuclear Research (CERN), Switzerland. Photon irradiation was also performed in Jyvaskyla. In these irradiation tests, stuck bits originating from electron-induced single-event effects (SEEs) were found, as well as single bit-flips from single electrons. To the best knowledge of the authors, this is the first time that stuck bits from single-electron events have been reported in the literature. It is argued in the article that the single-event bit-flips and stuck bits are caused by the same damage mechanism, which would be large displacement damage clusters, and that the two different fault modes represent different amounts of damage to the memory cell. After a large particle fluence, a rapid increase in the error rate was observed, originating from the accumulation of smaller displacement damage clusters in the memory cells. The 110-nm memory was a candidate component to fly on the European Space Agency (ESA) JUpiter ICy moons Explorer (JUICE) mission, so the SEE cross section as a function of electron energy was compared to the expected electron environment encountered by JUICE to estimate the error rates during the mission.
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- 2021
89. COTS Optocoupler Radiation Qualification Process for LHC Applications Based on Mixed-Field Irradiations
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Alessandro Masi, Luigi Dilillo, Angelo Infantino, Salvatore Danzeca, Rudy Ferraro, Ruben Garcia Alia, Markus Brugger, G. Foucard, European Organization for Nuclear Research (CERN), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
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particle accelerator ,Physics::Instrumentation and Detectors ,Nuclear engineering ,01 natural sciences ,7. Clean energy ,Gallium arsenide ,law.invention ,radiation hardness assurance (RHA) ,chemistry.chemical_compound ,indium: gallium ,nonionizing energy loss (NIEL) ,law ,optical ,Nuclear Experiment ,radiation: damage ,Large Hadron Collider ,irradiation ,Mesons ,electronics ,semiconductor ,CERN LHC Coll ,Displacement damage (DD) ,radiation: spectrum ,Protons ,performance ,Silicon ,Nuclear and High Energy Physics ,Materials science ,Radiation ,total ionizing dose (TID) ,Condensed Matter::Materials Science ,0103 physical sciences ,Radiation damage ,gallium: arsenic ,Neutron ,[PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] ,Irradiation ,Electrical and Electronic Engineering ,Neutrons ,010308 nuclear & particles physics ,crystal: defect ,Particle accelerator ,Nuclear Energy and Engineering ,chemistry ,aluminum ,Physics::Accelerator Physics ,Indium gallium arsenide - Abstract
International audience; Optoelectronic components are the most sensitive devices of systems exposed to radiation environments. Displacement damage (DD) effects can severely degrade the performances of such devices, which are extensively used in critical electronic systems installed in particle accelerators or nuclear power plants. This work investigates the use of application-specific radiation spectra for damage estimations in operation instead of mono-energetic proton or neutron irradiations. An analysis of the characteristics of the Large Hadron Collider (LHC) radiation environment in terms of DD is presented in this work along with the demonstration of the ability of the CERN High Energy Accelerator Mixed Field (CHARM) facility of CERN to reproduce them. Then, a set of optocouplers made of gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs) are tested under these environments, and the results are compared to proton and neutron irradiations.
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- 2020
90. Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs
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Yafei Ling, Zhengfeng Huang, Jie Song, Xiaoqing Wen, Zhili Chen, Jie Cui, Aibin Yan, Patrick Girard, Anhui University [Hefei], Hefei University of Technology (HFUT), Northeastern University [Shenyang], TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and Kyushu Institute of Technology
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Computer science ,Clock gating ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Topology ,Upset ,law.invention ,Circuit reliability ,[SPI]Engineering Sciences [physics] ,Robustness (computer science) ,law ,Single-node upset ,0202 electrical engineering, electronic engineering, information engineering ,Soft error ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,Radiation hardening ,020208 electrical & electronic engineering ,Transistor ,Double-node upset ,Triple-node upset ,Hardware_LOGICDESIGN ,Voltage - Abstract
International audience; First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.
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- 2020
91. On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits
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Arnaud Virazel, Patrick Girard, Valentin Gherman, B. Deveautour, Test and dEpendability of microelectronic integrated SysTems (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), TEST (TEST), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and Laboratoire d'Intégration des Systèmes et des Technologies (LIST)
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Error detection ,Adder ,Approximate computing ,Comparator ,Computer science ,Arithmetic circuits ,Design space exploration ,020208 electrical & electronic engineering ,Fault tolerance ,Duplication scheme ,02 engineering and technology ,Fault injection ,020202 computer hardware & architecture ,Arithmetic circuit ,Selective hardening ,[SPI]Engineering Sciences [physics] ,0202 electrical engineering, electronic engineering, information engineering ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Electrical and Electronic Engineering ,Error detection and correction ,Algorithm - Abstract
International audience; Selecting the ideal trade-off between reliability improvement and cost (i.e., area, timing and power overhead) associated with a fault tolerant architecture generally requires an extensive Design Space Exploration. In this paper, we present a feasibility study that addresses the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Four different selective hardening methods have been investigated and compared: i) a full duplication scheme, ii) a reduced duplication scheme based on a structural susceptibility analysis, iii) a reduced duplication scheme based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication scheme that uses an approximate version of the arithmetic circuit. Experimental results performed on adder and multiplier case studies demonstrate the interest of using approximate structures in a duplication scheme since they provide much better error detection capability than other selective hardening methods with lower area and power overheads. Note that all experiments have been done without considering the area and power overhead due to the comparators. This may slightly biased the results from a quantitative point of view, although it does not jeopardize the main conclusion about the interest of using approximate structures as duplication scheme. Moreover, validations using a gate-level fault injection campaign have shown that approximate structures offer a better reliability level compared to the other considered duplication scenarios.
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- 2020
92. Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks
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Luigi Dilillo, Carlo Cazzaniga, Annachiara Ruospo, Alberto Bosio, Daniel Soderstrom, Maria Kastriotou, Ernesto Sanchez, Lucas Matanaluza, Université de Montpellier (UM), Politecnico di Torino = Polytechnic of Turin (Polito), University of Jyväskylä (JYU), ISIS Neutron and Muon Source (ISIS), STFC Rutherford Appleton Laboratory (RAL), Science and Technology Facilities Council (STFC)-Science and Technology Facilities Council (STFC), Science and Technology Facilities Council (STFC), Institut des Nanotechnologies de Lyon (INL), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
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fault injection ,Computer science ,Neural nets ,Inference ,Radiation effects ,Radiation induced ,Fault (power engineering) ,Convolutional neural network ,Software ,Fault injection ,Computer Science (miscellaneous) ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Reliability (statistics) ,reliability ,Artificial neural network ,Approximate methods ,Event (computing) ,business.industry ,Reliability ,Computer Science Applications ,[SPI.TRON]Engineering Sciences [physics]/Electronics ,Human-Computer Interaction ,neural nets ,Computer engineering ,approximate methods ,radiation effects ,[INFO.INFO-ES]Computer Science [cs]/Embedded Systems ,business ,Information Systems - Abstract
International audience; Convolutional Neural Networks (CNNs) are currently one of the most widely used predictive models in machine learning. Recent studies have demonstrated that hardware faults induced by radiation fields, including cosmic rays, may significantly impact the CNN inference leading to wrong predictions. Therefore, ensuring the reliability of CNNs is crucial, especially for safety-critical systems. In the literature, several works propose reliability assessments of CNNs mainly based on statistically injected faults. This work presents a software emulator capable of injecting real faults retrieved from radiation tests. Specifically, from the device characterisation of a DRAM memory, we extracted event rates and fault models. The software emulator can reproduce their incidence and access their effect on CNN applications with a reliability assessment precision close to the physical one. Radiation-based physical injections and emulator-based injections are performed on three CNNs (LeNet-5) exploiting different data representations. Their outcomes are compared, and the software results evidence that the emulator is able to reproduce the faulty behaviours observed during the radiation tests for the targeted CNNs. This approach leads to a more concise use of radiation experiments since the extracted fault models can be reused to explore different scenarios (e.g., impact on a different application).
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- 2022
93. Neutron-Induced Effects on a Self-Refresh DRAM
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Manon Letiche, Alberto Bosio, Daniel Soderstrom, Lucas Matana Luza, Helmut Puchner, Ruben Garcia Alia, Luigi Dilillo, Carlo Cazzaniga, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), University of Jyväskylä (JYU), Infineon Technologies AG [München], European Organization for Nuclear Research (CERN), Institut Laue-Langevin (ILL), ILL, ISIS Neutron and Muon Source (ISIS), STFC Rutherford Appleton Laboratory (RAL), Science and Technology Facilities Council (STFC)-Science and Technology Facilities Council (STFC), École Centrale de Lyon (ECL), and Université de Lyon
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HyperRAM ,Computer science ,020209 energy ,käyttömuistit ,Self-Refresh ,02 engineering and technology ,Neutron ,Fault (power engineering) ,elektroniikkakomponentit ,0202 electrical engineering, electronic engineering, information engineering ,0601 history and archaeology ,Electrical and Electronic Engineering ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Safety, Risk, Reliability and Quality ,Simulation ,hiukkassäteily ,Block (data storage) ,060102 archaeology ,Event (computing) ,stuck bits ,neutronit ,06 humanities and the arts ,computer.file_format ,Condensed Matter Physics ,Self-refresh ,Atomic and Molecular Physics, and Optics ,SEE ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,[SPI.TRON]Engineering Sciences [physics]/Electronics ,radiation ,Identification (information) ,DRAM ,säteilyfysiikka ,Stuck bits ,Bitmap ,Node (circuits) ,[INFO.INFO-ES]Computer Science [cs]/Embedded Systems ,computer ,Dram ,Dynamic testing - Abstract
International audience; The field of radiation effects in electronics research includes unknowns for every new device, node size, and technical development. In this study, static and dynamic test methods were used to define the response of a self-refresh DRAM under neutron irradiation. The neutron-induced effects were investigated and characterised by event cross sections, soft-error rate, and bitmaps evaluations, leading to an identification of permanent and temporary stuck cells, single-bit upsets, and block errors. Block errors were identified in different patterns with dependency in the addressing order, leading to up to two thousand faulty words per event, representing a real threat from a user perspective, especially in critical applications. An analysis of the damaged cells’ retention time was performed, showing a difference in the efficiency of the self-refresh mechanism and a read operation. Also, a correlation of the fault mechanism that generates both single-bit upsets and stuck bits is proposed. Post- irradiation high-temperature annealing procedures were applied, showing a recovery behaviour on the damaged cells.
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- 2022
94. Low-Cost EVM Measurement of ZigBee Transmitters From 1-bit Undersampled Acquisition
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Florence Azaïs, François Lefèvre, T. Vayssade, Laurent Latorre, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Smart Integrated Electronic Systems (SmartIES), and NXP Semiconductors
- Subjects
business.industry ,Computer science ,digital signal processing ,RF test ,digital ATE ,EVM measurement ,wireless communication ,Computer Graphics and Computer-Aided Design ,Signal ,OQPSK ,Automatic test equipment ,ZigBee ,Modulation ,Radio frequency ,Electrical and Electronic Engineering ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,business ,Software ,Clock recovery ,Digital signal processing ,Computer hardware ,Communication channel ,Phase-shift keying - Abstract
International audience; Error Vector Magnitude (EVM) or alternately Offset Error Vector Magnitude (OEVM) is one of the most important performance to verify for RF circuits such as ZigBee transmitters in order to ensure that the quality of the generated modulated-signal complies with the requirements of the wireless communication standard. The conventional solution to measure this performance relies on the use of an Automatic Test Equipment (ATE) equipped with expensive RF channels. This paper presents a low-cost solution that permits to realize EVM measurement using only a standard digital ATE. The approach is based on 1-bit under-sampled acquisition of the RF modulatedsignal by a digital tester channel associated with a specificallytailored processing algorithm. This algorithm involves many different steps that are detailed in this paper, including phase and amplitude fluctuation extraction, RF signal reconstruction, symbol clock recovery, symbol bits detection and synthesis of reference data for EVM calculation. The proposed digital test solution is first evaluated through lab hardware experiments and then validated with EVM measurements on an industrial ATE.
- Published
- 2021
95. Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation
- Author
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Aziza, Hassen, Hamdioui, Said, Fieback, Moritz, Taouil, Mottaqiallah, Moreau, Mathieu, Girard, Patrick, Virazel, Arnaud, Coulié, Karine, Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), Aix Marseille Université (AMU), Delft University of Technology (TU Delft), Test and dEpendability of microelectronic integrated SysTems (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), HORIBA France SAS [Villeneuve d'Ascq], HORIBA Scientific [France], TEST (TEST), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
- Subjects
010302 applied physics ,Multi-level cell ,Cost structure ,Computer science ,variability ,current control ,02 engineering and technology ,Hafnium compounds ,01 natural sciences ,RRAM ,Die (integrated circuit) ,Resistive random-access memory ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,020201 artificial intelligence & image processing ,OxRAM multi-level cell ,write termination ,QLC ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Reset (computing) ,ComputingMilieux_MISCELLANEOUS ,MLC - Abstract
International audience; Multi-Level Cell (MLC) technology can greatly reduce Resistive RAM (RRAM) die sizes to achieve a breakthrough in cost structure. In this paper, a novel design scheme is proposed to realize reliable and uniform MLC RRAM operation without the need of any read verification. MLC is implemented based on a strict control of the cell programming currents of 1T-1R HfO 2 -based RRAM cells. Specifically, a self-adaptive write termination circuit is proposed to control the RRAM RESET current. Eight different resistance states are obtained by varying the compliance current which is defined as the minimal current allowed by the termination circuit in the RESET direction.
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- 2021
96. Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks
- Author
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Annachiara Ruospo, Lucas Matana Luza, Alberto Bosio, Marcello Traiola, Luigi Dilillo, Ernesto Sanchez, Politecnico di Torino = Polytechnic of Turin (Polito), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), École Centrale de Lyon (ECL), and Université de Lyon
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Neural Networks ,Fault Injection ,[INFO.INFO-ES]Computer Science [cs]/Embedded Systems ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Reliability ,[SPI.TRON]Engineering Sciences [physics]/Electronics - Abstract
International audience; In the last years, the adoption of Artificial Neural Networks (ANNs) in safety-critical applications has required an in-depth study of their reliability. For this reason, the research community has shown a growing interest in understanding the robustness of artificial computing models to hardware faults. Indeed, several recent studies have demonstrated that hardware faults induced by an external perturbation or due to silicon wear out and aging effects can significantly impact the ANN inference leading to wrong predictions. This work classifies and analyses the principal reliability assessment methodologies based on Fault Injection at different abstraction levels and with different procedures. Some of the most representative academic and industrial works proposed in the literature are described and the principal advantages, and drawbacks are highlighted.
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- 2021
97. On the evaluation of FPGA radiation benchmarks
- Author
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Maria Kastriotou, Christopher D. Frost, G. Bricas, Luigi Dilillo, Jerome Boch, L. Matana Luza, Carlo Cazzaniga, Georgios Tsiligiannis, Antoine Touboul, Institut d’Electronique et des Systèmes (IES), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Radiations et composants (RADIAC), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Université de Montpellier (UM), ISIS Facility, STFC Rutherford Appleton Laboratory (RAL), and Science and Technology Facilities Council (STFC)-Science and Technology Facilities Council (STFC)
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Finite impulse response ,Computer science ,02 engineering and technology ,Hardware_PERFORMANCEANDRELIABILITY ,Single event effects ,Neutron ,Radiation ,Benchmark ,01 natural sciences ,0103 physical sciences ,FIR filter ,0202 electrical engineering, electronic engineering, information engineering ,Electrical and Electronic Engineering ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Safety, Risk, Reliability and Quality ,Field-programmable gate array ,FPGA ,Multiplier ,010302 applied physics ,020208 electrical & electronic engineering ,Fault injection ,Benchmarking ,Neutron radiation ,Condensed Matter Physics ,Atomic and Molecular Physics, and Optics ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,[SPI.TRON]Engineering Sciences [physics]/Electronics ,Computer engineering ,Benchmark (computing) ,Multiplier (economics) ,[INFO.INFO-ES]Computer Science [cs]/Embedded Systems - Abstract
International audience; This paper presents a benchmarking methodology to analyse the failure mechanisms of FPGAs under radiation, using comparative results on the radiation sensitivity of parallel multipliers with different implementations. Atmospheric neutron beam test results of Artix7, Spartan7 and IGLOO2 FPGAs are presented and validated against fault injection campaigns.
- Published
- 2021
98. Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State
- Author
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Aziza, Hassan, Hamdioui, Said, Fieback, Moritz, Taouil, Mottaqiallah, Moreau, Mathieu, Girard, Patrick, Virazel, Arnaud, Coulié, K., Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), Delft University of Technology (TU Delft), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), Test and dEpendability of microelectronic integrated SysTems (TEST), and Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)
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TK7800-8360 ,variability ,K RRAM ,OxRAM multi-level cell ,write termination ,current control ,Electronics ,QLC ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,RRAM ,MLC - Abstract
International audience; RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation with- out the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell program- ming current of 1T-1R HfO2-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 μs, respectively.
- Published
- 2021
99. On Preventing SAT Attack with Decoy Key-Inputs
- Author
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Sophie Dupuis, Marie-Lise Flottes, Bruno Rouzeyre, Quang-Linh Nguyen, TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
- Subjects
Very-large-scale integration ,Hardware security module ,Corruption ,Computer science ,media_common.quotation_subject ,Supply chain ,Overproduction ,Computer security ,computer.software_genre ,Oracle ,Countermeasure ,SAT Attack ,IP Protection ,Design-for-Trust ,Key (cryptography) ,Hardware Security ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Resilience (network) ,computer ,media_common ,Logic Locking - Abstract
International audience; The globalized supply chain in the semiconductor industry raises several security concerns such as IC overproduction, intellectual property piracy and design tampering. Logic locking has emerged as a Design-for-Trust countermeasure to address these issues. Original logic locking proposals provide a high degree of output corruption-i.e., errors on circuit outputsunless it is unlocked with the correct key. This is a prerequisite for making a manufactured circuit unusable without the designer's intervention. Since the introduction of SAT-based attacks-highly efficient attacks for retrieving the correct key from an oracle and the corresponding locked design-resulting design-based countermeasures have compromised output corruption for the benefit of better resilience against such attacks. Our proposed logic locking scheme, referred to as SKG-Lock, aims to thwart SAT-based attacks while maintaining significant output corruption. The proposed provable SAT-resilience scheme is based on the novel concept of decoy key-inputs. Compared with recent related works, SKG-Lock provides higher output corruption, while having high resistance to evaluated attacks.
- Published
- 2021
100. Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications
- Author
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Santosh Kumar Vishvakarma, Ambika Prasad Shah, Neha Gupta, Patrick Girard, Sajid Khan, Michael Waltl, Indian Institute of Technology Indore (IITI), Indian Institute of Technology [Jammu] (IIT Jammu), Vienna University of Technology (TU Wien), TEST (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)
- Subjects
IoT ,TK7800-8360 ,Computer Networks and Communications ,Computer science ,02 engineering and technology ,Hardware_PERFORMANCEANDRELIABILITY ,error-tolerant ,supply voltage scaling ,reconfigurable architecture ,0202 electrical engineering, electronic engineering, information engineering ,Static random-access memory ,Electrical and Electronic Engineering ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,Scaling ,Hardware_MEMORYSTRUCTURES ,business.industry ,020208 electrical & electronic engineering ,Electrical engineering ,Failure rate ,Dissipation ,020202 computer hardware & architecture ,Power (physics) ,failure probability ,CMOS ,Hardware and Architecture ,Control and Systems Engineering ,Signal Processing ,Node (circuits) ,Electronics ,business ,Voltage - Abstract
This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.
- Published
- 2021
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