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In this paper we describe the layout of a Silicon Photonic chip, composed of two different Mach-Zehnder interferometers realized with SOI technology; we report the results obtained from the electromagnetic simulations, that have been performed splitting the MZIs in multiple components to extract the power transmission parameters and we also report the result of the measurements taken in lab. The aim of this study is to demonstrate the ability the Silicon photonics devices have to become the new generation of digital interconnects.

A front-end ASIC for 4D tracking is presented. The prototype includes the block necessary to build a pixel front-end chain for timing measurement, as independent circuits. The architecture includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time- to-digital converter. The blocks were designed with target specifications in mind including: an area occupation of 55 μm × 55 μm, a power consumption tens of micro ampere per channel and timing a resolution of at least 100 ps. The prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of the TimeSpOT project which aims to reach a high-resolution particle tracking both in space and in time, in order to provide front-end circuitry suitable for next generation colliders.

We present the development of a test ASIC, named Timespot1, designed in CMOS 28-nm technology, featuring a 32x32 pixel matrix and a pitch of 55 μm, The ASIC is conceived as the first prototype in a series, capable to read-out pixels with timing capabilities in the range of 30 ps and below. Each pixel is endowed with a charge amplifier, a discriminator and a Time-to-Digital-Converter, capable of time resolutions below 20 ps and read-out rates (per pixel) around 3 MHz. The timing performance are obtained respecting a power budget of about 50 µW per pixel, corresponding to a power density of approximately 2 W/cm2• This feature makes the Timespot1 approach an interesting solution for vertex detectors of the next generation of colliders, where high space and time resolutions will be mandatory requirements to cope with the huge amount of tracks per event to be detected and processed.

This paper presents the design and implementation of a particle detector in a Bipolar-CMOS-DMOS (BCD) 180 nm technology. The design has a substrate potential of — 50 V and supply voltage of 1.8 V. Size of the unit pixel sensor is $250\times 50\ \mu\mathbf{m}^{2}$ . The chip consists of an array of $47\times 6$ pixels including the signal processing circuitry. The total chip area is $3.3 \times 4.4\ \mathbf{mm}^{2}$ . The complete signal processing circuitry is hosted inside the diode sensor to achieve 100% fill factor. The chip consists of 106 input-output pads, including the pads for supplies viz. — 50 V, 0 V and 1.8 V. The measurement results are presented to validate the noise and crosstalk models of the designed detector. The comparison shows an average mismatch of 2.65 $\mu\mathbf{V}$ for the crosstalk voltages in a range of 3000 to 7000 injected electrons. The circuit noise has an average mismatch of $1.23\times 10^{-10}\ \mathbf{V}^{2}/\mathbf{Hz}$ between the analytical and the measurement results for a frequency range of 100 kHz to 22 MHz. The analog processing circuitry provides a measured voltage gain of 33.3 dB at 100 kHz of input frequency.

Future high luminosity colliders will require front-end electronics with unprecedented performance, both in space and time resolution (tens of micrometers and tens of picoseconds) and in radiation hardness (tens of megagray). Moreover, the high number of events will generate an enormous quantity of data (some terabits per second), and the limited bandwidth requires to perform data selection as close as possible to the front-end stage, to reduce the amount of data transmitted and stored for off-line analysis.The TimeSpOT (TIME and SPace real-time Operating Tracker) project, funded by INFN, is developing a complete demonstrator of a tracking device including all the features needed for future high luminosity experiments.In this presentation, we describe the first prototype of the readout electronics in 28 nm CMOS technology. The modules of the front-end circuitry have been designed and integrated in a test chip, which will allow us to characterize each block separately, and to connect them in a processing chain to evaluate the overall performance.

A dedicated test chip has been designed in order to support the study of the EMC performance, and more specifically the Conducted Emission, of a microcontroller family in M28 FDSOI technology. The focus in designing the test chip has been put on the on-die decoupling capacitors, in particular on the topology of the placement as well as the capacitance amount.

International audience; This paper presents the design of an SRAM cell in 28 nm, specifically designed to avoid metastability at start-up. Metastable operation is avoided by unbalancing the size of transistors. Extensive simulations have confirmed that the probability of metastable operation is greatly reduced.

International audience; The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 µm2) and large pixel chip size (~2x2 cm2), high hit rate (3 GHz/cm2), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 µs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed

An innovative Content Addressable Memory (CAM) cell with radiation hardened (RH) architecture is presented. The RH-CAM is designed using a commercial 28 nm CMOS technology. The circuit has been simulated in worst-case conditions, and the effects due to single particles have been analyzed by injecting a current pulse into a circuit node. The proposed architecture is suitable for real-time pattern recognition tasks in harsh environments, such as front-end electronics in the ATLAS experiment at the Large Hadron Collider (LHC) and in space applications.

This paper presents a new population count circuit, suitable for very scaled CMOS technologies. The proposed circuit is optimized for the total area, instead of the number of transistors, in order to take full advantage of deeply scaled technology features. Moreover, the circuit is purely combinational, in order to simplify the control logic. The envisaged solution has been designed in a commercial 28 nm CMOS technology, and the design of the layout has been validated. The total silicon area is 14.04 × 0.905 μm2 for a counter from 0 to 8.

Monochromatic X and gamma rays are a standard calibration tool for semiconductor detector. For finely segmented pixel detectors, like the ones foreseen for HL-LHC detector upgrades, the single pixel spectrum is affected by charge sharing across nearby pixels, due to diffusion and the finite range of photoelectrons , resulting in a low energy continuum below the photoelectric peak. In this paper a systematic simulation study will be presented. The shape of the transition between the photoelectric peak and the continuum is determined by diffusion and needs to be unfolded for a correct estimation of the energy resolution. Simulation results are compared with data collected with different high-resistivity CMOS devices with 50 × 250 μ m2 pixel size and photon energies between 13 and 60 keV. They show a good agreement, highlighting the potential usage of the whole single pixel spectrum to derive device characteristics.

International audience; This paper presents the characterization of the new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; and reducing power consumption and silicon area by means of new memory cells designed with full-custom approach. The design was submitted in December 2016; the prototypes were fabricated and packaged in a 17 × 17 Ball Grid Array (BGA) standalone package. Prototype characterization confirms the chip functionality. The final chip will be assembled in a System In Package (SiP) together with a bare FPGA die.

The paper presents the research activities in microelectronics, aiming at improving detection capabilities of future High Energy Physics (HEP) experiments. The output of this research will be the development of novel integrated circuits, to enhance the performance of electronic systems for the High Luminosity Large Hadron Collider (HL-LHC). In particular, the main research activities are focused on monolithic pixel arrays, on new digital architectures for pixel readout in 65 nm CMOS, and on associative memories for several interdisciplinary applications, such as fast tracking for trigger, DNA sequencing, magnetic resonance and image analysis.

International audience; RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

This paper briefly recalls the design of a silicon test chip specially conceived to study the noise propagation trough the silicon substrate and the ESD protection. The noise source is a logic block designed to emulate the clock tree of a microcontroller. The experimental results obtained on two versions of the test chip are reported and discussed. The two test chips have the same schematic, but they differ in ESD protections: in the first one the protections were completely removed, while the second test chip has ESD protections both on VDD and VSS. This allows to study the effect of the protection structures on the noise propagation through the different power domains and the substrate. Dedicated probe points have been introduced in the layout around the perimeter of the die. The measurements of the conducted emissions at the substrate probes and on the power supply pins have been performed according to the IEC61967-4, 150Ω method.

International audience; We present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available communication channels between the ARM CPU and the FPGA using Direct Memory Access (DMA) technique and the AM using Multi-Gigabit Transceivers (MGT). We report the measured performances and discuss potential applications and future developments. The proposed architecture is compact, portable and provide a large communication bandwidth between components.

International audience; In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM and FPGA is also enhanced. In addition, LVDS drivers and receivers are implemented to strengthen the signal integrity of the I/Os. The new AM chip design is submitted for the fabrication. The die will be packaged in a 17 × 17 Ball Grid Array (BGA) standalone package with a Silicon In Package (SiP) structure mounting AM dies and a bare die FPGA.

This paper proposes a novel population count circuit for Associative Memories (AM)s. Currently, AM chips requires a large number of silicon area for the population count circuitry. For this reason, is necessary an optimization in terms of area for the future AM devices to have a better memory density. A population count circuit counts how many blocks of the AM are in a matching state. If the count sum is greater than a preconfigured threshold, the output wire is set to ‘1’, otherwise is set to ‘0’. In the existing circuits there are, in addition, several control signals that are used to increase the circuit flexibility, but these controls require a large number of transistors and interconnections. The purpose of the proposed circuit is to reduce the number of transistors and interconnections complexity, with the final aim to reduce the occupied silicon area.

Associative memories are massively parallel circuits which perform a parallel comparison between stored data and input data. When operated in parallel comparison mode, they require high current spikes (in the order of few amperes) at every clock edge, and the voltage drop due to current spikes can seriously affect the circuit operation. This paper proposes a method to enhance the power integrity, both at package level and at chip level. This work aims at avoiding “bounce” effects on supply voltages, and at keeping the supply voltage ripple below one hundred millivolts during the comparison mode. A technique to mitigate the voltage ripple consists in placing decoupling capacitors on the Power Delivery Network (PDN). This technique can be applied both at the chip level and at the package level. We show that this technique allows us to keep the power network impedance below 0.1 Ω within the relevant bandwidth of the circuit.

The dynamic clocked comparator using a parametric amplifier is proposed and designed using a concept of the charge transfer amplification (CTA). A low gain (5 V/V) reverse discrete-time parametric amplifier (RDTPA) was used as a pre-amplifier stage of the proposed comparator. The level shifter scheme to nullify an input common-mode voltage ( V CMI ) shows minimal deviation for varying process corners. The complete design including the latch and the RDTPA is designed and fabricated in an STMicroelectronics 32 nm CMOS technology with the supply voltage of 1 V and a sampling frequency of 50 MHz. The fabricated chip results show 7 mV of an input offset voltage, 120 μW of power consumption and 2.4 pJ of energy per comparison.

Design techniques for radiation hardening of integrated circuits in commercial CMOS technologies are presented. Circuits designed with the proposed approaches are more tolerant to both total dose and to single event effects. The main drawback of the techniques for radiation hardening by design is the increase of silicon area, compared with a conventional design.

This paper presents the design of a LVDS input/output interface circuit for the next generation of Associative Memory (AM) chip. The bandwidth of Associative Memories is a critical aspect that needs to be addressed in order to increase the number of comparisons per second. Our aim is to transfer parallel buses at 500 MHz. Since a large number of receivers/drivers will be included in the AM chip, power consumption of the circuits has been taken into account. The design discussed in this work has been submitted for fabrication in December 2016 in a 28 nm CMOS technology.

This paper proposes a methodology to design radiation-hardened ICs, suitable for space applications and high-energy physics experiments. The miniaturization of ICs has brought an increase of circuit logic errors due to radiation, also at ground level. The increased complexity of IC design due to technology scaling requires new tools to design rad-hard circuits. In this paper, we propose a design tool that employs a layout-oriented simulation approach to identify the sensitive IC area and provide data about the effects due to radiation. The simulation tool is implemented in Cadence LayoutGXL. The proposed approach will help to have a more efficient IC design reducing design time and costs related to the need of fabricating prototypes to be characterized under radiation to test their hardness.

In this paper, we present a model to derive statistical properties of digital noise due to logic transitions of gates in a fully CMOS combinational circuit. Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters and input signals. However, the huge number of logic blocks in a complex IC makes digital switching a cognitively stochastic process. For a combinational logic network, we can model digital switching currents as stationary shot noise processes, deriving both their amplitude distributions and their power spectral densities. From the spectra of digital currents, we can also calculate the spectral components and the rms value of disturbances injected into the on-chip power supply lines. The stochastic model for switching currents has been validated by comparing theoretical results with circuit simulations.

This paper presents an approach for the analysis and the experimental evaluation of crosstalk effects due to the current pulses drawn from voltage supplies in mixed analog-digital CMOS ICs. To this end, two test chips were designed in 0.18-μm CMOS technology. The two test chips were integrated and then mounted on a board with and without package to compare measurements on chips mounted in package and mounted on board. To ensure that the differences between measurements are only due to the assembling technique, the same printed circuit boards were used for both chip-in-package and chip-on-board. Moreover, the experimental setup was carefully arranged so as not to introduce further disturbances due to external connections or noise sources. Both ICs were extensively simulated by using a realistic model of on-chip and off-chip parasitics to study what happens in the analog section when digital switching noise is injected. Simulations results, confirmed by test chip measurements, demonstrate that disturbances due to switching currents in digital blocks propagate through substrate, package, and interconnection parasitics and affect analog voltages, thus degrading the circuit performance. Therefore, reduction of parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends.

International audience; This paper is a review of recent progress of RD53 Collaboration. Results obtained onthe study of the radiation effects on 65 nm CMOS have matured enough to define first strategies toadopt in the design of analog and digital circuits. Critical building blocks and analog very frontend chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64 64pixels with complex digital architectures have been produced, and point to address the main issuesof dealing with extremely high pixel rates, while operating at very small in-time thresholds in theanalog front end. The collaboration is now proceeding at full speed towards the design of a largescale prototype, called RD53A, in 65 nm CMOS technology

Radiation detectors built in high-voltage and high-resistivity CMOS technology are an interesting option for the large area pixel trackers sought for the upgrade of the Large Hadron Collider experiments. A possible architecture is a hybrid design, where CMOS sensors are readout by front-end electronics coupled through a thin dielectric layer. A critical requirement is the radiation hardness of both the sensor and the front-end circuitry, up to a total dose ranging from 100 Mrad to 1 Grad (1 MGy to 10 MGy), depending on the distance from the interaction region. This paper explores the suitability of the BCD8 technology provided by STMicroelectronics for the construction of radiation-hard pixel detectors together with a technique to achieve reliability and repeatability of the hybridization process between the detector and the readout chip.

This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm2. To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. the other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications.

Journal of Instrumentation 11(02), C02056 (2016). doi:10.1088/1748-0221/11/02/C02056, The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger and data acquisition system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer is part of the ATLAS trigger upgrade project, it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100μs, full tracking information for tracks with momentum as low as 1 GeV . Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance., Published by Inst. of Physics, London

In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most important and challenging tasks. In this framework, the use of both voltage scaling and body biasing techniques is a mainstream strategy largely used for leakage power reduction. This work presents a case study to evaluate the impact of these techniques on an industrial microprocessor-based design. We analyze the impact of body biasing in terms of area penalties and routing efforts. Furthermore, a complete analysis flow is proposed to evaluate the achievable leakage reduction and the expected performance degradation. In order to overcome the limited spectrum of operating configurations covered by a given library set, we propose a practical and effective methodology based on a standard digital design and characterization flow. By using this procedure, a designer can efficiently evaluate the most appropriate leakage/timing trade-offs, and consequently determine the best supply voltage and biasing configurations to implement the design. The experimental results on our testcase demonstrate that body biasing leads to a leakage reduction up to six times with respect to the standard reference supply voltage configuration.

This paper proposes a new design method to enhance the radiation hardness of circuits for the next generation of pixel detectors in High Energy Physics experiments. The approach is based on Radiation Hardness By Design methodology to mitigate Single Event Effects. In particle detectors, front-end electronics opeates in an environment characterized by a high dose of radiation. We propose a set of digital cells specifically designed to tolerate a high level of radiation (up to 1 Grad). The cells have been designed in 65 nm CMOS technology. Simulation results show the complete functionality up to 1 Grad of total dose of radiation. The first prototype chip has been designed and submitted for fabrication under the Istituto Nazionale di Fisica Nucleare (INFN) CHIPIX65 project.