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In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node dimensions using ensemble Monte Carlo simulations. It is found that due to large external resistance, lack of stressing methods, smaller bandgap, larger dielectric constant, and increased variability that in the absence of major innovation, Ge is not an ideal candidate for channel replacement material of pMOS in future CMOS technology generation FinFETs. In order for Ge to compete with Si, it would at a minimum require a stressing mechanism and improved contact resistance, but leakage and variability would still be a concern for low-power applications. [ABSTRACT FROM AUTHOR]

Discusses a test structure for back-end-of-line (BEOL), an infrastructure Internet protocol for process monitoring. Method of characterizing and measuring yield ramp issues and solutions for improving silicon debut and design-for-manufacturability; Deep-submicron BEOL yield challenges; Traditional BEOL yield programs.

The article focuses on the design-for-manufacturing (DFM). At the large IDMs, cross-functional teams are being put into place for 65nm, and nascent internal or external tools are being readied that can truly deliver on DFM, i.e., to take yield information from the fab and present it as usable yield models up front in the design flow, concurrent with traditional design models such as speed, power, etc. DFM will have to be instituted with next-generation computer-aided design tools that are well calibrated using advanced characterization wafer data.