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A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter's frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing. [ABSTRACT FROM AUTHOR]

Miniaturized electronic devices are essential to improve the performance, reduce the weight and volume, and improve reliability of electronic packages in a spacecraft. With technology scaling, a prime reliability challenge for CMOS devices used in spacecrafts is the occurrence of soft errors due to the propagation of SETs in the space radiation environment. ASICs undergo stringent quality tests to ensure reliable operation of the spacecraft during its mission life. In general, SEE tolerance qualification tests estimate the heavy ion radiation tolerance of CMOS devices for space application. A new SEE test methodology using available scan structure in digital ASICs is proposed. Here, different patterns are loaded in the scan chain which helps to differentiate between SET and SEU soft errors, and test data analysis identifies the SEU fault location. Two different ASIC designs realized in 180 nm CMOS technology are tested in this methodology and detection of SET prone cell is also illustrated. [ABSTRACT FROM AUTHOR]

Summary Oscillator‐based Ising machines (OIMs) particularly those realized in complementary metal oxide semiconductor (CMOS) have gained popularity for solving combinatorial optimization problems (COPs) in recent years due to its scalability, low‐power consumption, and room temperature operation. The implemented OIMs have thus far focused on solving optimization problems with a single global minima. However, real‐life optimization problems often have multiple solutions. In this paper, we propose a generalized approach to solve COPs with single (without contention), as well as multiple (with contention) solutions using frequency tunable CMOS ring oscillator (ROSC)‐based Ising machine. A capacitive frequency tunable CMOS ring‐oscillator coupled with an internal subharmonic injection locking (SHIL) generator realized using 14‐nm FinFET models works as Ising spin in the proposed approach. We demonstrate how frequency tuning can help in attaining good quality results and also determine all possible solutions of COP with contention. We also propose a generalized algorithm for monitoring the states of the oscillator network to indicate tuning necessity and extract solutions from the oscillator's output irrespective of the type of COP. [ABSTRACT FROM AUTHOR]

This article comprehensively reviews and studies CMOS transformer tank voltage‐controlled oscillators (VCOs) designed to improve the frequency tuning range (FTR) and minimize phase noise (PN) across a broad frequency range, particularly for mm‐wave and fifth‐generation applications. The study focuses on enhancing the performance of the oscillators to meet the demanding requirements of these advanced applications. This study thoroughly investigates and compares various strategies to increase the FTR, minimize PN, and reduce power dissipation in transformer tank VCOs. The aim is to establish fundamental guidelines for implementing transformer‐based tank VCOs. The study comprehensively reviews and analyzes the overall architecture of transformer‐based tank VCOs, presenting a detailed examination of the methods employed to enhance VCO performance. Additionally, the study illustrates the impact of the coupling factor on the VCO's performance parameters, detailing and demonstrating the overall tank circuit quality factor (Q) and resonator coupling factor (κ). A thorough understanding of PN methodology and the limitations of FTR has led to the development of innovative architectures. These include transformer‐based capacitive feedback (FB) oscillators with resistively adjusted variable inductors, as well as class‐F and inverse class‐F VCOs. These novel architectures contribute significantly to the improvement of oscillator performance. [ABSTRACT FROM AUTHOR]

This paper presents a detailed design of a broadband power amplifier (PA) utilizing 0.18-μm CMOS technology, operating in the frequency range of 2–5 GHz. This ultra-wideband (UWB) power amplifier uses a cascode topology with current reuse to enhance gain over the desired frequency band, utilizing an inductive source degenerate design to achieve the best linearity and output power and gain while maintaining a wide bandwidth. The inductive source degenerate adopts bondwire and microstrip line design. The paper includes extensive analysis, simulation results, and measurements to verify the performance of the amplifier and demonstrate its suitability for broadband power amplifier applications. The measured results for the proposed UWB power amplifier show excellent performance, with an impressive third-order input intercept point (IIP3) ranging from 15 to 18.7 dBm over the frequency range of 2–5 GHz. The output third-order intercept point (OIP3) ranges from 33 to 35 dBm. Additionally, the gain flatness is specified as 12.5 ± 1.5 dB. The reverse isolation is greater than or equal to − 40 dBm. The PA has a P1dB output power (OP1dB) of 10.2 dBm at 3 GHz, 9.2 dBm at 4 GHz, and 9.2 dBm at 5 GHz, respectively. The PA has a P1dB power-added efficiency of 30.5% at 3 GHz, 23% at 4 GHz, and 22% at 5 GHz with a 50 Ω load termination. The power dissipation is 33.3 mW at a supply voltage of 1.8 V. In addition, the PA has an excellent small group delay variation of ± 65 ps. The chip area is 1.01 × 1.08 mm2, including the pads. The proposed UWB PA demonstrates exceptional linearity, efficiency, and group delay in the 2–5 GHz frequency band. [ABSTRACT FROM AUTHOR]

This paper discusses the design of a driver amplifier operating in the Ku-band using a 130 nm SOI CMOS process. The amplifier consists of two stages: a cascode amplifier in the first stage for high gain, and a CS amplifier in the final stage for high OP1dB. In the cascode amplifier structure of the first stage, a series inductor is added between the CS and CG amplifiers to simplify input matching. This modification shifts the maximum Gm point of the cascode amplifier to a lower frequency, resulting in a high gain at the target frequency. The measured amplifier achieves a maximum gain of 13.7 dB and an OP1dB of −0.3 dBm. It consumes 12 mW of power at 1.2 V and occupies an area of 0.188 mm², excluding the DC and RF pads. [ABSTRACT FROM AUTHOR]

In-memory computing (IMC) represents a promising approach to reducing latency and enhancing the energy efficiency of operations required for calculating convolution products of images. This study proposes a fully differential current-mode architecture for computing image convolutions across all four quadrants, intended for deep learning applications within CMOS imagers utilizing IMC near the CMOS sensor. This architecture processes analog signals provided by a CMOS sensor without the need for analog-to-digital conversion. Furthermore, it eliminates the necessity for data transfer between memory and analog operators as convolutions are computed within modified SRAM memory. The paper suggests modifying the structure of a CMOS SRAM cell by incorporating transistors capable of performing multiplications between binary (−1 or +1) weights and analog signals. Modified SRAM cells can be interconnected to sum the multiplication results obtained from individual cells. This approach facilitates connecting current inputs to different SRAM cells, offering highly scalable and parallelized calculations. For this study, a configurable module comprising nine modified SRAM cells with peripheral circuitry has been designed to calculate the convolution product on each pixel of an image using a 3 × 3 mask with binary values (−1 or 1). Subsequently, an IMC module has been designed to perform 16 convolution operations in parallel, with input currents shared among the 16 modules. This configuration enables the computation of 16 convolutions simultaneously, processing a column per cycle. A digital control circuit manages both the readout or memorization of digital weights, as well as the multiply and add operations in real-time. The architecture underwent testing by performing convolutions between binary masks of 3 × 3 values and images of 32 × 32 pixels to assess accuracy and scalability when two IMC modules are vertically integrated. Convolution weights are stored locally as 1-bit digital values. The circuit was synthesized in 180 nm CMOS technology, and simulation results indicate its capability to perform a complete convolution in 3.2 ms, achieving an efficiency of 11,522 1-b TOPS/W (1-b tera-operations per second per watt) with a similarity to ideal processing of 96%. [ABSTRACT FROM AUTHOR]

Gamification is being incorporated into university classrooms due to its educational benefits for students learning, including encouraging student behavior and engagement, and consequently improving learning outcomes. Despite gamification being increasingly used in education, little has been developed related to Very-Large-Scale Integration (VLSI). In this article, we describe two different gamification experiences applied to integrated circuit processing and design in an introductory VLSI design course for Electronic Engineers. While gamification in universities is still not very mature and our experience spans only two academic years, we observed that, with the practice of gamifying part of our course, the topics treated in games were profoundly learned and the experience was very positive in every aspect of the teaching–learning process. [ABSTRACT FROM AUTHOR]

This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λo2. [ABSTRACT FROM AUTHOR]

A four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW. [ABSTRACT FROM AUTHOR]

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 × 3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 × 3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., G H and G V , respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient (G) of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing G H and G V cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window. [ABSTRACT FROM AUTHOR]

Optical and electrophysiological methods are widely used in neuroscience to study brain activity. Each technique has its own strengths and weaknesses that complement each other to provide a more comprehensive understanding of neuronal activity. To this end, we developed an implantable CMOS image sensor device with an integrated carbon electrode for the simultaneous measurement of fluorescence and extracellular signals. The device is composed of a 450 × 1660 µm CMOS chip and micro-LED secured to a flexible printed circuit substrate. The chip has an imaging surface measuring 900 × 300 µm2, comprising 120 × 90 pixels recording at 10 frames per second. An absorption filter film was placed on top of the imaging surface to block excitation light. The device was coated with parylene-C for waterproofing and, finally, the coating film was readily turned into carbon electrodes by laser carbonization. We characterized the lasercarbonized electrodes by cyclic voltammetry, electrochemical impedance spectroscopy, and X-ray photoelectron spectroscopy to confirm carbonization. We then demonstrated simultaneous in vivo recording of fluorescence and extracellular signals in hippocampus CA1 using the device. [ABSTRACT FROM AUTHOR]

Video processing is the most emergent area of image processing in Research and Development. This paper, we present some advanced technology interrelated to video and image processing, which will provide a super-resolution high-quality most prominent visible light video for better human visualization and background motions or gesticulations of the human brain. There are two approaches for increasing the current resolution level of an image. The first one is the improvement of spatial resolution by reducing the size of pixels through the techniques of sensor manufacturing by about 40 $ {\mathcal{M}}{\textrm{m}^2} $ M m 2 for a 0.35 $ {\mathcal{M}}\textrm{m} $ M m CMOS process and the second approach is the enhancement of chip size that also enhances the capacitance. In video processing, we mainly focus on object images, i.e. any form of signal processing in which the input is an image and the output is a photograph or a frame of video. So, it will be better to converge over techniques of digital image processing. In the proposed algorithm (MHI Simulink model), edge extraction is performed to find the precious area of MRI and CT-Scan images. Using FPGA, edge detection methods have been implemented over scanned images to get better accuracy. The accuracy of the proposed method has been compared with Prewitt and Sobel's edge detection techniques. The proposed method has given better accuracy than Prewitt and Sobel methods. Finally, this paper shows future directions for researchers to enhance the characteristics of digital image and video processing. [ABSTRACT FROM AUTHOR]

This paper presents a novel extended input voltage dynamic range (IVDR) amalgamate charge pump (CP) for energy harvesting systems. The proposed amalgamate CP adaptively switches its charge transfer transistor into switch and diode connection based on the input voltage, effectively enhancing the power conversion efficiency (PCE) over a wide input voltage range. Implemented in 65 nm CMOS technology, the post‐layout results demonstrate a PCE exceeding 40% within the input voltage range of 0.36–0.85 V, under 60 kΩ load. The design achieves an extended IVDR of 0.49 V with a peak PCE of 50.02% observed at an input voltage of 0.45 V. The proposed amalgamate CP design features two distinct charge transfer transistor connections, leveraging the strength of Dickson CP with low reversion loss in high input voltage range and the low conduction loss of cross‐coupled CP (CCCP) in low input voltage range, thereby extending the input voltage operation range of conventional CP. [ABSTRACT FROM AUTHOR]

The increased short-channel effects in the ultra-nanoscale regime limit the operation of complementary metal oxide semiconductor (CMOS) technology. To combat the issues in the ultra-nanoscale regime, fin-shaped field effect transistor (FinFET) technology is the best choice because of its numerous advantages over CMOS technology. FinFET enhances the further scaling of the devices and control over the channel. Therefore, this research paper presents the implementation of a low leakage 4:2 compressor in FinFET technology. A compressor is a general block, especially used in multiplier units and hence in digital signal processing (DSP) systems. The design of the low power compressor improves the overall efficiency of the DSP systems. An extensive study of the proposed low power 4:2 compressor at 7 nm technology node is done in the paper. Mentor Graphics tools are used for the circuit simulations and analyzes. The key parameters, such as leakage power, delay, power delay product (PDP), and the process voltage temperature (PVT) variations, are estimated for the performance evaluation. The proposed 4:2 compressor saves 87.33% of leakage power and is 75.90% more energy efficient compared to its conventional counterpart. [ABSTRACT FROM AUTHOR]

This article proposed a technique for a low‐power and fast start‐up voltage‐controlled oscillator (VCO) for a high data rate 5 G New Radio (5G‐NR) application. The 5G‐NR high data rate signals require a fast start‐up VCO to accommodate the short pulse width. In this proposed work, a cross‐coupled pair (XCP) is integrated with a center‐tapped orthogonal symmetry inductor placed at the gates of the XCP, forming an inductive booster VCO (IBVCO). The inductive impedance at the gate of the XCP preserve the symmetry signal profile of the output voltage swing while alleviating the intrinsic parasitic capacitance effect and flicker noise effect of the transistor under the absence of the tail current source. The concept proves with the improvement on the phase noise performance and generating a fast start‐up without affecting the VCO bandwidth. The VCO also provides the enhancement of the output voltage swing under low power consumption. The IBVCO has been fabricated in 180 nm complementary metal oxide semiconductor technology and consumes a minimum area of only 0.7 mm2. The IBVCO achieved a 13% tuning range from 3.3 to 3.75 GHz bandwidth with a supply voltage, VDD of 0.7 V. The total power consumption is 1 mW with a corresponding phase noise of −122.60 dBc/Hz and a Figure of Merit (FoM) of 193.48 dBc/Hz at 3.52 GHz carrier center frequency at 1 MHz offset. The start‐up time of the VCO achieved is 5 ns. [ABSTRACT FROM AUTHOR]

This paper presents an inverter-based active feedback transimpedance amplifier (IAF-TIA), in which an active feedback is applied to a voltage-mode inverter-based TIA, and therefore, the controlled positive regeneration process enables the proposed IAF-TIA to achieve the limiting operations for input currents greater than 100 μApp. However, the active inverter feedback mechanism might be prone to instability, hence mandating a very careful optimization of the loop gain. For this purpose, a diode-connected NMOS transistor is employed as a switch in the feedback path with its gate connected to the input, which helps not only to mitigate the corresponding issue but also to accommodate large input currents up to 1.5 mApp. The proposed IAF-TIA implemented in a standard 180 nm CMOS process demonstrates a 70.5 dBΩ transimpedance gain, 1.21 GHz bandwidth, 4.3   pA / Hz noise current spectral density, 63.5 dB input dynamic range, and 23.6 mW power dissipation from a single 1.8 V supply. The chip core occupies an area of 180 × 50 μm2, including an on-chip P+/N-well/Deep N-well avalanche photodiode as an optical detector. [ABSTRACT FROM AUTHOR]

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The sample and hold circuit (SHC), as a key module of the analog-to-digital converters (ADCs), directly affects the sampling speed and accuracy of the entire data acquisition system. Using TSMC 0.18 μm current-mode SHC for high-speed ADC was designed using CMOS technology. The proposed circuit combines a single amplifier and negative feedback structure to eliminate clock-feed through noise and high signal-to-noise distortion ratio (SNDR) from low power supply voltage and very low current consumption. Meanwhile, a differential structure is provided to reduce distortion caused by channel charge injection. Discussed design issues such as clock feedthrough noise, channel modulation effects, and power consumption. The design verification of the proposed current-mode SHC was completed through circuit layout simulation using CMOS model parameters. The results show that, from a 1.0 V supply and with a power consumption of 54.4 μW, the proposed circuit provides 71.2 dB SNDR, 11.53 bit effective number of bits, and a figure of merit of 1.8 fJ/conversion-step when the sampling frequency is 10 KS/S. [ABSTRACT FROM AUTHOR]

This paper presents a three-stage E-band low-noise amplifier (LNA) fabricated in a 28-nm Complementary Metal Oxide Semiconductor High-Performance Compact Plus process. The proposed E-band LNA achieves a peak gain of 16.8 dB, exhibiting a gain variation of less than ±0.5 dB across the frequency range of 67.8–90.4 GHz. The measured 3-dB gain bandwidth spans from 64 to 93.8 GHz, and the minimum measured noise figure (NF) is 3.8 dB. By employing a one-stage common-source with a two-stage cascode topology, the proposed E-band LNA demonstrates competitiveness in terms of gain flatness and NF when compared to recently published E-band CMOS LNAs. [ABSTRACT FROM AUTHOR]

This paper presents the design of a synergistic arithmetic logic unit (SALU) that combines a complementary metal-oxide–semiconductor (CMOS) and memristors using the modified gate diffusion input (m_GDI) technique. The proposed design aims to reduce power consumption, delay, and the number of transistors, which are critical parameters in digital VLSI design. We have incorporated the m_GDI technique to implement the SALU, resulting in a lower number of transistors and reduced power consumption along with the delay and power delay product (PDP). The whole proposed architecture has been constructed using a basic m_GDI cell that consists of one p-type (pMOS) and two memristors. Combinational arithmetic circuits like full adder and full subtractor have been designed using the XOR-based m_GDI approach, and their performance will double that of current methods. A 1-to-8 de multiplexer circuit has also been utilized to perform 8 different operations for the ALU. Using Cadence Virtuoso tools in 45-nm technology, we have simulated the proposed design and evaluated its performance with existing designs. The proposed design has the potential to be a viable option for low-power and high-performance digital VLSI design applications. It delivers improved power, delay, and PDP characteristics while using fewer components. The power consumption, delay, and PDP of the proposed architecture are 9.71E−6 W, 2.141E−9 s, and 2.0789E−14 J, respectively. Furthermore, the design comprises just 33 pMOS transistors and 66 memristors, which is a lower count and unique combination in contrast to previous techniques. [ABSTRACT FROM AUTHOR]

An approach for the implementation of a resistorless, electronically tunable quadrature oscillator (RETQO) is proposed in this paper. The proposed circuit consists of only one EX-CCCII block and two capacitors with a ground connection. Non-ideality analyses are performed to prove the suitability of the RETQO design. The frequency of oscillation expression is obtained. The oscillator independently controls the condition of oscillation (CO) and the frequency of oscillation (FO). The acceptability of the circuit is confirmed using CMOS-based TSMC 180-nanometer technology. Also, numerous simulations based on the SPICE circuit simulator are accomplished. Moreover, experimentation has also been tested using IC AD844 which is commercially available. There is good agreement of the proposed work with existing reports. [ABSTRACT FROM AUTHOR]

This study addresses the demand for more efficient logic circuits by focusing on reducing area, power consumption, and delay. As conventional CMOS technology faces scaling and efficiency limitations, integrating emerging memory technologies like Resistive Random Access Memory (RRAM), also known as memristor, offers a promising solution. By replacing conventional PMOS transistors with memristors in CMOS logic, the study leverages the high-off resistance and low-voltage operation of RRAM devices to develop more compact and energy-efficient circuits. The proposed RRAM device is a Metal-Insulator-Metal structure fabricated with Platinum electrodes, Aluminum Oxide and Tantalum Pentoxide insulator layers. It operates with set and reset voltages of 1 V, and its current-voltage characteristics were theoretically modeled using the VTEAM model. A Memristor-based Imply and N-Imply(MINI) logic approach is introduced for XNOR, XOR and 2X1 Multiplexer designs and compared with three other hybrid NMOS-Memristor logics. Implementing 36 different 1-bit adder circuits in the Cadence Virtuoso 45 nm technology, the study evaluates area efficiency, power consumption, and delay. Results show that the memristor-based MINI logic designs are more area and powerefficient than traditional CMOS-based full adders and various optimized CMOS and memristor-based logics. This research underscores the potential of the proposed RRAM device integration in advanced hybrid logic design. [ABSTRACT FROM AUTHOR]