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First-principles calculations are used to systematically investigate the impact of surface effects on the energetic cost to incorporate point defects near the growing surface [Ge(001)] and its consequence on the dopant activation in P-doped Ge layers. We illustrate the formation enthalpy Delta H-f for the incorporation of a mono-vacancy, which is the dominant point defect responsible for the electrically inactive dopant incorporation in P-doped Ge. The calculated values point toward a significant lowering of Delta H-f near the growing surface in comparison to the bulk cubic Ge supercell. The impact of the surface almost vanishes beyond the sixth atomic monolayer located below the surface and the calculated Delta H-f values overlap with the ones computed for a bulk cubic Ge supercell. For epitaxial Ge:P layers, grown at low growth temperatures (

Integrating III-V semiconductors into next-generation silicon-based transistors is a promising alternative being considered as a route to faster and more energy-efficient electronic devices. These III-V materials will be doped, typically with Si as a dopant. However, dopant activation remains an issue, compounded by the fact there is still insufficient knowledge of the ease and preferred mechanistic pathways by which dopants, like Si, become activated within the III-V matrix. Using Density Functional Theory calculations, we have determined many of these critically important properties, namely, the energy barriers associated with the diffusion of both intrinsic point defects and silicon impurities in a prototypical ternary III-V material, here a CuAuI-ordered In0.5Ga0.5As. Refuting assumptions in the current literature, vacancy-assisted diffusion was found to be an unfavorable mechanism for this ordered ternary alloy, unlike in GaAs. Hence, substitutional Si atoms are essentially immobile on experimental timescales. While vacancies are nearly immobile, interstitials, especially split interstitials, can move easily within the crystal lattice. These defects become significant at high Si concentration leading to the unexpected phenomenon of enhanced diffusion of Si at high concentrations, which explains experimental observations.

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

Iodine-doped CdTe and Cd1−x Mg x Te layers were grown by molecular beam epitaxy. Secondary ion mass spectrometry characterization was used to measure dopant concentration, while Hall measurement was used for determining carrier concentration. Photoluminescence intensity and time-resolved photoluminescence techniques were used for optical characterization. Maximum n-type carrier concentrations of 7.4 × 1018 cm−3 for CdTe and 3 × 1017 cm−3 for Cd0.65Mg0.35Te were achieved. Studies suggest that electrically active doping with iodine is limited with dopant concentration much above these values. Dopant activation of about 80% was observed in most of the CdTe samples. The estimated activation energy is about 6 meV for CdTe and the value for Cd0.65Mg0.35Te is about 58 meV. Iodine-doped samples exhibit long lifetimes with no evidence of photoluminescence degradation with doping as high as 2 × 1018 cm−3, while indium shows substantial non-radiative recombination at carrier concentrations above 5 × 1016 cm−3. Iodine was shown to be thermally stable in CdTe at temperatures up to 600°C. Results suggest iodine may be a preferred n-type dopant compared to indium in achieving heavily doped n-type CdTe.

In order to improve electrical characteristics of FinFETs, various annealing treatments for dopant activation were studied in this work. The treatments including rapid thermal annealing (RTA), microwave annealing, and RTA-and-laser annealing with different powers were investigated. The on-current and carrier mobility of FinFET are significantly improved by a RTA-and-laser annealing with suitable power; meanwhile, the leakage current, interface characteristics and device reliability can be simultaneously maintained. The improvement can be attributed to the high thermal activation energy, less dopant diffusion, and enhanced quality of interfacial layer during the gate first processes. Therefore, a RTA-and-laser annealing with suitable power is promising for manufacturing high performance FinFET. Display Omitted Electrical characteristics of FinFETs with various annealing treatments are studied.Rapid thermal, microwave, and rapid thermal-and-laser annealing with different powers are compared.The on-current and electron mobility are enhanced by a RTA-and-laser annealing with suitable power.The improvement can be attributed to better dopant activation and less damage on gate dielectric.

The influence of extension doping on parasitic resistance and its variability has been investigated for FinFETs. Electrical characterization of FinFETs and crystallinity evaluation of the doped fin structure are carried out for different fin thicknesses and different donor species for ion implantation, i.e., As and P. Reducing the fin thickness and the use of donor species with a larger mass cause serious degradation in the variability and median value of the parasitic resistance. Crystallinity evaluation by transmission electron microscope reveals that significant crystal defects remain after dopant activation annealing for the cases of smaller fin thickness and the implanted dopant with a larger mass. The unrecovered defects cause serious degradation in the parasitic resistance and its variability.

Significant research effort has been placed into the use of III–V compound semiconductors, including InGaAs as channel materials in CMOS logic devices due to their superior electron mobilities compared to Si and other more conventional semiconductor materials. One of the major factors preventing industrial adoption of InGaAs as a channel material involves the minimization of source and drain contact resistances. To understand challenges to minimization of contact resistance, this work will outline the effectiveness of several doping approaches that have been attempted for n-type InGaAs including the use of silicon as a dopant and the effectiveness of each approach in achieving the highest level of activation possible. Previous and recently reported dopant diffusion behaviors are also included and discussed.

This work describes the development of a new method for ion implantation induced crystal damage recovery using multiple XeCl (308 nm) laser pulses with a duration of 30 ns. Experimental activity was carried on single phosphorus (P) as well as double phosphorus and aluminum (Al) implanted 4H-SiC epitaxial layers. Samples were then characterized through micro-Raman spectroscopy, Photoluminescence (PL) and Transmission Electron Microscopy (TEM) and results were compared with those coming from P implanted thermally annealed samples at 1650&ndash, 1700&ndash, 1750 &deg, C for 1 h as well as P and Al implanted samples annealed at 1650 &deg, C for 30 min. The activity outcome shows that laser annealing allows to achieve full crystal recovery in the energy density range between 0.50 and 0.60 J/cm2. Moreover, laser treated crystal shows an almost stress-free lattice with respect to thermally annealed samples that are characterized by high point and extended defects concentration. Laser annealing process, instead, allows to strongly reduce carbon vacancy (VC) concentration in the implanted area and to avoid intra-bandgap carrier recombination centres. Implanted area was almost preserved, except for some surface oxidation processes due to oxygen leakage inside the testing chamber. However, the results of this experimental activity gives way to laser annealing process viability for damage recovery and dopant activation inside the implanted area.

In this chapter, we give an overview of the basic physics and experimental method behind the conventional ion-beam modification of semiconductors. In particular, we describe the basic understanding of the keV ion implantation process used for doping Si and the fascinating amount of materials physics involved in the path from the initial implantation to the dopant activation. We also describe two recent developments related to the physics of implantation: the mechanisms of surface ripple formation and time-resolved experiments used to shed new light on defect migration and interaction processes.

The edge termination design strongly affects the ability of a power device to support the desired voltage and its reliable operation. In this paper we present three appropriate termination designs for 10kV n-IGBTs which achieve the desired blocking requirement without the need for deep and expensive implantations. Thus, they improve the ability to fabricate, minimise the cost and reduce the lattice damage due to the high implantation energy. The edge terminations presented are optimised both for achieving the widest immunity to dopant activation and to minimise the electric field at the oxide. Thus, they ensure the long-term reliability of the device. This work has shown that the optimum design for blocking voltage and widest dose window does not necessarily give the best design for reliability. Further, it has been shown that Hybrid Junction Termination Extension structure with Space Modulated Floating Field Rings can give the best result of very high termination efficiency, as high as 99%, the widest doping variation immunity and the lowest electric field in the oxide.

Thin films of degenerately doped metal oxides such as those of Sn-doped In2O3 (Sn:In2O3) are commercially significant for their broad utilization as transparent conducting electrodes in optoelectronic devices. Over the last decade, nanocrystals (NCs) of Sn:In2O3 and other doped metal oxides have also attracted interest for localized surface plasmon resonance (LSPR) that occurs in the near to mid-infrared region. The suitability of this LSPR for some applications depends on its capacity to concentrate light in small regions of space, known as near-field hot spots. This efficiency to create near-field hot spots can be judged through an LSPR figure-of-merit such as Quality factor, defined as the ratio of LSPR peak energy to its linewidth. The free electron density determines the LSPR peak energy while the extent of electron scattering controls the LSPR linewidth and hence these factors together essentially dictate the value of the Quality factor. An unfortunate tradeoff arises when dopants are introduced since the aliovalent dopants generating the free electrons (increasing LSPR energy) also act as centers of scattering of electrons (increasing LSPR linewidth), thereby decreasing the LSPR Quality factor. Dopant selection is hence of paramount importance to achieve a high value of LSPR Quality factor. Here, we describe the properties of aliovalent cationic dopants that allow both high LSPR energy and low LSPR linewidth and, subsequently, high LSPR Quality factor. In this context, we identify Zr4+ as a model aliovalent dopant for high LSPR Quality factor in the In2O3 lattice. The resulting Zr-doped In2O3 NCs exhibit one of the highest LSPR Quality factors reported in the mid-infrared region while also performing equivalently to the recognized materials for either high dopant activation (Sn:In2O3 NCs) or low LSPR linewidth (Ce-doped In2O3 NCs), simultaneously. The Zr donor level is positioned well into the conduction band of In2O3 and Zr doping is surface segregated, both minimizing electron scattering. The combination of this low electron scattering and high dopant activation of Zr4+ ions is responsible for the high LSPR Quality factors. These strategies can be used to design a variety of doped metal oxide NC systems exhibiting high LSPR Quality factors.

Copper-free polycrystalline CdTe solar cells doped with either Phosphorus, Arsenic or Antimony are compared for dopability, device performance and defect properties. In-situ doping of CdTe with group-V elements was carried out using vapor transport deposition followed by CdCl2 heat treatment. Uniform carrier concentration in ~1016 cm-3 range is achieved for all three dopants. Compatibility with CdSeTe ternary alloy is demonstrated and comparable quantum efficiency for all three dopants suggests that either dopant could serve as a replacement for copper. These results are compared with previously reported carrier concentration values for group-V doping of sx- and px- CdTe. Theoretical calculation for maximum carrier concentration based on acceptor energy level suggests least ionization of Antimony. Compensation worsens the achievable majority carrier concentration despite high acceptor doping.

Germanium is an important mainstream material for many nanoelectronic and sensor applications. The understanding of diffusion at an atomic level is important for fundamental and technological reasons. In the present review, we focus on the description of recent studies concerning n-type dopants, isovalent atoms, p-type dopants, and metallic and oxygen diffusion in germanium. Defect engineering strategies considered by the community over the past decade are discussed in view of their potential application to other systems.

The record low contact resistivity $(\rho_{\text{c}})$ of $4.4\text{x}10^{-10}\Omega-\text{cm}^{2}$ is achieved in Ti metal contact to in-situ B-doped $\text{GeSn}$ using B $(> 1\text{x}10^{21}\text{cm}^{-3})$ and Sn $(> 12\%)$ segregations at the Ti/GeSn:B interface. Sn incorporation into Ge lowers the Schottky barrier height of holes. Increasing B doping at the $\text{Ti}/\text{GeSn}:\text{B}$ interface reduces the hole tunneling distance. Thanks to the low growth temperature (305°C) of the chemical vapor deposition using Ge2H6, the GeSn:B with the bulk active [B] of $2.1\text{x}10^{20}\text{cm}^{-3} (>> > \text{the}$ solid solubility of B in $\text{Ge}=5.5\text{x}10^{18}\text{cm}^{-3}$ ) and the bulk [Sn] of 4.9% is successfully grown. Without the needs of the previously reported Ga dopants and the high temperature annealing for dopant activation, the record low $\rho_{\text{c}}$ is achieved with all the process temperatures $\leq 400^{\text{o}}\text{C}$ .

Herein we present a pulsed laser processing method for crystallization and dopant activation of a highly n-doped amorphous silicon (a-Si:H) carrier selective layer for high conductivity, high carrier lifetime, low emitter saturation current and limited surface layer heating as opposed to high temperature furnace annealing induced heating of the bulk Si wafer. We demonstrate increased crystallinity and reduced layer resistivity, without impacting surface passivation quality. Additionally, we examine the role of forming gas annealing (FGA) on further improving the passivation of laser-processed polysilicon layers to achieve a OC ), and 27 fA/cm2 recombination current density (J 0 ) with the potential for further passivation improvement via laser process optimization.

A possible effect of solidification velocity on activation of surface segregated Ga, In, and Al in high Ge content SiGe after UV melt laser anneal has been discussed. The experiment has shown that this effect depends on the atomic size of the dopants, implying that the solidification velocity may dominate the incorporation of the dopants into active substitutional sites. The control of the solidification velocity may play a key role for improving dopant activation over an equilibrium solid solubility limit.

High dopant (phosphorus) activation of 24% and 27% in strained and relaxed Ge 0.93 Sn 0.07 films are demonstrated by microwave annealing, respectively. The annealing effects on the carrier activation in strained and relaxed GeSn films by RTA and MWA were also investigated.

In this paper, we report on the phase selectivity in Cr and N co-doped TiO2 (TiO2:Cr,N) sputtered films by means of interface engineering. In particular, monolithic TiO2:Cr,N films produced by continuous growth conditions result in the formation of a mixed-phase oxide with dominant rutile character. On the contrary, modulated growth by starting with a single-phase anatase TiO2:N buffer layer, can be used to imprint the anatase structure to a subsequent TiO2:Cr,N layer. The robustness of the process with respect to the growth conditions has also been investigated, especially regarding the maximum Cr content (, The research leading to these results has received funding from projects RTI2018-095137-B-I00 and MAT2016-80394-R from Ministerio de Ciencia, Innovación y Universidades (Spain) and grant agreement n° 226716 from the European Community’s Seventh Framework Programme (FP7/2007-2013). Funding of TEM Talos F200X by the German Federal Ministry of Education of Research (BMBF) through Grant No. 03SF0451 in the framework of HEMCP is gratefully acknowledged.

Producción Científica, Junction stability and donor deactivation in silicon at high doping limit has been a long-standing issue in advanced semiconductor devices. Recently, heavily doped epitaxial Si:P layer with phosphorus concentrations as high as 3 × 1021 at./cm3 has been employed in nanowire field-effect transistor (FET) devices for sub-3 nm technology node as low resistance source-drain and channel stressor. In such highly doped Si:P, the actual dopant activation is much less than nominal phosphorus concentration due to inactive phosphorus atoms arising from dopant-vacancy defects (PnV) clustering phenomenon. Even with state-of-the-art high temperature millisecond annealing, this epitaxial film is thermally unstable upon subsequent thermal treatments. To overcome this limitation, we demonstrate a selective dopant activation scheme which results from the dipole moments of inactive PnV structures within the crystal lattice and their direct energy coupling with the external electric field. It's found that superior stability in dopant activation can be achieved through microwave annealing when a specific temperature and field conditions are met using a triple-parallel-susceptor setup in the microwave cavity. Based on experimental results and ab-initio calculation, we proposed a model, whereas the microwave-PnV interactions result in a specific distribution of dopant defect dominated by thermally stable P4V clusters through elimination of unstable low order PnV, leading to the suppression of donor deactivation and achieving thermally stable junction., Ministerio de Ciencia, Innovación y Universidades (Project MOST-109-2628-M-008-004-MY3)

We demonstrate Si-implanted AlN with high conductivity (>1 Ω−1 cm−1) and high carrier concentration (5 × 1018 cm−3). This was enabled by Si implantation into AlN with a low threading dislocation density (TDD) (

The aspects of Si+ implantation for low resistivity ohmic contact formation to gallium nitride (GaN) with moderate annealing temperatures for dopant activation were studied: encapsulation layer and temperature for activation annealing, and implantation fluence. The uniqueness of our approach was to implant GaN through a SiO2 retarding layer, which shifted the dopant distribution, allowing us to obtain a quasi-uniform Si profile with just one implantation. The retarding layer was extensively studied both theoretically and experimentally and its applicability for the formation of good ohmic contacts was presented. We characterized GaN after Si doping by electrical and structural methods, the latter supported by depth profiles of point and extended defects, calculated by McChasy simulation code based on measured Rutherford Backscattering/channeling spectra. Implantation with 250 keV Si+ to the effective fluence of 1.1×1016 cm−2 allowed us to obtain the best electrical parameters, sheet resistances RSH ≲ 50 Ω/sq. and specific contact resistance RC ≲ 0.1 Ω⋅mm and ρC ≈ 2×10−7 Ω⋅cm2, although there were still defects present.

Detailed information about the recrystallization and formation of defects in the ultra-shallow junction of implanted Si is a key for semiconductor fabrication below 20 nm regime. The surface quality of highly doped Si via annealing treatment would influence the fabrication and yield. Here, we employ nonlinear optics to study the correlated physical phenomena and underlying evolution of restructure of P + ion implanted Si. Reflective second harmonic generation (RSHG) results reveal the restructure of the implanted Si layer that involves recrystallization, dopant activation and dopant diffusion in correlation with annealing temperature. In the implanted Si layer, defects cause inactivity in electrical properties and generate isotropic dipole contribution to the RSHG pattern. The trend of isotropic dipole contribution is consistent with the sheet resistance measurement that presents more information about the evolution of the restructure. At lower annealing temperatures, the precipitation and the interstitialcy pairs form due to the effect of transient enhanced diffusion, and then the isotropic contribution of the RSHG pattern and sheet resistance sharply increases because of aggregation of the dopants. The isotropic contribution of RSHG is an index of the transformation of the electrical property as well as estimate recrystallization during rapid thermal annealing.

Advanced wafer-level packaging (WLP) techniques, mainly driven by high performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology has been widely studied and developed over the last decade for use in various WLP technologies, such as package-on-package (PoP), fan-out integration, and 2.5-D and 3-D integration using through-silicon-via (TSV). Temporary bonding technology enables handling of thinned substrates ( In this study, a series of formulations based on polar thermoplastics were developed for temporary wafer bonding applications. These materials target high temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All of these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (TTV < 5 μm) after grinding and have successfully passed a 200°C PECVD process without any delamination during grinding and PECVD processes.

Germanium n+/p junctions with high phosphorus dopant activation (>1020 cm−3) and minimal dopant diffusion were achieved by $P$ implantation and laser spike annealing (LSA) at temperatures ≥794 °C for 400 $\mu \text{s}$ . In addition, there is no evidence of any residual extended defectivity near the junction after LSA. The effect of F co-doping was also investigated, demonstrating the reduction in both diffusion and activation. The thermal stability and electrical characteristics of Ge n+/p junction activated by LSA were evaluated.

In this work, we investigated a low-thermal-budget dopant activation process based on microwave annealing (MWA) of phosphorus ions implanted by plasma doping and compared the proposed technique with the conventional furnace annealing and the rapid thermal annealing processes. We fabricated p-n junction diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs) on silicon and silicon-on-insulator substrates, respectively, in order to examine the dopant activation resulting from MWA. The investigated low-thermal-budget MWA technique proved effective for implanted dopant atom activation and diffusion suppression. In addition, a good interface property between the gate oxide and the silicon channel was achieved. Thus, low-thermal-budget MWA is a promising and effective method for the fabrication of highly-integrated semiconductor devices.

Rapid thermal annealing (RTA) enabled shallow junction formation requires very short time annealing at high temperatures for low thermal budget. RTA is typically done by lamp-based radiant heating. Radiant power from lamp arrays is close-loop controlled to execute the temperature of the Si wafer as programmed. The increase of annealing temperature and the decrease of annealing time are generally required for more aggressive device scaling. However, the use of non-equilibrium radiant heat sources (photon energy from lamp arrays) makes the heating process sensitive to the optical properties of the Si wafers. Local temperature non-uniformity during RTA is considered an important contributor for within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. This phenomenon is often referred to as “pattern effect” known from the early days of RTA introduction in the semiconductor industry. In efforts to reduce the “pattern effect”, various approaches have been proposed and implemented in device manufacturing. Shielding device patterns from the radiant heat source is a common approach, having limited success. It is done by either placing a dummy wafer on the pattern side of the Si wafer or backside heating. One other common approach is to homogenize the optical properties of the pattern side of Si wafer by either adding an optical absorption layer or dummy patterns. A differential thermal energy control technique is also proposed for pattern effect suppression. Non-radiative heating techniques have been proposed and demonstrated effectiveness of this “pattern effect” suppression. In this paper, various silicide contact formations on implanted single crystalline Si in source/drain region and implanted poly-Si in gate region were studied over wide ranges of RTA temperature and time using a hot wall RTA system which uses mainly natural convection and conduction through ambient gas. Dopant profiles of the silicide and doped Si after silicidation in the hot wall RTA system were characterized. Proposed possible silicide formation and dopant diffusion mechanisms are discussed. Differences between radiant heating and non-radiant heating on the silicide formation and dopant profiles are compared. The pattern and emissivity insensitive dopant activation and silicide contact formation annealing results will be introduced and potential applications of the hot wall RTA technique in advanced CMOS devices will be proposed.

In this Letter, high-temperature ion implantation and low-temperature microwave annealing were employed to achieve maximum n-type active concentration, which can be fully activated in germanium. To use the characteristic of microwave annealing more effectively, two-step microwave annealing was also employed. In the first step annealing, a high-power (1200 W; 425 °C) microwave was used to achieve solid-state epitaxial regrowth (SPER) and enhance microwave absorption. In the second step of annealing, unlike in conventional thermal annealing, which requires a higher energy to activate the dopant, a low-power (900W;375 °C) microwave was used to achieve lowest sheet resistance 78Ω/□ and maximum active concentration 1.025×1020 P/cm3, which close to its solid solubility limit of 2×1020 P/cm3.

In this study, the application of atmospheric pressure thermal plasma jet (TPJ) annealing for impurity activation in 4H–SiC is reported. The activation of phosphorus atoms implanted at 300°C in 4H–SiC by TPJ irradiation and analysis of its crystallinity are investigated. At the maximum annealing temperature of 1630°C, the minimum resistivity value is 3.1 mΩ·cm and the maximum carrier concentration value is 2.0 × 1020 cm−3. Orientation analysis suggests that the sample implanted at 300°C was recrystallized to a 4H–SiC(0001) structure after 1630°C annealing. Furthermore, a significant increase in the carrier concentration was observed with the increasing cooling rate during the activation annealing process. Rapid cooling may suppress the impurity deactivation. These results suggest that short-time high-temperature TPJ irradiation annealing is effective for P dopant activation in 4H–SiC.

3D sequential integration enables the full use of the third dimension thanks to its unique contact density far above the possibilities of 3D packaging solutions. However, as the transistors are sequentially stacked over each other, the thermal budget allowed for the fabrication of the top transistor is limited by the maximal temperature accepted by the already made bottom one. It was previously described that a thermal budget of T > 500 °C is enough to degrade the bottom transistors performance. So the technological challenge is to develop low temperature routines for the fabrication of the top devices. For that, different processes have to be adapted, mainly the dopant activation step, where the T > 1000 °C spike annealing must be replaced. In this contribution, we present the feasibility to dope by solid phase epitaxial regrowth (SPER) at 450 °C thin Si films (22 nm) containing high dopant concentration of 5 × 10 20 at/cm 3 . For n- and p-type dopants, the 450 °C SPER rendered low sheet resistance values, as low as the ones obtained with the high temperature activation method.