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BACKGROUND: In malignant tumours of the female reproductive system, cervical cancer is second only to breast cancer, seriously threatening the health and safety of most women. OBJECTIVE: To evaluate the clinical value of 3.0 T multimodal nuclear magnetic resonance imaging (MRI) in the International Federation of Gynecology and Obstetrics' (FIGO) staging of cervical cancer. METHODS: The clinical data of 30 patients with pathologically diagnosed cervical cancer admitted to our hospital from January 2018 to August 2022 were analysed retrospectively. Before treatment, all patients were examined with conventional MRI, diffusion-weighted imaging and multi-directional contrast-enhanced imaging. RESULTS: The accuracy of multimodal MRI in the FIGO staging of cervical cancer (29/30, 96.7%) was significantly higher than the accuracy obtained in a control group (21/30, 70.0%), with a statistically significant difference (p = 0.013). In addition, there was good agreement between two observers applying multimodal imaging (kappa = 0.881) and moderate agreement between two observers in the control group (kappa = 0.538). CONCLUSION: Multimodal MRI can evaluate cervical cancer comprehensively and accurately to enable accurate FIGO staging, providing significant evidence for clinical operation planning and subsequent combined therapy. [ABSTRACT FROM AUTHOR]

In order to improve the unified shading processor efficiency of the mobile graphics processor and reduce the number of accesses between it and the off-chip memory, this paper presents a four-port texture cache architecture. This architecture uses texture mapping based on Mipamp algorithm and the storage mode of different single-port cache is selected based on Level of Detail(LOD), which improves the hit rate of texture cache.In addition, in order to improve data throughput, four ports supporting 4 parallel reading are designed. FIFO buffer is designed for prefetching memory data and reducing memory latency. Using SV to build an experimental platform to test texture images，the results show that the average hit rate is about 92.5%, and the rate of data throughput is nearly 4 times that of the single port cache.

With the increasing number of processor cores integrated on-chip, the problem of “storage walls” in reconfigurable array processors is increasing. Traditionally, the use of multi-level shared Cache hardware design has high complexity and limited parallel access, and it is difficult to meet the memory requirements of reconfigurable array processors. This paper designs a local-priority, global-shared“physical distribution, unified logic” distributed Cache structure. The hardware overhead of this structure is small and parallel access is high. The Xilinx Virtex-6 series xc6vlx550T development board was used to test the design. The experimental results show that the average delay of proposed architecture is reduced by up to 30% compared with the similar structure, and the hardware overhead is only 5% of the Cache capacity. The maximum memory access bandwidth is 10.512 GB/s.

This paper considers the product service scheduling problem with service matching. This problem is a complex scheduling problem that integrates multiple traveling salesman problem (MTSP) and multiple service types. To solve the problem, a tabu search method was presented. With the objective of minimizing the total of engineers’ travel distances, total of the customer penalty values, and makespan, an optimization model of this problem is established. The historical search solutions are taken as tabu object, and limiting the quantity of search neighborhood solution is taken as the aspiration level. At last, the adaptability, validity, and stability of the model are verified by an example.