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This paper presents an advanced modeling technology on wafer warpage after post mold curing (PMC) for the 12 inch mold-1st Fan-Out Wafer Level Packaging (FOWLP) with consideration of effects of viscoelastic model and chemical cure shrinkage, and layer design of the mold-1st packages. Results show that warpage of mold-1st FOWLP wafer predicted by the advanced modeling technology agrees well with the experimental result. A new guideline for FOWLP process flow is provided as well, which will be useful to the packaging industry. The advantages of the new guideline for FOWLP process flow are: (1) to eliminate wafer warpage correction process and save a lot of cost and time; (2) to serve as a basis for process selection to meet the trends and needs of a reliable fan-out wafer level package with lower wafer warpage during FOWLP wafer process; and (3) to be important to enhance survivability during wafer process and thin-wafer handling.

With the drive towards adding more functionality on a system and the era of artificial intelligence and IoT in play, the semiconductor industry has responded by moving away from the Moore's law approach of shrinking the chip and instead focusing on 3D integration of dies and/or packages. While by itself this poses significant challenges in the manufacturing and testing of these new architectures, there is also a need to address the issues this creates for the design flow itself. The key difference in design flow is the increasing number of iterations, not only of designs, but also the combination of designs. One die may be used across multiple packages or PCBs. This necessitates the need to create flows which are cognizant of variations. Added to this is the complexity of having to tackle new architectures like fan out wafer-level packaging or 3D ICs. The classical methodology of passing the design information from the between chip/package and package/PCB teams will be much too restrictive, costly and potentially the key to faster time-to-market product. This paper explores the solution to this the complex system connectivity optimization challenge and further demonstrates a way to track and verify connection changes throughout the design process.

Within the European funded project smart-MEMPHIS the goal was to tackle the main challenge for all smart devices – self-powering. The project was aimed to design, manufacture and test a miniaturized autonomous energy supply based on harvesting vibrational energy with piezo-MEMS energy harvesters. Cost effective packaging was needed for 3D system integration of a MEMS-based multi-axis energy harvester, an ultra-low-power ASIC to manage the variations of the frequency and harvested power, and a miniaturized energy storing supercapacitor. Miniaturization was another key demand as target applications were a leadless pacemaker and a wireless sensor network for structural health monitoring. Panel Level Packaging (PLP) was selected as packaging technology for the harvester components. A basic study on the embedding of piezo-MEMS harvester has been performed as well as the development and proof of concept of a new PLP based supercapacitor housing. For the power management unit an ASIC together with two capacitors have been integrated by Fan-out Panel Level Packaging (FOPLP). Material selection and process development was first done on wafer level size and then transferred to large area 457x305 mm2 panel size. Main focus was here to find a suitable material combination and process parameters for the embedding of SMD capacitors together with bare dies in a fan-out panel level package. A technology study has been performed to analyze the influence of SMD component size and pitch, thermal release tape and epoxy molding compound type during compression molding. Results have used to finally select materials for prototype built. Reliability testing have been performed to prove the overall concept and material selection for PLP.

The demand for higher functionality devices drives integration technologies in the third dimension to overcome limitations in Moore's Law. One popular example for 3D Integration is Package-on-Package (PoP), where memory stacks are mounted above the processor. Heterogeneous Integration (HI) is one of the key technologies to meet future fan-out (FO) application standards using higher bandwidths and higher chip-to-chip interconnection density or IO density. However, HI brings new challenges like large-area panel production and design limitations. Fast increasing package size in combination with insufficient increase in stepper reticle size is inhibiting designs for large packages and HI applications. A solution which provides limitless design and fine resolution patterning capabilities is a full-field projection scanner. For next generation FO applications, a projection scanner provides superior performance compared to a stepper by enabling limitless design, allowing dies of any size and patterning of non-repeated features at higher throughput and lower cost. This paper presents technical challenges and provides solutions for future HI FO applications, using a full-field exposure system for large package integration, eliminating low yielding stitching steps. High accuracy overlay, fine resolution for RDL routing and large depth of focus (DOF) for thick resist applications with high aspect ratio is demonstrated. The extendibility to large panel packaging integration is discussed.

In this invited talk, we will present some recent progresses on wafer scale integration of GaAs, InP, InAs and GaSb thin film templates on Si substrates using innovative smart cutting by ion implantation, wafer bonding, splitting and surface treatment. High quality thin film templates (less than 0.5 μm thick) with a surface roughness less than 1 nm and a line-width of less than 100 seconds in X-ray diffraction are achieved. Quantum well structures epitaxially grown on such templates by molecular beam epitaxy reveal comparable photoluminescence properties with those grown on commercial III-V substrates.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger rectangular substrates formats are targeted.

New microelectronics applications such as smartphones, automotive computing and server/AI CPUs heavily rely on wafer-level packaging (WLP) to meet performance targets. To meet future cost targets as well, Outsourced Semiconductor Assembly and Test (OSAT) foundries look to panel level packaging (PLP) for significant cost reduction. One of the most difficult parameters for PLP is to establish an economical process for 2/2μm line/space fine line plating with good deposition speed as well as good uniformity. Due to the different handling and panel plating equipment originating from the PCB industry, target line/space dimensions were typically 20/20μm down to 10/10μm, which was easier to achieve considering the lack of rotational movement, large substrate size and substrate surface quality.We present the successful scaling of high speed, extremely uniform plating technology from horizontal wafer plating to vertical panel plating. Using the patented high speed plate technology, we are capable to inject cation-rich electrolyte very close to the substrate surface, with the possibility of disturbing and breaking the surface boundary layer. Within the same plate, we have electrolyte removal holes that allow a direct path to the anode, which allows for uniform electrical fields within 5% all over the substrate surface.

Developing reliable and tunable metamaterials is fundamental to next-generation optical-based nanodevices and computing schemes. In this review, an overview of recent progress made with a unique group of ceramic-based functional nanocomposites, i.e., vertically aligned nanocomposites (VANs), is presented, with the focus on the tunable anisotropic optical properties. Using a self-assembling bottom-up deposition method, the as-grown VANs present great promise in terms of structural flexibility and property tunability. Such broad tunability of functionalities is achieved through VAN designs, material selection, growth control, and strain coupling. The as-grown multi-phase VAN films also present enormous advantages, including wafer scale integration, epitaxial quality, sharp atomic interface, as well as designable materials and geometries. This review also covers the research directions with practical device potentials, such as multiplex sensing, high-temperature plasmonics, magneto-optical switching, as well as photonic circuits.

Advancements of modern electronics have demanded to incorporate a diverse set of additional functionalities into device platforms such as high mechanical deformability and improved material/process sustainability. Traditional silicon (Si) wafers-based device manufacturing is intrinsically limited in realizing such novel aspects owing to their rigid/bulky nature as well as complex and unsustainable process schemes. Two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors are highly promising owing to their extremely large mechanical flexibility and near atom thickness coupled with van der Waals (vdW) attraction-enabled relaxed assembly requirement. Major challenges for realizing such opportunities for emerging electronics have been associated with a lack of reliable manufacturing methods to precisely separate 2D TMD layers from original growth wafers and integrate them on desired functional substrates in a controllable, scalable, and sustainable manner. In this talk, I will discuss recent efforts in my group on exploring viable manufacturing strategies to assemble wafer-scale 2D TMD layers of heterogeneously tailored components on arbitrary substrates. We grew various 2D TMD layers of controlled layer orientation on specially-treated growth substrates with high hydrophilicity or water solubility via a chemical vapor deposition (CVD) process. By taking advantage of the large surface energy contrast between growth substrates vs. grown 2D TMDs, we precisely peel off wafer-scale 2D TMD layers from their original substrates using water preserving their intrinsic structural/chemical integrity. We then integrate them on substrates of virtually unrestricted kinds and shapes in a layer-by-layer fashion, realizing heterogeneously-assembled wafer-scale 2D TMDs layers on a variety of exotic substrates impossible with any conventional approaches. The achieved material quality has been characterized via extensive microscopy/spectroscopy techniques, and the original substrates have been sustainably recycled for sequential growth and integration. Several demonstrations of 2D TMDs-enabled mechanically reconfigurable electronic devices will be presented, which will be impossible with any other traditional materials. This novel manufacturing strategy is believed to greatly broaden the applicability of 2D TMDs in emerging areas of electronics such as three-dimensionally conformal electronic devices of unconventional forms factors.

This paper presents the design and measurement of a 50 Gb/s PAM-4 optical modulator driver in a $0.25\ \mu \text{m}$ SiGe:C BiCMOS process and analyzes the RF performance of a new photonic-electronic wafer scale packaging technology and its impact on the eye diagram of the driver. In the new wafer scale packaging technology $7\ \mu \text{m}$ through polymer vias are created to connect an InP photonic wafer to a Silicon electronic wafer. The new through polymer vias with their small size, high density, low parasitics and strong mechanic reliability are suitable for high data rate optical communication up to 130 GBaud. A linear optical modulator driver has been designed and fabricated. It has 15 dB of gain with a 3 dB bandwidth of 24 GHz, delivers 3.2 V differentially at 50 Gb/s PAM-4 and consumes 400 mW, resulting in a figure of merit of 8 pJ/bit.

One of the most important problem for multi-chip module manufacturing technology with embedded in carrier cavities dies is ensuring surface planarity. Critical areas in this case are the gaps between the carrier and dies, filled with compound. Absence of planar surface in these areas can lead to defects in commutation layers, internal stresses and, as result, to significant decrease in assembly reliability. In this article, surface reliefs of carrier with embedded dies after molding with variety epoxy and silicone based polymers have been investigated. As a result, the minimum irregularity height of about 4 microns was achieved for optimal combination of molding compound and polyimide coating in the minimum gap with of about 250 microns.

A novel embedded silicon fan-out wafer level packaging (eSiFO), which was proposed by Huatian Technology in 2015 and now in production, has a relatively simple manufacturing process eliminating molding and de-bonding process compared to typical fan-out process. This paper briefly introduces eSiFO technology at first, and then mainly studies its electrical and thermal performance, as well as RDL reliability. This study finds that eSiFO technology has a good package performance, and can further provide optimal performance for mobile electronics and potential IoT and 5G applications.

Fan-out is arguably the fastest-growing advanced packaging technology, driven predominately by mobile processing and wireless. These designs often contain single large die, or multiple die, yet are limited in the number of available routing layers. Without the benefit of high layer counts and with substrates not much larger than the die extents, providing the ability to plan and optimize the design can significantly and positively impact the ability to provide a routable solution. This paper will discuss the challenges of designing a large FO-WLP device, as well as the capabilities required to plan, optimize, and implement the interconnect in the design in as few layers as possible. We will discuss the challenges at each phase of the design: from initial system planning and feasibility, assignment, early SI analysis, optimization and implementation, and finally sign-off.

With continuous development in packaging technology, Fan-Out Wafer Level Packaging (FOWLP) has become an established approach to reach higher integration levels and geometric efficiency. Up to now, the FOWLP market has been mainly focused on compression molding using relative thick mold caps, basically as outcome from the eWLB development started by Infineon. With the wider adoption of FOWLP, also new encapsulation processes and equipment are introduced into the market. One such technology is wafer level transfer molding. This technology progresses on the current FOWLP capabilities, and achieves the thinnest mold cap possible via a process called exposed die molding, which can only be accomplished using transfer molding. This paper discusses two of the key factors that are crucial for a successful transfer molding process of thin 12" exposed wafer level packages. First, the influence of epoxy mold compound (EMC) on warpage is discussed. Contrary to compression molding, transfer molding uses materials which so far tend to induce more warpage. This paper introduces the basics behind warpage and how this can be used to select a proper EMC. Completing this section is an indicative warpage calculation using an analytical approach. Secondly, the topic of dynamic clamping in correlation to exposed die molding is discussed. A key part of exposed die molding is the critical balance between clamping force and the fluid pressure of the injected EMC. The control strategies used to maintain this balance will be discussed in this second section. Finally, an exposed die 12" wafer level molded demonstrator is presented.

New, emerging, and existing markets demand ever-smaller electronic devices that surpass the performance of their physically larger predecessors with thinner and smaller form factors and lighter, increased functionality with faster data transfer, without sacrificing battery lifetime and affordability. Fan out wafer level packaging (FOWLP) is fast becoming the new die and wafer level packaging technology of choice for the next generation of compact, high-performance electronic devices, fulfilling the above requirements with higher I/O interconnect density and packages with multi-layer redistribution lines (RDL) with finer line/space widths. The versatility of FOWLP technologies provides the ability to expand into 3D packaging architectures such as multi-chip, system-in-package (SiP) assembly, and package-on-package (PoP) configurations.Implementing a unified FOWLP design approach requires a significant expansion in communication between the IC design world, the package design world, and a new dimension, that of communication and interaction with the OSAT/Foundry that will fabricate and assemble the complete device. FOWLP, as with other emerging High Density Advanced Packages (HDAP), have unique and often restrictive/strict rules and guidelines, a hybrid combination of traditional ASIC and organic packaging worlds.This paper will explore best-practice approaches for embarking on FOWLP design, including how to leverage your Foundry or Outsourced Substrate Assembly and Test (OSAT) partner, and how to ensure your design is manufacturable the first time to avoid expensive and time-consuming changes.

In this paper, we report a low-temperature wafer-to-wafer fusion bonding process whose maximum processing temperature is 300C and can potentially be further reduced to 250C. This low-temperature process would enhance the compatibility of the three-dimensional wafer-scale integration technology with the devices and with the temporary adhesive materials that might suffer from high-temperature FBEOL processes. Preliminary experiments are done with blanket 300mm wafers, and characterization results from SAM imaging and mechanical shear test are reported to evaluate the feasibility of the low-temperature fusion bonding process.

New microelectronics applications such as smartphones, automotive computing and server/AI CPUs heavily rely on wafer-level packaging (WLP) to meet performance targets. To meet future cost targets as well, Outsourced Semiconductor Assembly and Test (OSAT) foundries look to panel level packaging (PLP) for significant cost reduction. One of the most difficult parameters for PLP is to establish an economical process for 2/2µm line/space fine line plating with good deposition speed as well as good uniformity. Due to the different handling and panel plating equipment originating from the PCB industry, target line/space dimensions were typically 20/20µm down to 10/10µm, which was easier to achieve considering the lack of rotational movement, large substrate size and substrate surface quality.We present the successful scaling of high speed, extremely uniform plating technology from horizontal wafer plating to vertical panel plating. Using the patented high speed plate technology, we are capable to inject cation-rich electrolyte very close to the substrate surface, with the possibility of disturbing and breaking the surface boundary layer. Within the same plate, we have electrolyte removal holes that allow a direct path to the anode, which allows for uniform electrical fields within 5% all over the substrate surface.

This paper discusses techniques leveraged by the WLP packaging to reduce cost and form factor, optimize signal integrity, and improve thermal performance. Measurement results and diagrams are shared illustrating how the signal path and grounding structure improves using the WLP construction, and the paper describes how a 33 GHz bandwidth is achieved at a significantly lower cost than alternative solutions.

Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applications. However, to date its application space has been limited to a small die form factor due to challenging chip board interaction (CBI) control. The combination of ultralow dielectric constant (ULK) based advanced silicon technology and WLP is another challenge for industry to overcome.In this article, to systematically address the CBI, a large test vehicle based on 22-nm fully depleted silicon on insulator (FD-SOI) technology platform and WLP technology is described. In particular, CBI during drop test and temperature cycle on board is investigated and its failure mode analysis is discussed. The impact of silicon die thickness and ball grid array (BGA) metallurgy is also explored.

The re-distribution layer (RDL) first type fan out technology is expected to be used for the advanced packages with fine pitch wiring such as side by side die to die interconnection. To demonstrate the fabrication of RDL-first Fan out- Panel level package/wafer level package (FO-PLP/WLP), the actual package was designed. The influences of the material properties of the capillary underfill (CUF) and epoxy molding compound (EMC) on the warpage and the stress on fine patterns for the designed RDL-first FO-PLP were investigated. The numerical analysis was performed. As for the warpage, it was found that warpage can be reduced by using low modulus CUF and EMC. As for the stress on fine patterns, it was revealed that the stress concentrates at the gap between dies, the under part and the tip of the fillet of CUF. By using low Tg CUF, the stress on fine pattern was greatly reduced at 20°C. It was estimates that the low Tg of CUF is effective for the stress reduction. From these results, we selected the optimum combination of CUF and EMC for this designed package. 4 RDL layers, which include line and space of 2/2, 3/3, 5/5 and $5/ 5 \mu \mathrm{m}$ were successfully fabricated with the format size of 320 mm square. The layers were interconnected with small diameter filled Cu vias of $9 \mu \mathrm{m}$. As for the bonding of 8 dies, two bonding methods were carried out with the thermal compression bonder. One was TCB using CUF. The other was the collective bonding by TCB using NCF. Both of the bonding methods could make the solder joints and the solder wetting to the electrode from the bump. Finally the compression mold with granular material was carried out.

In Fan-Out wafer level packaging (FOWLP), errors from the die placement robot, and from expanding and shrinking mold compound in which the dies are embedded (magnification error), lead to undesirable errors in layer to layer overlay, creating increasing demands to improve lithography equipment overlay control beyond the inherent equipment capability (“tool-to-itself”). Mask-less laser direct imaging (LDI) technologies, or die-by-die alignment strategies on steppers can deal with these error contributions, but they cannot provide adequate throughput and have a high cost-of ownership, and therefore offer a limited solution for the industry. An active Optical Run-Out Correction and Beam-Steering technology for a full-field UV projection scanner has been developed, that directly translates into a better overlay for errors caused by the embedding of dies in mold compound for Chip-First FOWLP applications, without loss in resolution, printing performance, and resolution. This feature allows compensation of any type of symmetrical run-out or run-in up to + /-200 ppm, as well as asymmetrical run-out in Y up to 50 ppm. With additional alignment information, the system’s flexibility also allows for other compensation schemes, like trapezoidal or other form of compensation. In this paper, we will detail the principle and realization of this optical run-out correction technology. Performance data results for magnification error mitigation will be presented, and its effects on overlay, patterning performance, resolution, and throughput will be studied. Other properties of full-field exposure such as non-repeated dies, stitching-free exposure of any die size especially for very large packages for data center applications, and large depth-of-focus are explored. This feature is available on wafer and panel format full-field exposure systems.

TSV first or TSV last are technologies used in 3D packaging, that are now well described in the literature. However there is still room for some improvement especially in the field of TSV isolation. Certain applications such as power applications or light emitting diodes serially powered on the 230 Volts-50 Hz network require some trench isolation for wafer level packaging. In this case the breakdown voltage (up to 600 V) of the trench/TSV becomes a critical issue. In this study different organic and mineral passivation layers were tested to classify their resistance to high voltage. The impact of the Temperature process and the deposition method is shown. Some thermal oxides are also tested and the breakdown voltage is found to be around $800\mathrm{V}/ \mu \mathrm{m}$. Some FEM simulations were achieved showing the influence of the trench geometry. The oxide is then implemented on pixelated samples fabricated on 200mm highly doped Si wafers. Experimental measurements show a breakdown voltage location at the trench crossing zone and a value of $400 \mu \mathrm{m} /\mathrm{V}$ in accordance with the FEM simulations.

Crystalline optical whispering gallery mode resonators made from alkaline earth fluorides can achieve exceptionally large optical finesse, and are used in a variety of applications, from frequency stabilization and narrow linewidth lasers, to low-noise microwave generation or soliton Kerr frequency combs. Here we demonstrate an efficient coupling method to resonators of these materials, which employs photonic integrated waveguides on a chip based on silicon nitride. By converting a mode from silicon nitride to a free-hanging silica waveguide on a silicon chip, coupling to a crystalline resonator is achieved with a high extinction, while preserving a quality factor exceeding 200 million. This compact, heterogeneous integration of ultra-high Q-factor crystalline resonators with photonic waveguides provides a proof of concept for wafer scale integration and robust, compact packaging for a wide range of applications.

Fan-out wafer level packaging (FOWLP) has been an area of focus in the electronics packaging industry for multiple years now. As the technology matures, the number of applications for which FOWLP is suitable is growing. Depending on the application, FOWLP may be competing against wire bond, flip chip, embedded, interposer-based, or 3D stacked technologies. In order to make an informed decision, designers must understand not only the value of FOWLP technology, but the value of the package it seeks to replace. Technical capabilities and final package cost are the two key factors to evaluate when making this decision. This analysis focuses on package-on-package (PoP) technologies. Amkor, TSMC, and STATS ChipPAC are all examples of OSATs and foundries providing FOWLP-PoP solutions. The incumbent technology against which FOWLP-PoP is compared is flip chip packaging with through mold vias, and both process flows will be discussed. A cost and yield analysis is carried out to determine the cost implications of different design attributes, and activity based cost modeling is used. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The goal of this analysis is to understand the costs associated with variations of the FOWLP-PoP process, and to evaluate the design attributes that play a role in determining whether FOWLP-PoP or FC-PoP has the potential to be cost-effective.

This paper proposed a high-speed precision handling technology of micro-chip using programmable laser debonding technology for fan-out wafer level packaging (FOWLP) application, and investigated the programmable capability, the speed and the accuracy with laser debonding experiments on chips down to 25umX25um. The proposed FOWLP approach has features of: (a) all steps are based on wafer-level processes by using programmable laser debonding technology to achieve the reconstituted wafer, enabling high-speed precision hanldinghandling technology for micro-chip. And, (b) two bonding interface layers, one high-strength adhesive layer for chips firmly joined to handler and the other UV-sensitive layer for easily laser debonding, can improve the die-shift issues. The successfully debonding results, including selectively debonding 200umX400um chips from handler wafer and specifically debonding 25umX25um chips forming the letters "IBM", indicates the programmable capability of this technology. The experiment results show that the debonding speed can be up to 360,000 components per hour (cph), and the debonding accuracy can be in the microns range.

In the 70's, Amdahl proposed and then abandoned the concept of wafer scale integration to build a high-performance mainframe on a single silicon wafer. Recent developments in advanced packaging such as the Silicon Interconnect Fabric being worked on at UCLA, flexible electronics, three-dimensional integration allow us to revisit this concept with a very high probability of success. This talk will examine the technology, challenges, and architectural benefits of such systems for the heterogeneous integration of massively scaled-out high performance systems as well as physically flexible integration platforms for Medical applications.

Electroplated unidirectional (111) nanotwin copper has shown a high thermal stability and tensile strength. It is suitable for multi-layer fine line RDL in fan out wafer level packaging. With the line width keeps shrinking to 1μm, nanotwin copper with submicron grain size and low transition layer thickness from substrate is required. In this paper, we demonstrate a nanotwin copper of submicron grain plated using DC and proprietary additives as well as its mechanical properties and thermal stability.

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.

A high-precision Cu–Cu bonding system for 3-D ICs (3-DICs) fabrication adopting a new precision alignment methodology is proposed. A new pressure profile control system is applied in the thermocompression bonding process. Experimental results show that the alignment capability is 250 nm or better, with similar overlay accuracy ( $\vert $ average $\vert + 3\sigma )$ for permanent bonding. These developments are expected to contribute to the fabrication of future 3-DICs.

We present a novel, wafer-based fabrication process that enables integration and assembly of electronic components, such as ASICs and decoupling capacitors, with flexible interconnects. The electronic components are fabricated in, or placed on precisely defined and closely-spaced silicon islands that are connected by interconnects embedded in parylene-based flexible thin film. This fully CMOS compatible approach uses optimized DRIE processes and an SiO2 mesh-shaped mask, allowing for the simultaneous definition of micrometer- to millimeter-sized structures without compromising the flexibility of the device. In a single fabrication flow a unique freedom in dimensions of both the flexible film and the silicon islands can be achieved making this new technique ideal for the realization of semi-flexible/foldable implantable devices, where structures of different sizes have to be combined together for the ultimate miniaturization.

In this paper, we present a method to use three-dimensional wafer scale integration (3D-WSI) to build large-scale cognitive systems up to the scale of a human brain (1010 neurons, 1013 synapses). We analyze the effect of scaling by simulating some cognitive systems. The result exhibits attractive properties of the 3D-WSI technology, as compared with the traditional integration scheme using printed circuit boards. At the scale of a human brain, the 3D-WSI system reduces the communication latency by about 10X, while consuming at least 100X less communication power.

International audience; We report on a new cost effective, with a low temperature budget and simple bonding process on silicon, presenting efficient heat spreading and great potentialities in integration. This process is based on a thick electro-plated copper bonding layer through silicon vias and is expected to reduce significantly the bonded device internal temperature. We apply this process to realize 1.55-μm emitting vertical-cavity surface-emitting lasers. We demonstrate continuous wave operation from room temperature up to 55 °C, an internal temperature reduction of 13 °C, and we estimate a decrease of 30% of the overall device thermal impedance.

This analysis focuses on two of the primary variations of fan-out wafer level packaging: die-first packaging in which the die are placed face down, and die-last packaging. These two technologies share many of the same activities, but those activities occur in a different order. One key factor setting these two process flows apart is yield. Even with the assumption that the same level of defects are introduced in each process flow, the resulting total yield differs. This paper analyzes the impact of defects on the die-first and die-last processes. Each process is evaluated separately, then the two processes are directly compared across a range of designs, defect density assumptions, and incoming die cost assumptions. The cost of the processing, cost of the incoming die, and the cost of processing and die lost to scrap are included.

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. Besides developments to higher and heterogeneous integration the movement to larger formats and panel level packaging to lower cost is noticeable.

Semiconductor assembly process has been improved by wafer level packaging (WLP) introduction in high volume manufacturing. Cu-Redistribution layer (RDL) miniaturization is one of key process for small, thin and light chip manufacturing. Development of high resolution and transmittance control of photoresist is required to this technology realization on topology substrate. Photoresist development with high resolution and transmittance is required to this technology realization on the topology substrate. Chemical amplified (CA) type photoresist indicated stable sensitivity at various thickness because of high transparency at 365nm wavelength. Below 2um L&S resolution was achieved by the optimized formulation in this research.

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ∼ 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ∼ 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available.

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

One of the main advantages of 2D materials for various applications is that they can be prepared in form of water‐based solutions. The high yield and cost‐effectiveness of this method make them of great interest for printed electronics, composites, and bio‐ and healthcare technologies. However, once deposited on a substrate, etching away these solution‐processed materials is a difficult task, yet crucial for pattern definition and thus device fabrication. In particular, the realization of micrometer‐sized patterns requires mesh and paste optimization when screen‐printed or solvent‐engineered and surface functionalization when inkjet‐printed, both usually involving additional postdeposition steps. These constraints are holding back the integration of these 2D materials in devices and applications. In this work, a method for the fabrication of micrometer‐sized well‐defined patterns in water‐based 2D materials is presented, with an extensive characterization of the films and patterns obtained. The method is ultimately used to create humidity sensors with performance comparable to that of commercial ones. These sensor devices are fabricated onto a 4′ silicon and polyethylene terephthalate (PET) wafers to create all‐graphene humidity sensors that are flexible, transparent, and compatible with current complementary metal–oxide–semiconductor (CMOS) and roll‐to‐roll workflows.