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Oxidative stress is an important cause of skin injury induced by UVB radiation. Moringa oleifera also known as horseradish tree or drumstick tree, have multiple nutraceutical or pharmacological functions. However, whether Moringa oleifera protects skin against oxidative stress injury remains unknown. To investigate the effects of the ethanol extract of Moringa oleifera stem (MSE) on skin oxidative stress injury and its molecular mechanism, we first determined the effect of MSE on epidermal oxidative stress injury induced by H 2 O 2 in keratinocytes (HaCaT cells) and by UVB-radiation in mice. Then we investigated the effect of MSE on the enhancement of antioxidant system and activation of PPARα in vitro and in vivo . Furthermore, the flavonoids compositions in MSE were assayed by high-performance liquid chromatography (HPLC), and then molecular docking study was used to assess the major component in MSE to activate PPARα. Our results indicate that MSE (100–400 μg/mL) protected the epidemic cell against oxidative stress injury in vitro and topical treatment with MSE cream (6%) inhibit UVB-induced oxidative stress injury in the epidermis of the mouse skin. PPARα activation is involved in the protective effect of MSE. HPLC assay and molecular docking study indicated that rutin might be the main component in MSE to activate PPARα. These results confirm that MSE exerts the protective effect on oxidative stress induced skin keratinocytes injury. Moreover, the protective effect of MSE is mediated by enhancement of antioxidant defense systems and activation of PPARα in skin keratinocytes.

A 28-GHz voltage-controlled oscillator (VCO) with a wide tuning range and a low phase noise is presented in this paper. A PMOS-only cross-coupled pair with a lower flicker noise is exploited to provide the negative resistance. The mechanisms for enhancing the Q-factor of the LC tank at millimeter-wave (mm-wave) frequencies are analyzed and applied to optimize the proposed VCO design to obtain a low phase noise. To guarantee accurate oscillating frequencies, distributed interconnections are carefully modeled by EM simulations. Fabricated in a standard 90-nm CMOS process, the proposed VCO achieves a wide tuning range of 20.1 %, from 25 to 30.66 GHz and a low phase noise of −105.47 dBc/Hz at 1-MHz offset. The current of the core circuit is 10.5 mA under a single 1.2-V supply. The core area of the chip is 0.38 mm × 0.24 mm.

An ultra-low-power (ULP) CMOS full-band (780/868/915/2400 MHz) ZigBee receiver front-end is presented. The front-end consists of a wideband common-gate LNA and an I/Q current-commutating mixer. Current reuse and active trans-conductance (gm ) boosting techniques are utilised in this design. Details on design and optimisation method for the proposed ULP receiver front-end are provided. Measurement results for 180 nm RF CMOS implementation show the front-end has a conversion gain of 25.2 dB at sub-GHz bands and 17.5 dB at 2.4 GHz band. The minimum noise figure at sub-GHz bands is 7.3 dB. The receiver front-end consumes only 0.826 mA from a 1.0 V DC supply and the size of the core circuit is 0.052 mm2.

Human adenovirus type 12 (HAdV-12) displays a relatively low virulence and slow replication in cultured human cells, which is manifested by premature death of HAdV-12-infected cells. Whereas HAdV-2 induction of IFN-β expression was transient, HAdV-12-infected cells maintained high levels of IFN-β expression, protein kinase R (PKR) activation and eIF-2α phosphorylation throughout the infectious cycle. The importance of the IFN-inducible PKR kinase in restriction of HAdV-12 was supported by the enhanced growth of the virus following PKR knockdown in HeLa cells. Ectopic expression of HAdV-2 VA RNAI increased HAdV-12 hexon protein expression, suggesting that insufficient VA RNA expression contributes to the restricted growth of HAdV-12. Although some adenovirus species are known to persist in human lymphoid tissues, HAdV12 has so far not been found. Thus, it is possible that the inability of HAdV12 to evade the INF response may have implications for the virus to establish long-lasting or persistent infections.

A 0.2–2.5 GHz active resistive negative feedback low noise amplifier (LNA), based on current-reuse transconductance boosting technique is designed in 0.18-µm CMOS technology. The LNA has the characteristics of high gain, low noise and reasonable power consumption. Meanwhile, the input resistance feedback technology is adopted to greatly increase the matching bandwidth of the input. Post-layout simulated results get a 3-dB bandwidth of 0.2–2.5 GHz and 19.2 dB power gain. Its input/output matching is less than −10 dB in the 0.1–4.5 GHz frequency range, and the input third-order intercept point (IIP3) is greater than −9 dBm. The LNA noise figure (NF) is 2.5–3.16 dB in the 0.2–2.5 GHz. The circuit consumes 24 mW DC power from a 3 V supply and the layout size is 980 µm × 530 µm.

A fully-integrated differential transceiver for C-band, based on polyphase filters (PPFs) to achieve a high image rejection ratio (IRR), is proposed in the paper. The transceiver meets the requirements for the 5GHz band radar application, which is implemented in 1P6M 0.18μm CMOS technology. The receiver achieves 7.2dB NF, 29.3dB gain and 50.7dB IRR with 3-level digital gain controllability, while draws 93.1mA from 3.3V power supply. The transmitter achieves 16.4dBm output peak power, 29.5dB gain and 65.6dB IRR, which dissipates 138.4mA from 3.3V power supply. The die area is 2.7mm×2.9mm.

This paper presents a 6-bit active phase shifter in 0.13-μm SiGe BiCMOS technology for Ku-band phased arrays based on a phase interpolation technique. An input Marchand balun and a RC poly phase filter are used for high I/Q accuracy wideband quadrature generation with high linearity and an integrated current-mode DAC is used for controlling the amplitude of I/Q path signal to achieve 6-bit phase resolution. The phase shifter operates in the 12–18 GHz range. The simulation results show an rms phase error less than 2.61°. The average insertion gain ranges from −11.16 dB to −20.39 dB with an rms gain error less than 0.4 dB for 64 phase states. The phase shifter achieves an input P1dB of 9.98 dBm at 16 GHz for 0°-phase state. The core area of the phase shifter is 1.1×0.9 mm2, with a total current consumption of 13.4 mA from a 3.3 V supply voltage.

This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

We present a 31-45.5 GHz injection-locked frequency divider (ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 dBm. The power con- sumption is 2.88 mW under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm0.42 mm.

A 37 GHz wide-band programmable divide-by-N frequency divider (FD) composed of a divide-by-2 divider (acting as the first stage) and a divider with a division ratio range of 273–330 (acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider (with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic (DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as −20 dBm at 32 GHz and the phase noise at 37 GHz is less than −130 dBc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 mW at a supply voltage of 1.2 V and occupies an area of only 730 μm ×475 μm.

We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator (LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency (IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power (LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain (VCG) of 9.8 dB, a double sideband noise figure (DSB-NF) of 11.6 dB, and a linearity in terms of input 1 dB compression point (Pin,1dB) of −13 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 mW.

A 26–47.9 GHz ultrawideband CMOS dual injection-locked frequency divider (dual-ILFD) with high input impedance is demonstrated. As the differential input signal is injected into the gate of the PMOS tail transistor and NMOS switch transistor, the proposed divider has high input impedance and can be driven easily by the preceding driving circuits. Meanwhile, the locking range of the proposed divider is extended significantly by fully utilizing the dual-injection technique. The proposed dual-ILFD is fabricated in a standard 90-nm CMOS process and on-wafer measurements are performed. The measurements show that the free-running frequency of the divider is 19.11 GHz. At an incident power of 0 dBm, a total locking range from 26 to 47.9 GHz is achieved. The power consumption is 2.88 mW at a supply voltage of 1.2 V. The total chip size is 0.62 × 0.42 mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2126–2129, 2014

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6[Formula: see text]GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-[Formula: see text]m CMOS process. The receiver achieves 6.9-dB NF, [Formula: see text]7.5-dBm IIP3 and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41[Formula: see text]dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106[Formula: see text]mA in the Rx mode and 141[Formula: see text]mA in the Tx mode from the 3.3-V power supply.

This paper presents a low-voltage ZigBee transceiver covering a unique frequency band of 780/868/915/2400 MHz in 180 nm CMOS technology. The design consists of a receiver with a wideband variable-gain front end and a complex band-pass filter (CBPF) based on poles construction, a transmitter employing the two-point direct-modulation structure, a Ʃ-&Delta, fractional-N frequency synthesizer with two VCOs and some auxiliary circuits. The measured results show that under 1 V supply voltage, the receiver reaches &ndash, 93.8 dBm and &ndash, 102 dBm sensitivity for 2.4 GHz and sub-GHz band, respectively, and dissipates only 1.42 mW power. The frequency synthesizer achieves &ndash, 106.8 dBc/Hz and &ndash, 116.7 dBc/Hz phase noise at 1 MHz frequency offset along with 4.2 mW and 3.5 mW power consumption for 2.4 GHz and sub-GHz band, respectively. The transmitter features 2.67 dBm and 12.65 dBm maximum output power at the expense of 21.2 mW and 69.5 mW power for 2.4 GHz and sub-GHz band, respectively.

A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-&mu, m SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99&ndash, 9.33 dB, the maximum relative attenuation is 31.87&ndash, 30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58&ndash, 0.36 dB and the phase error RMS is 2.06&ndash, 3.46&deg, in the 12&ndash, 17 GHz frequency range. The total chip area is 1 &times, 0.9 mm2.

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

Human enterovirus 71 (EV71) is the main causative agent of hand, foot, and mouth disease (HFMD) and is associated with several severe neurological complications in the Asia-Pacific region. Here, we evaluated that while passive transfer of neutralizing monoclonal antibody (nMAb) against the VP2 protein protect against lethal EV71 infection in BALB/c mice. Protective nMAb were mapped to residues 141-155 of VP2 by peptide ELISA. High-resolution structural analysis showed that the epitope is part of the VP2 EF loop, which is the "puff" region that forms the "southern rim" of the canyon. Moreover, a three-dimensional structural characterization for the puff region with prior neutralizing epitopes and receptor-binding sites that can serve to inform vaccine strategies. Interestingly, using hepatitis B virus core protein (HBc) as a carrier, we demonstrated that the cross-neutralizing EV71 antibodies were induced, and the VP2 epitope immunized mice serum also conferred 100% in vivo passive protection. The mechanism of in vivo protection conferred by VP2 nMAb is in part attributed to the in vitro neutralizing titer and ability to bind authentic viral particles. Importantly, the anti-VP2(aa141-155) antibodies could inhibit the binding of human serum to EV71 virions showed that the VP2 epitope is immunodominant. Collectively, our results suggest that a broad-spectrum vaccine strategy targeting the high-affinity epitope of VP2 EF loop may elicits effective immune responses against EV71 infection.

A 0.5 V LC-VCO implemented in 0.18 μm CMOS technology for wireless sensor network is described in this paper. An improved varactor tuning technique is proposed to decrease low frequency noise up-conversion and AM---FM phase noise of VCO, also it can increase Q of LC tank and reduce power consumption of VCO. For coarse tuning of VCO, it can increase the varactor control voltage variation range. For fine tuning of VCO, it can reduce the varactor nonlinearity. The measured tuning range is 4.58---5.26 GHz and power consumption is 2.2 mW. The measured phase noise is ?114 dBc/Hz at 1 MHz frequency offset from a 4.8 GHz carrier.

A Ka-band sub-harmonically pumped resistive mixer (SHPRM) was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance (balun) with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation (LO) signal from single to differential mode. The results showed that the SHPRM achieves the conversion gain of −15–−12.5 dB at fixed f IF=0.5 GHz with 8 dBm LO input power for the radio frequency (RF) bandwidth of 28–35 GHz. The in-band LO-intermediate freqency (IF), RF-IF, and LO-RF isolations are better than 31, 34, and 36 dB, respectively. Besides, the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB, respectively. The measured input referred P1dB and 3rd-order inter-modulation intercept point (IIP3) are 0.5 and 10.5 dBm, respectively. The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm2 including pads.

An analytical model is proposed to analyse the energy recovery circuit (ERC) efficiency of plasma display panel (PDP) data driver integrated circuit (IC). The experimental measurements agree with the analysis results very well. The analysis results show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time T ERC , the channel resistor R on and the capacitance of C L . The range of T ERC is restricted in actual PDP system. C L is determined by physical parameters of PDP panel, and its value is nearly changeless. Therefore the ERC efficiency of PDP data driver IC can be improved significantly by using superior DPLD (double-channel p-type lateral extended drain metal oxidesemi conductor) transistor that has smaller R on .

The genome of T4-type Vibrio bacteriophage KVP40 has five genes predicted to encode proteins of pyridine nucleotide metabolism, of which two, nadV and natV, would suffice for an NAD+ salvage pathway. NadV is an apparent nicotinamide phosphoribosyltransferase (NAmPRTase), and NatV is an apparent bifunctional nicotinamide mononucleotide adenylyltransferase (NMNATase) and nicotinamide-adenine dinucleotide pyrophosphatase (Nudix hydrolase). Genes encoding the predicted salvage pathway were cloned and expressed in Escherichia coli, the proteins were purified, and their enzymatic properties were examined. KVP40 NadV NAmPRTase is active in vitro, and a clone complements a Salmonella mutant defective in both the bacterial de novo and salvage pathways. Similar to other NAmPRTases, the KVP40 enzyme displayed ATPase activity indicative of energy coupling in the reaction mechanism. The NatV NMNATase activity was measured in a coupled reaction system demonstrating NAD+ biosynthesis from nicotinamide, phosphoribosyl pyrophosphate, and ATP. The NatV Nudix hydrolase domain was also shown to be active, with preferred substrates of ADP-ribose, NAD+, and NADH. Expression analysis using reverse transcription-quantitative PCR (qRT-PCR) and enzyme assays of infected Vibrio parahaemolyticus cells demonstrated nadV and natV transcription during the early and delayed-early periods of infection when other KVP40 genes of nucleotide precursor metabolism are expressed. The distribution and phylogeny of NadV and NatV proteins among several large double-stranded DNA (dsDNA) myophages, and also those from some very large siphophages, suggest broad relevance of pyridine nucleotide scavenging in virus-infected cells. NAD+ biosynthesis presents another important metabolic resource control point by large, rapidly replicating dsDNA bacteriophages.

A wideband 2–3 GHz three-stage low noise amplifier (LNA) featuring current reuse, cascaded L-match input network, and multiple gated transistors method (MGTR) is designed in 0.18-μm CMOS technology. The current-reused topology is adopted to fulfill low power consumption, meanwhile, high gain and low noise are obtained. The cascaded L-match input network is used to enhance the input matching bandwidth. The MGTR is utilized to improve the linearity performance. Post-layout simulated results present a maximum power gain of 28.7 dB, a good input matching across 1.8–6.5 GHz and a high third-order input intercept point (IIP3) of-10.4 dBm. A noise figure (NF) of 3.1–3.3 dB is achieved within 2–3 GHz with a power dissipation of 6.2 mA from a 3 V power supply.

This paper presents a 24–48-GHz low power high gain low noise amplifier (LNA) in a 90-nm LP CMOS process. The asymmetrical T-coils, together with gate-inductive peaking, not only enhance the wideband gain, but also facilitate the layout design and reduce the chip area. The fabricated LNA circuit exhibits a broadband of 24–48-GHz and an average gain of 20 dB, while consuming a dc current of 17.6 mA from a 1.2 V supply. The minimum noise figure is only 3.1dB. This monolithic integrated circuit achieves excellent relative bandwidth of 67% compared with the previous published millimeter-wave (MMW) CMOS amplifiers.

ADAR1, the interferon (IFN)-inducible adenosine deaminase acting on RNA, catalyzes the C-6 deamination of adenosine (A) to produce inosine (I) in RNA substrates with a double-stranded character. Because double-stranded RNA is a known inducer of IFN, we tested the role of ADAR1 in IFN induction following virus infection. HeLa cells made stably deficient in ADAR1 (ADAR1 kd ) were compared to vector control (CON kd ) and protein kinase PKR-deficient (PKR kd ) cells for IFN-β induction following infection with either parental (wild-type [WT]) recombinant Moraten vaccine strain measles virus (MV) or isogenic knockout mutants deficient for either V (V ko ) or C (C ko ) protein expression. We observed potent IFN-β transcript induction in ADAR1 kd cells by all three viruses; in contrast, in ADAR1-sufficient CON kd cells, only the C ko mutant virus was an effective inducer and the IFN-β RNA induction was amplified by PKR. The enhanced IFN-β transcript-inducing capacity of the WT and V ko viruses seen in ADAR1-deficient cells correlated with the enhanced activation of PKR, IFN regulatory factor IRF3, and activator of transcription ATF2, reaching levels similar to those seen in C ko virus-infected cells. However, the level of IFN-β protein produced was not proportional to the level of IFN-β RNA but rather correlated inversely with the level of activated PKR. These results suggest that ADAR1 functions as an important suppressor of MV-mediated responses, including the activation of PKR and IRF3 and the induction of IFN-β RNA. Our findings further implicate a balanced interplay between PKR and ADAR1 in modulating IFN-β protein production following virus infection.

Double-stranded RNA (dsRNA) plays a centrally important role in antiviral innate immunity, both for the production of interferon (IFN) and also in the actions of IFN. Among the IFN-inducible gene products are the protein kinase regulated by RNA (PKR) and the adenosine deaminase acting on RNA 1 (ADAR1). PKR is an established key player in the antiviral actions of IFN, through dsRNA-dependent activation and subsequent phosphorylation of protein synthesis initiation factor eIF2α thereby altering the translational pattern in cells. In addition, PKR plays an important role as a positive effector that amplifies the production of IFN. ADAR1 catalyzes the deamination of adenosine (A) in RNA with double-stranded (ds) character, leading to the destabilization of RNA duplex structures and genetic recoding. By contrast to the antiviral and proapoptotic functions associated with PKR, the actions of ADAR1 in some instances are proviral and cell protective as ADAR1 functions as a suppressor of dsRNA-mediated antiviral responses including activation of PKR and interferon regulatory factor 3.

This paper presented a 12-channel parallel optical receiver front-end amplifier array design and realization in a low cost 0.18 µm CMOS technology. Each channel incorporated a transimpedance amplifier and a limiting amplifier. To meet the challenge for the design of high gain front-end amplifier at date rate of up to 10 Gb/s, an optimized circuit topology was proposed and some bandwidth extension technologies were adopted, including regulated cascode, shunt peaking, and active negative feedback. Against the power consumption, crosstalk and noise, some corresponding solutions were presented such as applying isolation structure for parallel amplifier array, and optimization of noise and circuit parameters for 10 Gb/s applications. The on-wafer measurements revealed that this chip’s operation speed reached up to 10 Gb/s per channel, and 120 Gb/s with 12-channel in parallel operation. Consuming a DC power of 853 mW from a 1.8 V supply voltage, the chip exhibits a conversion gain of up to 92.6 dBΩ, and a −3 dB bandwidth of 8 GHz, the output swing and input sensitivity for a bit-error rate of 10−12 at 10 Gb/s are 310 mV and 10 mVpp, respectively. The chip size is 1142 µm×3816 µm including on-wafer testing pads.

This letter presents a wideband transformer balun with a center open stub. Since the interconnected line between two coupled-lines greatly deteriorates the performance of balun in millimeter-wave designs, the proposed center open stub provides a good solution to further optimize the balance of balun. The proposed transformer balun with center open stub has been fabricated in 90 nm CMOS technology, with a compact chip area of 0.012 mm 2 . The balun achieves an amplitude imbalance of less than 1 dB for a frequency band ranging from 1 to 48 GHz along with a phase imbalance of less than 5 degrees for the frequency band ranging from 2 to 47 GHz.

A 1.8 mW wideband common-gate (CG) low-noise amplifier (LNA) with double capacitor-cross-coupled (CCC) feedback is presented for multiband wireless communication standards. To achieve a low-noise figure (NF) and high-voltage gain under low power consumption, the CG LNA is based on the double CCC feedback and current-reuse techniques. Post-layout simulated results for 0.18 μm CMOS implementations show that the voltage gain is 18.1 dB with a 3 dB bandwidth from 100 MHz to 1.7 GHz and the IIP3 is -4.9 dBm at 1 GHz. The average NF is 2.4 dB within the entire 3 dB bandwidth. The LNA consumes 1.8 mW from a 1.8 V DC supply and the active size is 0.15 × 0.14 mm 2 .

An ultra-low-power common-gate low noise amplifier (CG-LNA) for 2.4 GHz wireless sensor network (WSN) applications is proposed in this letter. The current-reuse and active $g_{\rm m}$ -boosting techniques are utilized. The analysis, design method and measurement results are shown. An implemented prototype using 0.18 $\mu$ m CMOS technology is evaluated using on-wafer probing. Measurements also show a gain of 14.7 dB and an ${\rm IIP}_{3}$ of 2 dBm at 2.44 GHz. The measured noise figure is 4.8 dB at 2.44 GHz. ${\rm S}_{11}$ is below ${-}18$ dB from 2–3 GHz. The proposed LNA consumes 0.58 mW from 1.8 V dc supply.

Two size forms of ADAR1 adenosine deaminase are known, one constitutively expressed (p110) and the other interferon (IFN)-induced (p150). To test the role of ADAR1 in viral infection, HeLa cells with ADAR1 stably knocked down and 293 cells overexpressing ADAR1 were utilized. Overexpression of p150 ADAR1 had no significant effect on the yield of vesicular stomatitis virus. Likewise, reduction of p110 and p150 ADAR1 proteins to less than approximately 10 to 15% of parental levels (ADAR1-deficient) had no significant effect on VSV growth in the absence of IFN treatment. However, inhibition of virus growth following IFN treatment was approximately 1 log(10) further reduced compared to ADAR1-sufficient cells. The level of phosphorylated protein kinase PKR was increased in ADAR1-deficient cells compared to ADAR1-sufficient cells following IFN treatment, regardless of viral infection. These results suggest that ADAR1 suppresses activation of PKR and inhibition of VSV growth in response to IFN treatment.

The protein kinase regulated by RNA (PKR) and the adenosine deaminase acting on RNA (ADAR1) are interferon-inducible enzymes that play important roles in biologic processes including the antiviral actions of interferons, signal transduction, and apoptosis. PKR catalyzes the RNA-dependent phosphorylation of protein synthesis initiation factor eIF-2 alpha, thereby leading to altered translational patterns in interferon-treated and virus-infected cells. PKR also modulates signal transduction responses, including the induction of interferon. ADAR1 catalyzes the deamination of adenosine (A) to generate inosine (I) in RNAs with double-stranded character. Because I is recognized as G instead of A, A-to-I editing by ADAR1 can lead to genetic recoding and altered RNA structures. The importance of PKR and ADAR1 in innate antiviral immunity is illustrated by a number of viruses that encode either RNA or protein viral gene products that antagonize PKR and ADAR1 enzymatic activity, localization, or stability.

A high performance slow-wave elevated microstrip line (SE-MSL) structure with periodical slot-type floating shields underneath the signal line is proposed in a 65-nm CMOS technology. The proposed SE-MSL demonstrates a better performance in terms of both higher effective dielectric permittivity and quality factor and a lower attenuation constant at millimeter-wave frequencies, when compared to conventional microstrip lines and coplanar waveguide structures. For a 50-Ω SE-MSL, the electromagnetic (EM) simulations show a relative effective permittivity of 29.5, an attenuation constant of 0.985 dB/mm and a quality factor of 31.85 at 60 GHz.

Human enterovirus 71 (EV71) and coxsackievirus A16 (CA16) are the major etiological agents of hand, foot and mouth disease (HFMD) and are often associated with neurological complications. Currently, several vaccine types are being developed for EV71 and CA16. In this study, we constructed a bivalent chimeric virus-like particle (VLP) presenting the VP1 (aa208-222) and VP2 (aa141-155) epitopes of EV71 using hepatitis B virus core protein (HBc) as a carrier, designated HBc-E1/2. Immunization with the chimeric VLPs HBc-E1/2 induced higher IgG titers and neutralization titers against EV71 and CA16 in vitro than immunization with only one epitope incorporated into HBc. Importantly, passive immunization with the recombinant HBc-E2 particles protected neonatal mice against lethal EV71 and CA16 infections. We demonstrate that anti-VP2 (aa141-155) sera bound authentic CA16 viral particles, whereas anti-VP1 (aa208-222) sera could not. Moreover, the anti-VP2 (aa141-155) antibodies inhibited the binding of human serum to virions, which demonstrated that the VP2 epitope is immunodominant between EV71 and CA16. These results illustrated that the chimeric VLP HBc-E1/2 is a promising candidate for a broad-spectrum HFMD vaccine and also reveals mechanisms of protection by the neighboring linear epitopes of the VP1 GH and VP2 EF loops.

The IEEE 802.11ah complements the other standards to provide support for machine-type communications (MTC) in local area network using a different spectrum from the highly congested WLAN operating at 2.4GHz/5GHz ISM bands. In order to satisfy massive station communications, the paper presents traffic indication map (TIM) compressed scheme for the Internet of Things and Smart Grid based on IEEE 802.11ah. The simulation results are discussed by evaluating the impact of the TIM compression on the system performance and cost. Results indicate that the proposed scheme has an acceptable cost and can support massive communications with higher performance enhancement. The proposed compressed TIM indication length can efficiently save the TIM bit map space and simultaneously be superior to the traditional structure.

This paper presents the design of a low power and a highly linear folded down-conversion mixer, for wideband applications, implemented in a 65nm CMOS process. Post-layout simulation results are presented. The proposed multiple-gated transistor (MGTR) based mixer achieves a linearity enhancement of 12.68 dB when compared to a conventional folded single balanced mixer operating at an input radio frequency (RF) range of 10.25∼13.75 GHz (direct conversion), with a fixed local oscillator (LO) frequency of 12 GHz and a corresponding intermediate frequency (IF) ranging from dc∼1.75 GHz. The proposed mixer combines the advantages of both gm3 cancellation and low output impedance in order to maximize linearity without employing a tuned load, hence not limiting the performance of the mixer to narrowband applications.

This paper presents a fully integrated IF module which can receive or transmit signal with only one port. The switching time between reception and transmission is less than 3µs. In the state of reception, the IF module can convert differential signal to single-ended signal. Simulation results show 3.2dB power gain and 11.65dBm OP1dB while drawing 45mA from a 3.3V supply. In the state of transmission, the IF module can convert single-ended signal to differential signal. Simulation results show 0∼15dB programmable voltage gain and −3.5dBm IP1dB while drawing 16mA from a 3.3V supply. At working frequency of 1.3GHz∼1.4GHz, VSWRs can attain high performance in two states, both are less than 1.5∶ 1. The chip is designed in 0.18µm CMOS technology, the die area is 1.5*1.5 mm2. All the components of the linearization scheme are designed on-chip enabling maintenance of a single chip transceiver solution.

A wideband double-balanced mixer using 90 nm CMOS technology is demonstrated. The DC current paths of the transconductance stage and the switch stage are separated individually by an integrated transformer balun. The primary coil is absorbed in the DC path of transconductance and functions as an inductive load. Simultaneously, the secondary coils perform as a current source of the switch stage. The transconductance employs a common gate amplifier together with the gate-inductive gain-peaking technique for providing a wideband input matching and extending the operating bandwidth. The fabricated mixer operates from 15 to 40 GHz with around 5 dB conversion gain, matches to 50 Ω over the full band and only takes up 0.39 mm 2 .

A broadband low-noise amplifier (LNA) is proposed. The active gm -boosting technique is utilised to reduce the common-gate (CG) LNA noise figure and improve gain. An implemented prototype using 0.13 μm CMOS technology is evaluated using on-wafer probing. S 11 and S 22 are below − 10 dB across 0.1–5 GHz. Measurements show a power gain of 18.3 dB with a − 3 dB bandwidth from 100 MHz to 2.1 GHz and an IIP3 of − 7 dBm at 2 GHz. The measured noise figure is better than 2.5 dB below 2.1 GHz, better than 4.5 dB below 5 GHz and at 500 MHz it obtains its minimum value 1.8 dB. The LNA consumes 14 mW from 1.5 V supply and occupies an area of 0.04 mm2.

A 1.2V wide-band programmable divide-by-N frequency divider (FD) with consecutive 16-519 division ratios has been designed and fabricated using standard 90nm CMOS technology. The programmable FD consists of a high speed divide-by-8/9 dual-modulus prescaler, a pulse counter (P counter) and a swallow counter (S counter). Dynamic current-mode logic (DCML) DFF and signal locking technique have been used in this divider to achieve high speed operation. The proposed divider exhibits wide frequency range from 7GHz to 20.5GHz and dissipates 8.52mW power consumption at 1.2V voltage supply. Utilizing this FD, a charge-pump based PLL has been realized with 31.5GHz-34GHz frequency range. The phase noise of the PLL at 34.027GHz is −91.3dBc/Hz@1MHz offset. This PLL consumes 30.72mW power and occupies 1.32mm×1.01mm chip area.