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In this paper, new type of single input and three output universal filters with current conveyor as an active element is proposed. Current conveyor works similar to operational amplifier but the input and output signals are current rather than voltage. There are several types of current conveyors exist. Out of the existing, Second order current conveyor (CCII) is chosen as an active element. The proposed circuits are designed using the similar type of active element and grounded passive components. The detailed mathematical analysis is carried out. The necessary expressions for quality factor and sensitivity are also derived. The responses of High pass filter, Low pass filter and Band pass filter are measured simultaneously. The notch and all pass filters can also be realized by adding the appropriate components. All simulation work is carried out with MULTISIM 13.0. The comparative analysis is carried out with the existing techniques and is tabulated. It has been observed that the proposed circuits works good in comparison with the existing topologies. [ABSTRACT FROM AUTHOR]

Abstract To improve the corrosion resistance of magnesium, the ceramic coatings were prepared on Mg-4.71Zn-0.6Ca alloy by micro-arc oxidation (MAO) with different current modes. The microstructure, thickness, and composition of the coatings were characterized by scanning electron microscopy (SEM) equipped with energy dispersive X-ray spectrometer (EDS) and X-ray diffraction (XRD). The electrochemical test was used to evaluate the corrosion behaviors of the Mg alloy, and the degradation rate of Mg alloy was investigated by immersion tests in Hank's solution, and the corrosion products were analyzed by EDS, XRD and fourier transform infrared spectrometer (FT-IR). The experimental results showed that the corrosion resistance of Mg-4.71Zn-0.6Ca alloy was significantly improved by MAO treatment, and the MAO Mg alloy prepared under hybrid mode exhibited the better corrosion resistance than other two modes, and the bioactivity of magnesium alloy was also improved. The MAO Mg-4.71Zn-0.6Ca alloy that prepared under hybrid mode had the potential to be served on bone repair and implant materials. Highlights • To improve the corrosion resistance of magnesium, the ceramic coatings were prepared on Mg-4.71Zn-0.6Ca alloy by micro-arc oxidation (MAO) with different current modes (unipolar, bipolar and hybrid current modes) • The influence of current modes on the morphology, structure, corrosion resistance and bioactivity of MAO coating is evaluated • The MAO Mg alloy obtained under hybrid mode showed better corrosion resistance with other modes • The bioactivity of Mg-4.71Zn-0.6Ca alloy is improved by MAO under hybrid mode, which had the potential to be served on bone repair and implant materials. [ABSTRACT FROM AUTHOR]

A novel ac coupled feedback (ACCF) is proposed to alternatively realize fast transient response while inherently controlling the start-up in-rush current of a dc–dc switching converter. The proposed ACCF is modified from a conventional capacitor multiplier and connected between the outputs of the converter and the transconductance. With this supplemental feedback, the transient response has been significantly improved due to the gain-boosting effect around the compensator’s mid-band. Moreover, the ACCF circuit assists to manage the ramping speed of the output voltage during power-up, thereby eliminating the bulky soft-start circuit. The new controller is very simple to implement and occupies a tiny footprint on-chip. A buck converter with the proposed scheme has been fabricated using the 0.18- $\mu \text{m}$ standard CMOS process with an active silicon area of 0.573 mm2. Measurement results show that the output voltage rises linearly for a soft-start period of 1.05 ms according to the designed slope. Excellent load transient responses are achieved under different load current steps; the output voltage overshoot/undershoot of 60 mV settles down within $10~\mu \text{s}$ for a load variation from $50~\mu \text{A}$ to 1 A in $1~\mu \text{s}$. Moreover, the proposed converter maintains both excellent load and line regulations of 0.018 mV/mA and 0.0056 mV/mV, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a new 8-fold current-mode sawtooth folding amplifier. In the proposed circuit the number of current mirrors in the signal path between the input and the output is minimised. This results in minimising the delay in the signal path of the 8-fold current-mode sawtooth folding amplifier. Thus, the speed of the proposed amplifier is improved while enjoying a compact design and consuming less DC power. The functionality of the proposed circuit was tested and confirmed using LFoundry 150 nm process in Cadence simulation tools. Simulation results show that 8.4 ns settling time for the full-scale rising edge and 3.5 ns for the fullscale falling edge can be achieved. For comparison with already existing folding amplifiers, the proposed circuit was scaled down to provide four folds. Simulation results obtained from the 4-fold amplifier show that a full-scale delay of 5.9 ns can be achieved. This is more than four times faster than already existing designs in the open literature. Furthermore, the simulation results obtained from a sinusoidal and a triangular input current confirm the workability of both the 4-fold and the 8-fold amplifiers. The simulation results also show that the circuit is temperature insensitive and is functioning as expected in the temperature range -25°C to 125°C. [ABSTRACT FROM AUTHOR]

Micro-arc oxidation (MAO) coatings were prepared on the AZ31 Mg alloy under the constant/gradient current control modes. The effects of current output modes on the growth rate, energy consumption, microstructure, and corrosion resistance of MAO coatings were studied. The results shows that the current step-down mode (G852) exhibited a lower unit energy consumption than the constant current mode (C5) and the current step-up mode (G258), even though the same average current density current was used during MAO process. Meanwhile, the G852 is conducive to a thick and dense coating, resulting in a better corrosion resistance. The method of energy saving preparation of corrosion resistant MAO coating by adjusting the current mode is of great significance for practical production.

Implementation of CMOS current-mode analog computational circuits are presented in this paper. A new Linearly Tunable OTA is employed in a modified structure as a basic building block for implementation of the circuits either linear or nonlinear functions. The proposed trans-conductance amplifier provides a constant Gm over a wide range of input voltage which allows the implementation of high precision computational circuits including square rooting, squaring, multiplication and division functions. Layout pattern of the proposed circuit confirms that the circuit can be implemented in 102μm*69μm active area. In order to verify the performance of the circuits, the post layout simulation results are presented through the use of HSPICE and Cadence with TSMC level 49 (BSIM3v3) parameters for 0.18 μm CMOS technology, where under supply voltage of 1.8 V, the maximum relative error of the circuits within 500 µA of input range is about 11 μA (2.2 % error) and the THD remains as low as 1.2 % for the worst case. Moreover, the power dissipation of the complete structure is found to be 0.66 mW.

this paper presents a novel fully differential (FD) ultra high common mode rejection ratio (CMRR) current operational amplifier (COA) with very low input impedance. Its FD structure that attenuates common mode signals over all stages grants ultra high CMRR and power supply rejection ratio (PSRR) that makes it suitable for mixed mode and accurate applications. Its performance is verified by HSPICE simulations using TSMC 0.18µm CMOS technology and ±0.75V supply voltage that indicate such outstanding results of 81.1dB gain,298MHz gain-bandwidth product, 64º phase margin, 28.2m&Omega input impedance, 159dB CMRR and PSRR+/PSRR- of 174dB/163dB all at low power consumption of 0.302mW.To study the robustness of the COA against technology and get such results close to measurement, Monte Carlo analysis is applied on both pre- layout and post layout simulations of the design. The results are as 73.29dB and 2.07MHz, 1.92&Omega, and150.35dB for Ai magnitude and bandwidth, Ri, and CMRR, respectively, in pre-layout case while change to 66.58dB and 1.44 MHz, 11.07 &Omega, and 147.10dB, for the same arrange, in post layout case. These measurement-like results thus, prove excellent practical performance of the proposed COA.

This paper describes the design of current mode low-pass ladder filters based on CMOS technology. The filters are derived from passive RLC ladder filter prototypes using new CMOS lossy and lossless integrators. The all-pole and Elliptic approximations are used in the proposed low-pass filter realizations. The proposed two types of filter can be electronically tuned between 10kHz and 100MHz through bias current from 0.03µA to 300µA. The proposed filters use 1.5 V power supply with 3 mW power consumption at 300 µA bias current. The proposed filters are resistorless, use grounded capacitors and are suitable for further integration. The total harmonic distortion (THD) of the low-pass filters is less than 1% over the operating frequency range. PSPICE simulation results, obtained by using TSMC 0.18µm technology, confirm the presented theory.

This work presents the design of a discrete second-generation voltage conveyor (VCII) and its capability to be used as electronic interface for silicon photomultipliers. The design addressed here exploits directly at the transistor level, with commercial components, the proposed interface; the obtained performance is valuable considering both the discrete elements and the application. The architecture adopted here realizes a transimpedance amplifier that is also able to drive very high input impedance, as usually requested by photons detection. Schematic and circuital design of the discrete second-generation voltage conveyor is presented and discussed. The complete circuit interface requires a bias current of 20 mA with a dual 5V supply voltage; it has a useful bandwidth of about 106 MHz, and considering also the reduced dimensions, it is a good candidate to be used in portable applications without the need of high-cost dedicated integrated circuits.

In this paper, the second-generation CMOS currentcontrolled- current-conveyor based on differential pair of operational transconductance amplifier has been researched and presented. Since the major improvement of its parasitic resistance at x-port can be linearly controlled by an input bias current, the proposed building block is then called “The Second-Generation Electronically-tunable Current-controlled Current Conveyor” (ECCCI). The applications are demonstrated in form of both 2 quadrant and 4 quadrant current-mode signal multiplier circuits. Characteristics of the proposed ECCCII and its application are simulated by the PSPICE program from which the results are proved to be in agreement with the theory.

This paper proposes a new single resistance controlled sinusoidal oscillator (SRCO) which employs only one voltage differencing current conveyor (VDCC), two grounded resistors and two grounded capacitors. The presented circuit configuration offers the following advantageous features (i) explicit current-mode output with independent control of condition of oscillation (CO) and frequency of oscillation (FO) (ii) low active and passive sensitivities and (iii) a very good frequency stability. The proposed structure can also be configured as (a) trans-admittance low pass filter and band pass filter and (b) quadrature oscillator. The validity of the proposed SRCO, quadrature oscillator and trans-admittance low pass filter and band pass filter has been verified by PSPICE simulations using TSMC CMOS 0.18μm process model parameters.

A wireless RF receiver system suitable for Internet-of-Things (IoT) applications is presented. The system is able to simultaneously harvest energy from out-of-band blockers with normal receiver operation; thus, the battery life for IoT applications can be extended. The system has only a single antenna for simultaneous RF energy harvesting and wireless reception. The receiver is a mixer-first quadrature receiver to tolerate large unavoidable blockers. The system is implemented in 180-nm CMOS technology and operates at a 900-MHz industrial, scientific, and medical band. The receiver gain is 41.5 dB. Operating from a 1-V supply, the receiver core consumes 430 $\mu \text{W}$. Furthermore, this power can be reduced to $220~\mu \text{W}$ in the presence of a large blocker (${\approx} 0$ dBm) by the power provided by the blocker RF energy harvesting where the power conversion efficiency is 30%. [ABSTRACT FROM AUTHOR]

This paper gives an overview of how CMOS design methods can be applied to ion-sensitive field effect transistor (ISFETs) for pH-based DNA methylation and miRNA detection. Design specifications are fundamentally defined by the choice of analysis. As such, the focus for DNA methylation was on developing front-end analogue circuits to carry out Methylation-specific PCR (MSP) for Point-of-Care applications, and sequencing for detailed analysis. The use of MSP prompted the design of an ISFET weak inversion current mirror topology for differential sensing and reduction of drift and temperature sensitivities. The primary limitation in ion-semiconductor sequencing is base calling of repeated nucleotides known as homopolymers. Implementation of a switched current integrator can potentially increase both accuracy and window for detection, within the frequency region of DNA reactions. For quantifying miRNAs, digital back-end processing circuits were considered toward a fully portable platform that can carry out real-time monitoring of DNA amplification reactions. Two systems to evaluate threshold cycles were developed, based on the Derivative method and a new proposed 3-point exponential evaluation aim to reduce detection time simultaneously. Both implementations were tested with datasets from fluorescent qPCR reactions, as well as pH-LAMP experiments that have been optimized for on-chip amplifications. All designs were fabricated in unmodified CMOS with performance assessed based on functionality as well as pH-resolution required in practice. [ABSTRACT FROM AUTHOR]

Abstract A new design for electronically tunable current mode (CM) instrumentation amplifier (IA) is presented in this paper. It employs Modified Z copy Current Differencing Transconductance Amplifier (MZC-CDTA) along with a resistor. The gain of the proposed CM IA is controlled by a single resistor and can theoretically approach infinite value. Electronic tuning feature is augmented by using a MOS based resistor. The functionality is verified through simulations on Cadence Virtuoso using TowerJazz’s 180 nm Technology Node and performance against PVT variations is also examined. Feasibility of on-chip implementation is confirmed by the post-layout simulations carried out. [ABSTRACT FROM AUTHOR]

In this paper, a new pseudo-exponential function is described and a new CMOS exponential-control variable gain amplifier (VGA) based on the new function is introduced. No multiplier is needed in the proposed approach. The VGA operates in current mode and includes two different stages. The first stage is a simple current amplifier while the second stage is an attenuator. The overall behavior of the stages gives the new pseudo-exponential function. The VGA circuit has been designed and simulated for a 0.18 μ CMOS process. Post layout results show that the circuit has a bandwidth of 164 MHz and a gain range of 32.5 dB between − 21 and + 11.5 dB. [ABSTRACT FROM AUTHOR]

A novel current mode MOSFET-C filter is presented for a wide range of low frequency applications ranging from biomedical signal sensing up to speech processing region. Presented filter consumes only 2.3 µW with symmetrical supply voltages as low as ± 0.5 V. The filter structure can be easily adjusted by means of changing external capacitor values. Furthermore, proposed filter is given with a novel design methodology based on polynomial regressive small signal models. In this way, promising interaction between design parameters such as VGS, VDS, channel width (W), channel length (L) and filter specifications such as f0, Q and power is provided. Simulation results with 0.18 µm TSMC CMOS technology are given, furthermore proposed filter is tested to process a real fetal PCG signal at 355.4 Hz. It is shown that proposed filter attains a promising performance in comparison with the previously presented counterparts for low frequency applications. [ABSTRACT FROM AUTHOR]

An $E$ -band direct-conversion subharmonic receiver (SHRX) is designed exploring a coupled-rotary-traveling-wave-oscillator-based (coupled-RTWO-based) architecture. Distributed oscillators are leveraged to generate $N=8$ differential phases at $f_{\mathrm{ LO}}=f_{\mathrm{ RF}}/4$. Current-mode passive mixers (MXs) are adopted to enable <1-V supply operation and greatly simplify the layout. An inductively degenerated neutralized common source (DCS) low-noise amplifier (LNA) is embedded in a fourth-order transformer-based matching network to allow broadband impedance scaling and high reverse isolation. Implemented in a 28-nm bulk CMOS technology without ultra-thick top metal option, the realized prototype outperforms prior reported CMOS designs in terms of phase noise, figure of merit (FOM), and tuning range. The SHRX front end achieves 8.3-dB noise figure (NF), 12.5 GHz −3-dB RF bandwidth (BW), and −25-dBm ICP1 dB, while consuming <100 mW. [ABSTRACT FROM AUTHOR]

This paper is an overview of developments and results regarding neutron noise measurements in current mode at the CROCUS zero power facility. Neutron noise measurements offer a noninvasive method to determine kinetic reactor parameters such as the prompt decay constant at criticality $\alpha = \beta _{\mathrm {eff}}/\Lambda $ , the effective delayed neutron fraction $\beta _{\mathrm {eff}}$ , and the mean generation time $\Lambda $ for nuclear databases and code validation efforts. A newly developed current mode detection system using two fission chambers in the core reflector was used to accurately measure the kinetic parameters of CROCUS. Characteristics of the system and the performed noise measurements are presented. We implemented noise postprocessing of the current signals acquired at 900 mW using the autopower spectral density/cross-power spectral density (CPSD) method. The final CPSD estimated values were found to be $\alpha =(153.3 \pm 8.6)\,\,\text{s}^{-1}$ , $\beta _{\mathrm {eff}}=(778 \,\pm \,14)$ pcm, and $\Lambda =(50.7\,\pm \,2.9)\,\,\mu \text{s}$. In order to comply with experimental uncertainty targets (<3%), the measurement time was 6 h. In comparison with code predictions using MCNP5-v1.6 employing the JEFF 3.1 and ENDF/B-7.1 cross-sectional libraries, we found differences up to 3%, confirming the need for accurate kinetic parameter measurements. In the future, the new measurement system will also be used for studies of spatial and external reactor noise. [ABSTRACT FROM AUTHOR]

Abstract In this paper, a novel current mode enhanced input range four-quadrant analog multiplier is presented. The proposed class AB based translinear current squarer allows the designer to control the input range via a digital code. Moreover, the proposed scheme improves the linearity of the circuit and has a high robustness against process variations. The Post-layout and Monte Carlo simulations of the multiplier in a 0.18 μm standard CMOS technology show an input range of (1+m) × 10 μA (where 'm' is an adjustable parameter), a THD of 1% (@1 MHz), a −3 dB bandwidth of 332.3 MHz (for m = 3) and a power consumption of 186 μW. Highlights • A wide and programmable operating range current mode multiplier is proposed. • The structure is based on modified ‏class AB current buffer and translinearity principal. • The designer can control the input range via a digital code according to the requirements of different applications. • The proposed scheme improves the linearity and robustness of the circuit against process variation. [ABSTRACT FROM AUTHOR]

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In this study, both current and transimpedance mode instrumentation amplification operations are met through a new active building block proposal, namely Current DifferencingTransresistance Amplifier block, CDTRA. In order to regard CDTRA as an instrumentation amplifier (IA), two grounded passive resistors are needed. Passive resistors together with electronically tunable transresistance parameter of active block, r m , set versatility over gain tunability for instrumentation amplifier. Proposed active block is current input, current/voltage output design. It has low impedance input, high impedance for current output, and low impedance for voltage output respectively. Since this particular IA is based on CDTRA, then it inherits these electrical characteristics fully. Numerous SPICE simulations are performed through the paper to verify validity of the study. TSMC 0.18 µm CMOS technology parameters are utilized through simulations. Experimental work is performed for the proposed IA circuit. [ABSTRACT FROM AUTHOR]

This paper presents a new resistorless and electronic tunable third-order quadrature oscillator based on voltage difference transconductance amplifiers (VDTAs). The proposed configuration using two VDTAs and three grounded capacitors has three current outputs and two voltage outputs. The resistorless circuit enjoys electronically and independently control of oscillation condition and oscillation frequency. It can simultaneously provide two quadrature output voltages, two quadrature output currents, and one amplitude-controllable output current. All the current output terminals possess high-output impedance terminals. The active and passive sensitivities of the quadrature oscillator are low. The simulation and experimental results are included to validate the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents an implementation of Ultra low Voltage Second Generation Current Conveyor (ULV-CCII). The methodology adopted for the design is the use of level shifting stage to lower the effective threshold voltage of the PMOS differential pair transistors. The combination of conventional and level shifted P-MOS differential pairs together with low voltage folded cascode output sage was used to achieve almost rail to rail operation at an ultralow supply of ±0.4V. This approach also benefits from increased common mode range. The CCII provides voltage transfer bandwidth of 7.8MHz and the current transfer bandwidth of 17MHz,while dissipating a nominal power of 123 μW. A versatile dual mode universal filter is realized to validate the functionality of the ULV-CCII. The filter is capable of working in both current and voltage modes without a change in its topology. The filter employs only two CCIIs, two capacitors, and two resistors.The use of only positive single input CCII simplifies the implementation and relaxes the matching constraints during layout, leading to enhanced filter performance. The filter works at ±0.4V supply and provides all standard filter responses in the voltage mode as well as low pass and band pass response for the current mode of operation.TheH-spice simulation results in 0.18μm TSMC CMOS technology are presented to prove the results. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS ultra-low-power, high-speed four-quadrant current multiplier/divider circuit is presented. Based on square-difference approach, the proposed circuit is using a new current squarer with MOS transistors operating in weak inversion region. The translinear loops are the basic building blocks in realization of the current-mode two-quadrant squarer and four-quadrant multiplier/divider circuits. The proposed designs have been simulated using HSPICE in 0.18 μm TSMC CMOS (level-49 parameter) process. Post-layout simulation results with 0.8 V power supply show the total power dissipation of 770 nW, the total harmonic distortion of 0.67% (at 100 kHz), the maximum linearity error of 2%, and the − 3 dB bandwidth of 34.1 MHz. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage, and temperature) variations. [ABSTRACT FROM AUTHOR]

In this paper, we present voltage-mode and current-mode differential magnetless nonreciprocal devices obtained by pairing two single-ended (SE) circulators, each consisting of three first-order bandpass or bandstop LC filters, connected in either a wye or a delta topology. The resonant poles of each SE circulator are modulated in time with 120° phase-shifted periodic signals, resulting in synthetic angular-momentum biasing achieved through spatiotemporal modulation (STM). We tailor the two SE circulators to exhibit a constant 180° phase difference between their STM biases. Unlike conventional differential time-variant circuits, for which only the even or odd spurs are rejected, we show that the proposed configuration cancels out all intermodulation products, thus making them operate alike linear time-invariant (LTI) circuits for an external observer. In turn, this property enhances all metrics of the resulting circulator, overcoming the limitations of SE architectures, and improving insertion loss, impedance matching, bandwidth, and noise figure. We show that this differential architecture also significantly relaxes the required modulation parameters, both in frequency and amplitude. We develop a rigorous small-signal model to guide the design of the proposed circuits and to get insights into their pseudo-LTI characteristics. Then, we validate the theory with simulations and measurements showing remarkable performance compared to the current state-of-the-art of magnetless nonreciprocal devices. [ABSTRACT FROM AUTHOR]

In this paper, analysis and design of a new current-mode instrumentation amplifier (CMIA) circuit is presented. The proposed circuit employs two Current Operational Amplifiers (COA) as active building blocks, one resistor and two transistors operating as variable resistors to electronically control the differential-mode gain. The main feature of the proposed CMIA is that unlike most previously reported CMIAs, its CMRR has negligible sensitivity to mismatches. In addition, in the proposed circuit both active building blocks operate in negative feedback loop which results in an overall enhanced performance. SPICE simulation results using 0.18 μm TSMC CMOS parameters and supply voltage of ±0.9 V show a constant CMRR of about 51 dB regardless of mismatches and wide bandwidth ranging from 14.8 MHz to about 3 MHz for differential-mode gains between 3 and 18 dB, respectively. [ABSTRACT FROM AUTHOR]

To achieve the maximum current rising rate, the second-generation fast control power supply (FCPS) applies voltage control mode while retaining the first-generation current tracking mode. When the power supply outputs high voltage, the accompanied frequent overcurrent protection will return the power to dc side, which leads to overvoltage protection, so the current limiting protection is applied. Experimental results prove that voltage mode can greatly improve the ability to suppress vertical unstable displacement of plasma. [ABSTRACT FROM AUTHOR]

In this paper, a membership function generator (MFG) is presented which can produce triangular, trapezoidal, S-shaped or Z-shaped membership functions. The presented structure can operate in both trans-conductance (voltage–current) and current mode (current–current) with high programmability. The slope (keeping the height or width of the membership function constant), height (keeping the width constant) and width (keeping the height constant) of the membership function are independently programmable. Moreover, the width of the trapezoid can be varied without changing slope or height and all the generated shapes can be positioned horizontally. The topology, primarily, is presented in transconductance mode which can be converted to current mode with a little change in the input section of the circuit. Simulation results for the proposed circuit are presented in two operation modes. The most remarkable feature of the proposed MFG is its capability of generating outputs while consumes a very low amount of power. The analytical analysis of the proposed circuits is also given in HSPICE using TSMC 0.18 μm CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, three novel low-power and high-speed 1-bit inexact Full Adder cell designs are presented based on current mode logic in 32 nm carbon nanotube field effect transistor technology for the first time. The circuit-level figures of merits, i.e. power, delay and power-delay product as well as application-level metric such as error distance, are considered to assess the efficiency of the proposed cells over their counterparts. The effect of voltage scaling and temperature variation on the proposed cells is studied using HSPICE tool. Moreover, using MATLAB tool, the peak signal to noise ratio of the proposed cells is evaluated in an image-processing application referred to as motion detector. Simulation results confirm the efficiency of the proposed cells. [ABSTRACT FROM AUTHOR]

In this work, a novel design automation method is presented for easy construction of MOSFET-Only or MOSFET-C filters. In contrast to previous works in the literature, the proposed algorithm is simple since it uses polynomial fitting models obtained from SPICE data in order to reformulate small signal parameters and some DC characteristics of MOSFET’s. Polynomial regressive models facilitate to interact between design constraints (power, area, speed, pole frequency etc.) and design variables (operating voltages, currents and device dimensions). In this regard, two novel agile MOSFET-Only filters produced with the proposed automation process are presented in order to qualify the automation flow. The produced filters are simulated in LT-SPICE and CADENCE-SPECTRE environment by using 0.18 µm TSMC technology. These agile filters can easily be used in a wide range of applications such as encrypted communications or very high frequency circuits. In addition, it is shown that there is a good agreement between proposed design automation flow and simulations. [ABSTRACT FROM AUTHOR]

This paper presents novel solution of a fractional-order low-pass filter (FLPF). The proposed filter operates in the current mode and it is designed using third-order inverse follow-the-leader feedback topology and operational transconductance amplifiers (OTAs), adjustable current amplifiers (ACAs), auxiliary multiple-output current follower (MO-CF) as simple active elements. The filter offers the beneficial ability of the electronic control of its order and also the pole frequency thanks to electronically controlled internal parameters of OTAs and ACAs. As an example, five particular values of fractional order of the FLPF were chosen and parameters of the filter were calculated. Similarly, also electronic control of the pole frequency of the filter was studied. The design correctness and proper function of the filter are supported by simulations with CMOS models and also by experimental laboratory measurements. Comparison of the simulation results of the proposed filter for two different approximations of the parameter aplha is also included. [ABSTRACT FROM AUTHOR]

In this work, novel first order MOS-C phase shifter structures are proposed in NMOS and PMOS configurations. Core circuits consist of only three transistors and a single capacitor. The pole frequency of the phase shifters can be easily controlled by the bias voltage. The presented circuits in this work bring advantages such as low power consumption and small chip area when compared to other works including large numbers of active and passive elements in the literature. Furthermore, the proposed circuits are designed with a simple design automation flow that is proper for MOS-Only or MOS-C architectures. It is shown by simulations that the simulation results agree with the theoretical results for a wide frequency range. [ABSTRACT FROM AUTHOR]

In this paper an analog voltage divider employing a single operational transresistance amplifier as active element is proposed. Its extension as square-rooter and inverse function has also been discussed. The circuit is found to function as a two quadrant divider. The realization of the circuit as a resistorless configuration is also given which eases monolithic integration and consumes less space. The performance of the proposed circuit is verified through PSPICE (Cadence EDA Tools) simulations using 0.25 µm CMOS technology parameters provided by MOSIS (AGILENT). The various simulation results confirm the feasibility of the proposed circuits. [ABSTRACT FROM AUTHOR]

In this paper a new active element namely Dual X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing eight topologies of lossy and lossless grounded inductor simulators and two topologies of floating inductor simulators. All the designed grounded simulators require only two passive elements and a single active block. The two floating inductor simulators require a single active block and one or three grounded passive elements. In addition, all the designs make use of only grounded capacitors for implementation which is advantageous for fabrication. All the proposed active inductors, except two, did not require any component matching conditions for realization and all the inductor simulators are perfectly tunable. The effect of non-idealities on the proposed grounded simulator structures is also studied. To demonstrate the workability of the inductor simulators they are used in design of second order low pass filter, parallel RLC resonance circuit, third order Butterworth high pass filter, parallel RLC current mode multifunction filter and a voltage mode band pass filter. The DXCCDITA is implemented in 0.35 μm TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient number of simulations are provided to establish the functionality of the active inductor structures. [ABSTRACT FROM AUTHOR]

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths. Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption. The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results. [ABSTRACT FROM AUTHOR]