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This work is part of our effort to find an alternative to IDDQ testing. Specifically, this paper presents our variance reduction post-processing approach in order to replace IDDQ. It describes our test procedure based on Delta IDDQ histograms. It shows how this test procedure can help to reduce variance, optimize test resources and reduce the impact of process drifting and resolution loss caused by the expected IDDQ growth. Another practical aspect is discussed, namely the use of the proposed test procedure in a production test. We propose a new distribution model and revisit some experimental data, which provides a better understanding of the relationship between defect and fault. The results obtained so far confirm the pertinence of our test approach and the necessity of keeping current testing alive.

Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses IDDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of IDDQ contour plots. A “family” of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.

The purpose of this paper is to introduce a new IDDQ measurement technique based on active successive approximations, called ASA-IDDQ. This technique has unique features facilitating a speed-up in IDDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold IDDQ testing since it amplifies the effectiveness of post-processing techniques.

The effectiveness of single threshold IDDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta IDDQ is identified as one alternative for deep submicron current measurements. Often delta IDDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the IDDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate IDDQ limits for normal and stressed operating conditions of 0.18 μm n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed ΔIDDQ testing is also investigated.

In this paper, functional IDDQ testing has been applied for a 90nm VLIW processor to effectively detect aging degradation. This technique can provide health data for reliability evaluation as used in e.g. prognostic software for lifetime prediction. The test environment for validation, implementing an accelerated test (AT), has been investigated and IDDQ measurement data resulting from AT is presented. It is found that the quiescent current for the processor characterizes power degradation with a coefficient of -0.025 with the aging trend. This is in coherence with behaviour of the NBTI aging mechanism, but contradicting other mechanisms such as TDDB. It shows the NBTI aging is the dominant factor for processor technology of 90nm and beyond.

In this paper, functional IDDQ testing has been applied for a 90nm VLIW processor to effectively detect aging degradation. This technique can provide health data for reliability evaluation as used in e.g. prognostic software for lifetime prediction. The test environment for validation, implementing an accelerated test (AT), has been investigated and IDDQ measurement data resulting from AT is presented. It is found that the quiescent current for the processor characterizes power degradation with a coefficient of -0.025 with the aging trend. This is in coherence with behaviour of the NBTI aging mechanism, but contradicting other mechanisms such as TDDB. It shows the NBTI aging is the dominant factor for processor technology of 90nm and beyond.

This paper introduces a methodology for assessing the fault security attributes of Fault Secure (FS) circuits. Structural VHDL circuit descriptions are used to simulate the fault effects of reafistic transistor level defects that occur in CMOS ICs. Defective standard cells are simulated at the analog level of abstraction and the resultant fault effects are implemented in defect-injectable VHDL models to allow logic simulation. Typical fault effects include functional changes, propagation delay increases, sequential logic faults, stuck-at faults, reduced noise margins, and increased IDDQ. The defect-injectable VHDL models are swapped into FS circuit designs and the effects of the defects are analyzed in the context of the digital circuit. The FS circuits can then be assigned a figure of merit based on the ratio of detected defects to those that actually cause output errors. To facilitate the execution of the methodology, an integrated software tool has been developed that, in combination with a commercial VHDL simulation tool, provides an automated means for determining the figure of merit. Implemented using a GUI, the new tool is user friendly and flexible enough to be used with various logic circuits and different IC technologies. Three different checker, as benchmarks, were evaluated to demonstrate the FSA tool and the methodology to assess their relative fault security.

The increase in the off-state current for sub-quarter micron CMOS technologies is making conventional IDDQ testing ineffective. Since natural process variation together with low-VTH devices can significantly increase the absolute leakage value and the variation, choosing a single threshold for IDDQ testing is impractical. One of the potential solutions is the cooling of the chip during current testing. In this paper we analyze the impact of CMOS technology scaling on the thermal behavior of different leakage current mechanisms in n-MOSFETs and estimate the effectiveness of low temperature IDDQ testing. We found that the conventional single threshold low temperature IDDQ testing is not effective for sub-quarter micron CMOS technologies and propose the low temperature DIDDQ test method. The difference between pass and fail current limits was estimated more than 200 £ for 0.13-mm CMOS technology. q 2002 Published by Elsevier Science Ltd.

Deep-submicron technologies pose difficult challenges for I/sub DDQ/ testing in the future. The low threshold voltage used by DSM devices decreases the defect resolution of I/sub DDQ./ However, because I/sub DDQ/ is a valuable test method, researchers are working to augment with other test parameters to prolong its effectiveness.

I DDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, we propose a technique for the elimination, during testing, of the normal leakage current from the sensing node of a circuit under test. In this way the already known in the open literature I DDQ sensing techniques can be applied in the nanometer technologies.

This paper treats the test of CMOS digital ICs by using the thermal mapping of the silicon surface as a test observable. Two different temperature-sensing strategies are presented. The novel sensors developed are an on-chip CMOS Differential Temperature (DT) sensor and a Proportional to Absolute Temperature (PTAT) sensor. The sensors have been implemented in a standard .18 μm CMOS technology.

In this paper we analyze fault behaviors of internal feedback bridging faults. To investigate their behaviors, we use a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results, we find that behaviors of internal feedback bridging faults are more complex than those of external feedback bridging faults. We expose that they cause IDDQ-only failure, internal latch and internal oscillation as well as latch and oscillation behavior. These phenomena are caused by the following facts: formation of an electrically conducting feedback loop and connection of the feedback loop with the circuit output depend on input values of the circuit, and the feedback loop is often alive only within the circuit. We also discuss methods for detecting this kind of fault.

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 107 gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.

Increase in MOSFET leakage currents with scaling has led to different scaling scenarios for power-performance optimization. MOSFET leakage currents and defects contribute to current drawn in the quiescent state of a CMOS chip. Measurement of this current, IDDQ, is useful in eliminating chips with gross defects early in the test flow. DC and AC components of total power in the active mode are functions of power supply voltage, switching activity and temperature. Circuit design strategies and dynamic on-chip power management schemes help alleviate potential reliability issues and rising energy cost of high performance CMOS chips.

Modern Integrated Circuits (ICs) are becoming increasingly vulnerable to malicious inclusions and alterations (hardware Trojans) due to the globalization of semiconductor design and fabrication processes, which brings in the requirement for reliable detection of hardware Trojans made in an untrusted fabrication facility during post-manufacturing test. In this paper, we present a new method for Trojan detection that calculates temporal features of IDDT and IDDQ signals, then applies mRMR (minimum-redundancy maximum-relevance) algorithm to select feature subset, and finally uses Mahalanobis distance calculation to detect Trojan circuits. Experimental results featuring an information-leak hardware Trojan inserted into a 128-bit AES cryptographic circuits on Xilinx Spartan-3E FPGAs demonstrate the simplicity and effectiveness of the proposed approach for Trojan detection.

Opens in interconnection paths disconnect the driven gate(s) from the driving gate. Detectability conditions to test full opens in interconnections are investigated. It has been found that the detectability of this defect depends strongly on the signals at the driving gate and coupling lines. Three possible situations are analyzed. The first is when there is full controllability of both the signal driving the open and the signal(s) at the coupling line(s). Then, the cases of partial and low controllability of the signals are analyzed. Conditions for reliable detection of this defect by logic and IDDQ testing have been determined. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. Routing design for testability techniques are recommended for some interconnection opens non detectable by either a stuck-at based or IDDQ testing. Experimental data on intentionally designed defective circuit is presented.

This paper presents a real case study on the testing of 8-bit mixed-signal CMOS micro-controller devices by applying the I DDQ testing methodology. The aim of the study is to evaluate the feasibility of using the I DDQ test to enhance the overall fault coverage. Failure analysis operated on the failed sample indicated a good correlation between the fault coverage and the parts that failed the I DDQ test.

Systematic investigations on defect-free IDDQ in deep submicron CMOS with reverse body bias were performed by SPICE simulation towards an attempt to improve resolution of IDDQ measurement. Effects of reverse body bias on off-state leakage of scaled CMOS devices and IDDQ of typical CMOS circuit cells were investigated. It was found that reverse body bias can effectively reduce defect-free IDDQ of typical 0.18 μm technology devices and logic gates while the faulty current is not as much reduced. The reduction in defect-free IDDQ was enhanced as the device temperature went up and diminishes as the temperature went down. Further investigation showed that reverse body bias also makes the defect-free IDDQ less sensitive to the input state; therefore, a single IDDQ current threshold might still be used for IDDQ testing of 0.18 μm CMOS circuits. It was found that there might exist an optimal reverse body bias that minimized the defect-free IDDQ current. The optimal reverse bias value decreases as the temperature went down and might vary from circuit to circuit, process to process, and technology generation to generation.

Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to enhance the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults, and to define the diagnosis area encircling the abnormal portions. The proposed technique progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal IDDQ. The fundamental diagnosis way employs the comparative operation of each circuit element to determine whether the same logic state with abnormal IDDQ exists in normal logic state or not.

This paper presents a test technique that employs two different supply voltages for the same IDDQ pattern. The results of the two measurements are subtracted in order to eliminate the inherent sub-threshold leakage. Summary of the experiment carried out on “System on a Chip” (SOC) device build in 0.35 μ technology is also shown. These experiments proved that the method is effective in detecting failures not detectable with the single limit IDDQ.

The high leakage current in deep submicron, short-channel transistors can increase the stand-by power dissipation of future IC products and threaten well established quiescent current (I/sub DDQ/)-based testing techniques. This paper reviews transistor intrinsic leakage mechanisms. Then, these well-known device properties are applied to a test application that combines I/sub DDQ/ and ICs maximum operating frequency (F/sub max/) to establish a novel two-parameter test technique for distinguishing intrinsic and extrinsic (defect) leakages in ICs with high background leakage. Results show that I/sub DDQ/ along with F/sub max/ can be effectively used to screen defects in high performance, low V/sub T/ (transistor threshold voltage) CMOS ICs.

In order to reduce IDDQ testing time, it is important to reduce the number of IDDQ measurement vectors, because IDDQ measurement is a time-consuming process. For obtaining minimum number of IDDQ measurement vectors for sequential circuits, fault simulation needs to be performed without fault-dropping, thus requiring very high simulation time. In this paper we propose algorithms to select small number of IDDQ measurement vectors. The proposed algorithms can concurrently simulate multiple faults and use heuristics for selection of IDDQ measurement vectors to reduce simulation time. Experimental results are presented to demonstrate the effectiveness of the proposed method.

Built-in current sensor (BICS) is known to enhance test accuracy, defect coverage of quiescent current (I_{DDQ}) testing method in CMOS VLSI circuits. For new deep-submicron technologies, BICSs become essential for accurate and practical I_{DDQ} testing. This paper presents a new BICS suitable for power dissipation measurement and I_{DDQ} testing. Although the BICS presented in this paper is dedicated to submicron technologies that require reduced supply voltage, it can also be used for applications and technologies requiring normal supply voltage. The proposed BICS has been extended for on-line measurement of the power dissipation using only an additional capacitor. Power dissipation measurement is important for safety-critical applications and battery-powered systems. A simple self-test approach to verify the functionality and accuracy of BICSs has also been introduced. The proposed BICS has been implemented and tested using an N-well CMOS 1.2 μm technology. Practical results demonstrate that a very good measurement accuracy can be achieved.

This paper analyzes the detectability of resistive bridging faults in CMOS (micro)-pipelined circuits. Logic and electrical level detection conditions are provided for functional and Iddq testing techniques. The kind of operations and the sensitivity to dynamic fault effects of pipelined circuits make such conditions more complex than in the combinational case. In particular, it is shown that the kind of used latches has a relevant impact on fault coverage, and should be carefully accounted in test generation and fault simulation. Finally, guidelines are drawn for the extension of combinational test generation and fault simulation algorithms to the considered case.

IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we propose an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.

The usability of IDDQ testing is limited by the subthreshold currents of the low-VT, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold voltage and subthreshold current are presented in the range of −75 … 25 Centigrade. The subthreshold currents decrease by a factor of about 100–1000 by cooling-down the chip to −75 Centigrade.

The current trends in decreasing the minimum feature sizes in CMOS technologies are producing new failure mechanisms for which the classical test methods become inefficient. This situation causes a growing concern in the design and test communities due to the fact that the advances in integration advance faster than the ability of test specialists in providing the required strategies to test the new circuits. If the current levels of reliability are to be maintained new paradigms to guarantee the quality levels of the future megatransitor chips will be required. In this paper, after reviewing the technology trends in CMOS technologies, the emerging failure mechanisms of these technologies are analyzed. The challenges facing testing in nanometric technologies are explored in terms of voltage test difficulties as well as current test (IDDQ) problems and solutions.

I DDQ testing detects a majority of faults occurring in logic,ICs. Nethertheless, it has not eliminated the complex task of fault isolation at the silicon level of ICs. Liquid Crystak or Emission Microscopy can deal with this challenge. Unfortunately these two techniques lack sensitivity for some defects when the abnormal current consumption (I DDQ ) remains weak. On the other hand we can use very powerful tools like the electron beam tester to deeply analyze faulty devices by internal contactless testing. In some laboratories, people have underlined the interest of merging the two techniques (I DDQ testing and Voltage Contrast) to get fast and accurate defect localization. In this paper, we will move on to the next step of identifying practical key issues necessary for obtaining results on current VLSI.

This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employingIDDQtesting can be achieved with only logic monitoring required.

Certain logic functions such as the control units of VLSI processors are difficult to be implemented by random logic. Since the programmable logic arrays (PLAs) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. Besides, due to high quality demand in the semiconductor market, the testing of PLAs becomes an important issue. Because the structure of the PLAs is basically arrays of transistors or gates, the traditional test generation algorithms for stuck-at faults are hard to be employed. Thus, many test-generation approaches and designs for PLA testability have been developed. The IDDQ test is one of the effective techniques of detecting both bridge faults and open faults in CMOS integrated circuits. We present a testability configuration of PLAs which will be transformed into inverters in the test mode so that the IDDQ testing with only two test vectors and low overhead circuitry for the detection of all the bridge ...

This paper presents a novel built-in current sensor that uses two additional power supply voltages besides the system power supply voltage, and that is constructed by using a current mirror circuit to pick up an abnormal IDDQ. It is activated only by an abnormal quiescent power supply current and minimizes the voltage drop at the terminal of the circuit under test. Simulation results showed that it could detect 16-μA IDDQ against 0.03-V voltage drop at 3.3-V VDD and that it reduced performance degradation in the circuit under test. It is therefore suitable for testing low-voltage integrated circuits. Moreover, we verified the behavior of the sensor circuit implemented on the board by using discrete devices. Experimental results showed that the real circuit of the sensor functioned properly.

The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. A technique to test open defects producing data retention faults is proposed. An initial condition is forced during the writing phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (I_DDQ) increases and the fault can be detected sensing the I_DDQ. The testability regions for the defective memory cell were determined using state diagrams. Conditions to obtain the optimum vector have been stated. A DFT circuitry has been proposed. The cost of the proposed approach in terms of area, test time, and performance degradation is analyzed.

This paper describes a highly accurate and efficient fault simulator for interconnect opens in combinational or full-scan digital CMOS circuits. The analog behavior of the wires with interconnect opens is modeled very efficiently in the vicinity of the defect in order to predict what logic levels the fanout gates will interpret and whether a sufficient IDDQ current will be flowing inside the fanout gates. The fault simulation method is based on characterizing the standard cell library with SPICE, using transistor charge equations for the site of the open, using logic simulation for the rest of the circuit, taking four different factors that can affect the voltage of an open into account, and considering the potential oscillation and sequential behavior of interconnect opens. The tool can simulate test vectors for both voltage and current measurements. Simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets are presented.

A method to detect open node defects that cannot be detected by the conventional IDDQ test method has previously been proposed employing a sinusoidal wave superposed on the DC supply voltage. The present paper proposes a strategy to improve the detectability of the test method by means of frequency analysis of the supply current. In this strategy, defects are detected by determining whether secondary harmonics of the sinusoidal wave exist in the supply current. The effectiveness of the method is confirmed by experiments on two CMOS NAND gate packages (SSIs).

Quality assurance in electronic components and systems requires effective test strategies to be applied to ICs of increasing complexity and size. The traditional voltage techniques based on logic observation of the outputs have been found insufficient to guaranty the low defect escape requirements of growing sectors of IC users. This fact has motivated the search for complementary testing techniques which try to detect defects escaping logic testing. This paper attempts to explore the state of the art and the perspective of the test based on the observation of the quiescent current consumption of the IC, generally known as I DDQ testing. After introducing the basic principle of the technique and the components of the quiescent current in CMOS technologies, the physical defects which cause an increase of the I DDQ are presented. The state of the art of the detection of circuits with sensor(s) located on-chip (BICS) and off-chip is explored. A literature review of the circuits to sense the quiescent current permits their classification according to their function and structure. The different techniques to generate the input vectors to force the increase in quiescent current consumption are presented and, as an example, an ATPG to detect bridging faults is presented in detail. Finally the future trends of I DDQ testing are discussed taking into account the implications of scaling in CMOS. As the power supply voltage is reduced to maintain the electric fields in the MOS transistors and the global power consumption, the threshold voltages of the devices need to be lowered to maintain or increase the speed of the logic. As a consequence, the quiescent current consumption, I DDQ , increases exponentially. This fact decreases the discriminability of nondefective in front of defective quiescent currents. On the other hand, techniques to reduce the leakage currents are becoming available thanks to an active research effort directed mainly to decrease the quiescent power consumption in submicron ICs.

In this work, a fast identification of I ddq failures using spectroscopic photon emission microscopy (SPEMMI) is proposed. The spectra obtained from failure sites on the I ddq failed chips were compared with the ones of known defective components. Four distinguishable spectra categories were identified. They were attributed to gate oxide breakdown, metal shorts, blackbody radiation, and ESD caused junction spiking. The focused ion beam (FIB) technique was used to look at the damage sites for confirmation of the SPEMMI results.

As a result of performing the Iddq (IC's power supply current) failure analysis on CMOS logic LSI using the backside OBIC (optical beam induced current) method, we succeeded in detecting a short circuit at an overlapped portion between a power supply line and a signal line. So far a circuit failure beneath the Al wiring has been difficult to find because the surface of LSI chip is covered by the wiring. However, we succeeded in detecting the carriers abnormally generated at a failure portion of a circuit on the chip surface by the optical energy when the backside of wafer was irradiated by an He-Ne laser. The backside OBIC technique is an effective method of failure analysis for advanced multilayer LSIs.

IDDQ testing has progressed to become a worldwide accepted test method to detect CMOS IC defects. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage, which is referred to IDDT testing. This letter presents a formal procedure to identify IDDT testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by IDDQ or other test methods, which shows the significance of IDDT testing.

本論文では, プリント配線板上にSSIを用いて実現したTTL回路における断線故障を, その回路に流れる静的電源電流を測定することで検出する方法を提案している。また, そのための検査入力生成手法を提案し, ISCAS-85ベンチマーク回路をTTL-LS型SSIを用いて実現した回路に対し, その検査人力を生成している。それにより, 従来の外部出力論理値測定による検査法に比べ本論文で提案している検査法は, より少ない検査入力で, より高い故障検出率で断線故障を検出できる能力を持つことを明らかにしている。

This paper presents a new built-in current sensor (BICS) that detects defects using the current testing technique in CMOS integrated circuits. The proposed circuit is a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applicable in deep submicron process. The area overhead of the BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm standard CMOS technology.

Transistor level models and testing methodologies are developed for detecting the bridging faults in CMOS and BiCMOS circuits. The quiescent power supply current (IDDQ) is utilized as the basis of modelling and test generation. Multiple and single bridging faults are covered. Modelling and testing techniques are presented. The first technique employs a new model called the Current Transfer Function (CTF) that is used to detect the bridging faults in CMOS and BiCMOS circuits. The CTF is a Boolean representation of the IDDQ flow path in terms of input variables and transistor topology of a circuit. The other technique employs an extension of the logic transistor function (LTF) model that was developed earlier for detection of transistor stuck faults. This technique is used for modelling and generating the test for single bridging faults in CMOS circuits, as it is simpler and efficient. However, because of certain limitations this technique is not extended for bridging faults in BiCMOS circuits and the multi...

A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) and parametric behavior of the BiCMOS circuits in the presence of transistor stuck faults. The model employs the logic transistor function (LTF). The LTF describes the circuit in terms of its input variables and transistor topology. The model assumes four logic values: 0, 1, M and I, where M and I imply a memory and an indeterminate element, respectively. The faults in BiCMOS circuits may affect the logic level at the output or the parameters of the circuit. The circuits are normally tested at the parametric level by IDDQ (steady state power supply current) testing or by timing testing. The LTF model is utilized to generate the test vectors for both the functional testing and the parametric testing. Simulation is performed using hspice to support the results.

We present two algorithms, called list-based scheme and tree-based scheme, to compute bridging fault (BF) coverage ofIDDQtests. These algorithms use the novel ideal of “indistinguishable pairs,” which makes it more efficient and versatile than known fault simulation algorithms. Unlike known algorithms, the two algorithms can be used for combinational as well as sequential circuits and for arbitrary sets of BFs. Experiments show that the tree-based scheme is, in general, better than the list-based scheme. But the list-based scheme is better for some classes of faults.

I DDQ testing is indispensable in improving the quality of CMOS circuits. Currently, I DDQ testing is usually conducted by using I DDQ test vectors selected from a test set generated for logic testing. Since I DDQ measurement is relatively slow, it is necessary to select a set of I DDQ test vectors which is as small as possible and which can detect as many faults as possible. In this paper, we consider the problem of I DDQ test vector selection based on the transistor short fault model. First, we define fault equivalence for the transistor short-fault model and propose methods for reducing the number of faults that need to be considered by equivalence fault collapsing. Then, we formalize the I DDQ test vector selection problem and propose a new selection method based on fault tables. Furthermore, we show the effectiveness of the proposed method by experimental results.

An increasing demand for the portable applications has elevated power consumption to be the most critical parameter. A transistor level model and a testing methodology are presented for detected bridging and stuck short faults in CMOS combinatorial circuits, with the power consumption as a major constraint during testing. The circuits are modeled by the CTF (Current Transfer Function) model. The quiescent current (IDDQ) measurement technique is utilized as the testing methodology. Transistor stuck open faults, that can change the test vector for IDDQ, are incorporated in the model. Simulation using hspice is carried out to support the results.

Undetectable stuck-at faults in combinational circuits are related to the existence of logic redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable by IDDQ testing. An efficient method for the identification and removal of such functionally equivalent nodes (f-redundant nodes) in combinational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f-redundancy nodes. An f-redundancy removal algorithm based on circuit transformations to improve bridging fault testability, is also proposed. The efficiency of the identification and removal of f-redundancy has been evaluated on a set of benchmark circuits.