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A route to the titled compounds in >99% ee was achieved from sequential diastereoselective alkylations of chiral, nonracemic bicyclic lactams 6 and 15. An intramolecular addition of the organolithium species derived from 17a-c and 28a-d gave, after hydrolysis, diketones 25a-c and 30a-d, which were cyclized to the titled compounds 4a-c and 31a-d. As an example of the versatility of this method, the ABC ring system of the triterpene stelliferin A, isolated from marine organisms, was prepared in high enantiomeric excess

The trans-2,3-disubstituted pyrrolidine moiety, found in the pyrrolizidine alkaloids as well as other natural product, has been accessed from the α,β-unsaturated bicyclic lactams 1d and 10. Conjugate addition of lower order cyanocuprates to lactams 1d and 10 resulted in endo entry of the cuprate with high diasterelectivity. Other cuprates were investigated and resulted in diminished or opposite stereoselectivities. Further transformation of the β-subtituted lactams provided the title compounds in good overall yield and high enantiomeric excess

Task‐switching paradigms are ideal for studying how primates implement and apply rules. This chapter summarizes a large body of work conducted on the comparative primatology and neurophysiology of task‐switching in macaque monkeys. This chapter presents ?ndings of rule representations from single‐neuron recordings in the intraparietal sulcus in posterior parietal cortex and argues that rule representation and control is implemented by a network spanning both frontal and posterior brain regions. These ?ndings provide a useful model for studying neuronal representations of task rules and the neural processes that apply those rules.

Sequential-pulse (or dual-pulse) laser-induced breakdown spectroscopy (DP-LIBS) with an orthogonal spark orientation is described for elemental analysis of bulk aqueous solutions at pressures up to ∼138 × 105 Pa (138 bar). The use of sequential laser pulses for excitation, when compared to single-pulse LIBS excitation (SP-LIBS), provides significant emission intensity enhancements for a wide range of elements in bulk solution and allows additional elements to be measured using LIBS. Our current investigations of high-pressure solutions reveal that increasing solution pressure leads to a significant decrease in DP-LIBS emission enhancements for all elements examined, such that we see little or no emission enhancements for pressures above 100 bar. Observed pressure effects on DP-LIBS enhancements are thought to result from pressure effects on the laser-induced bubble formed by the first laser pulse. These results provide insight into the feasibility and limitations of DP-LIBS for in situ multi-elemental detection in high-pressure aqueous environments like the deep ocean.

Laser-induced breakdown spectroscopy (LIBS) is presented for detection of several Group I and II elements (e.g., Na, Ca, Li, and K), as well as Mn and CaOH, in bulk aqueous solution at pressures exceeding 2.76 × 107Pa (276 bar). Preliminary investigations reveal only minor pressure effects on the emission intensity and line width for all elements examined. These effects are found to depend on detector timing and laser pulse energy. The results of these investigations have implications for potential applications of LIBS for in situ multi-elemental detection in deep-ocean environments.

New chemical sensors are needed for both present day expeditionary oceanography and an emerging new phase involving long term in situ ocean observations. Over the past four decades, a new spectrochemical technique, laser induced breakdown spectroscopy (LIBS), has been under development for the identification of the elemental constituents of materials. This technique uses a laser to create a spark or plasma on a sample. The plasma emission is then analyzed with a spectrometer to determine its elemental composition. Recently, LIBS has been identified as a viable tool for in situ field measurements because it is able to analyze all forms of matter (solids, liquids, and gases), can operate in a stand-off mode, and is non-invasive and non-destructive. A marine LIBS sensor would be a useful tool for studying many environments in the ocean, especially mid-ocean ridge hydrothermal vents where in situ measurements are difficult due to the presence of high-temperature, corrosive fluids. A feasibility assessment of oceanic LIBS in the laboratory has been initiated. A high pressure chamber was designed and built for investigating the effect of realistic ocean environments on the LIBS signal. Preliminary work shows that LIBS can successfully detect Li, Na, K, Ca, Mn, and Zn in bulk aqueous solutions at pressures up to 272 atm, making LIBS a viable technique for deep ocean chemical sensing.

We have designed and demonstrated a standoff Raman system for detecting high explosive materials at distances up to 50 meters in ambient light conditions. In the system, light is collected using an 8-in. Schmidt–Cassegrain telescope fiber-coupled to an f/1.8 spectrograph with a gated intensified charge-coupled device (ICCD) detector. A frequency-doubled Nd: YAG (532 nm) pulsed (10 Hz) laser is used as the excitation source for measuring remote spectra of samples containing up to 8% explosive materials. The explosives RDX, TNT, and PETN as well as nitrate- and chlorate-containing materials were used to evaluate the performance of the system with samples placed at distances of 27 and 50 meters. Laser power studies were performed to determine the effects of laser heating and photodegradation on the samples. Raman signal levels were found to increase linearly with increasing laser energy up to ∼3 × 106 W/cm2 for all samples except TNT, which showed some evidence of photo- or thermal degradation at higher laser power densities. Detector gate width studies showed that Raman spectra could be acquired in high levels of ambient light using a 10 microsecond gate width.

Processor layout and data distribution are important to performance-oriented parallel computation, yet high-level language support that helps programmers address these issues is often inadequate. This paper presents a trio of abstract high-level language constructs - grids, distributions, and regions - that let programmers manipulate processor layout and data distribution. Grids abstract processor sets, regions abstract index sets, and distributions abstract mappings from index sets to processor sets; each of these is a first-class concept, supporting dynamic data reallocation and redistribution as well as dynamic manipulation of the processor set. This paper illustrates uses of these constructs in the solutions to several motivating parallel programming problems.

Experiments are presented indicating that on shared-memory machines, programs written in the nonshared-memory programming model generally offer better performance, in addition to being more portable and scalable. The authors study the LU decomposition problem and a molecular dynamics simulation on three shared-memory machines with widely differing architectures, and analyze the results from three perspectives: performance, speedup, and scaling. >

Explicitly parallel programs have the potential for greater performance than their implicitly parallel counterparts. However, this benefit can be accompanied by additional programming difficulties. We address one particular problem that has implications for both scalability and portability: the need for programs do accommodate diverse data decompositions. We explain why programs with explicit communication have difficulties in handling changes in data decomposition, and we present a solution to this problem which involves the notions of derivative functions and configuration parameters. We illustrate the technique by using three different data decompositions to solve the Modified Gram-Schmidt method on four parallel machines. >

ZPL is a parallel array language designed for high performance scientific and engineering computations. Unlike other parallel languages, ZPL is founded on a machine model (the CTA) that accurately abstracts contemporary MIMD parallel computers. This makes it possible to correlate ZPL programs with machine behavior. As a result, programmers can reason about how code will perform on a typical parallel machine and thereby make informed decisions between alternative programming solutions. The paper describes ZPL's performance model and its syntactic cues for conveying operation cost. The what you see is what you get (WYSIWYG) nature of ZPL operations is demonstrated on the IBM SP-2, Intel Paragon, SGI Power Challenge, and Cray T3E. Additionally, the model is used to evaluate two algorithms for matrix multiplication. Experiments show that the performance model correctly predicts the faster solution on all four platforms for a range of problem sizes.

Using a specially constructed machine independent communication optimizer that allows control over optimization selection, we quantify the performance benefit of three well known communication optimizations: redundant communication removal, communication combination, and communication pipelining. The numbers are shown relative to the base performance of benchmark programs using the standard communication optimization of message vectorization. The effects on the number of calls to communication routines, both static and dynamic, are tabulated. We consider a variety of communication primitives including those found in Intel's NX library, PVM and the T3D's SHMEM library. The results show substantial improvement, with two combinations of optimizations being most effective.

Contracts F30602-97-l-0150 and F306O2-97-l-0270 were a joint effort but funded using different contract vehicles at the request of DARPA, the sponsoring agency. This report documents the design and development of CILK, a language for multi-threaded parallel programming based on ANSI C. CILK is designed for genera-purpose parallel programming, but it is especially effective for exploiting dynamic, highly asynchronous parallelism, which can be difficult to write in data-parallel or message-passing style. Three world-class chess programs were written in CILK by the CILK group at MIT. CILK provides an effective platform for programming dense and sparse numerical algorithms, such as matrix factorization and N-body simulations. Unlike many other multithreaded programming systems, CILK is algorithmic, in that the runtime system employs a scheduler that allows the performance of programs to be estimated accurately based on abstract complexity measures. CILK is available for download at http:/supertech. lcs . mit. edu/cilk/

This report documents the task of migrating MATLAB programs to ZPL so that the computations can run on parallel platforms and achieve significant performance improvements. It entails three tasks: Upgrade ZPL to support sparse representations, provide an interface to a parallel scientific library, and provide a mechanism by which programmers can know when their MATLAB programs have limited parallelism. The project achieved all three goals. The prototype was fully implemented and made available over the Internet. In benchmark tests ZPL programs were shown to perform as well as or better than programs written by experts using C and message passing. ZPL programs are fully portable running well on any UNIX platform. Additionally, the language is convenient, automatically producing all concurrency, all communication and very aggressive scalar optimizations. This research produced two dozen technical papers and four PhD dissertations.

In this paper, we consider the problem of generating efficient, portable communication in compilers for parallel languages. We introduce the Ironman abstraction, which separates data transfer from its implementing communication paradigm. This is done by annotating the compiler-generated code with legal ranges for data transfer in the form of calls to the Ironman library. On each target platform, these library calls are instantiated to perform the transfer using the machine's optimal communication paradigm. We confirm arguments against generating message passing calls in the compiler based on our experiences using PVM and MPI — specifically, the observation that these interfaces do not perform well on machines that are not built with a message passing communication paradigm. The overhead for using Ironman, as opposed to a machine-specific back end, is demonstrated to be negligible. We give performance results for a number of benchmarks running with PVM, MPI, and machine-specific implementations of the Ironman abstraction, yielding performance improvements of up to 42% of communication time and 1–14% of total computation time.

This paper describes a new approach to compiling and optimizing array languages for parallel machines. This approach first decomposes →ray language operations into factors, where each factor corresponds to a different communication or computation structure. Optimizations are then achieved by combining, or joining, these factors. Because factors preserve high level information about array operations, the analysis necessary to perform these join operations is simpler than that required for scalar programs. In particular, we show how data parallel programs written in the ZPL programming language are compiled and optimized using the factor-join approach, and we show that a small number of factors are sufficient to represent ZPL programs.

The right model of parallel computation must possess various properties including accurately predicting the behavior of real programs on physical computers. It is argued that this property must be tested experimentally. Three experiments are reviewed supporting the hypothesis that the CTA machine model and the Phase Abstractions programming model predict accurately for real programs on physical computers. Data for ten MIMD computers is reported. Additionally, basic concepts connected with models of computation are reviewed, and several recently developed parallel models are critiqued.

This paper presents performance results for ZPL programs running on the Kendall Square Research KSR-2 and the Intel Paragon. Because ZPL is a data parallel language based on the Phase Abstractions programming model, these results complement earlier claims that the Phase Abstractions model can lead to portability across MIMD computers. The ZPL language and selected aspects of the compilation strategy are briefly described, and performance results are compared against hand-coded programs.

Generally, routers used in state-of-the-art parallel computers are a form of oblivious router known as demonstration order routers. Examples include the iPSC/2, nCUBE, DELTA, Paragon, Dash, J-Machine, etc. In networks based on these routers all packets between source S and destination D take a single path, oblivious to network congestion and faults. This can lead to poor performance under high loads when congestion can be significant, and to system failure in large or unmaintainable systems where faults are likely. For these two reasons - performance and dependability - adaptive routing techniques have long been advocated. Adaptive routers can be divided into two broad classes, minimal adaptive, in which packets always take a shortest path to their destinations, and nonminimal adaptive, in which packet routes are not restricted to shortest paths. Though there have been many proposals for both types, it is generally true that nonminimal adaptive routers are superior minimal adaptive routers 10, 13. This is consistent with one's intuition follows: Although minimal adaptive router can bypass congestion by sending packets along alternate paths, they discover the congestion too late. That is, when there are no alternate forward paths to choose from, the packet's forward progress is stalled, and is now contributing to the congestion. This affect motivates nonminimal adaptive routing in which a packet can back up or deroute, and go around congestion when there are no forward paths.

The trans-2,3-disubstituted pyrrolidine moiety, found in the pyrrolizidine alkaloids as well as other natural product, has been accessed from the α,β-unsaturated bicyclic lactams 1d and 10. Conjugate addition of lower order cyanocuprates to lactams 1d and 10 resulted in endo entry of the cuprate with high diasterelectivity. Other cuprates were investigated and resulted in diminished or opposite stereoselectivities. Further transformation of the β-subtituted lactams provided the title compounds in good overall yield and high enantiomeric excess

The design of a protection system for an operating system is seen to involve satisfying the competing properties of richness and integrity. Achieving both requires the interplay of analysis and synthesis. Using a formal model from the literature, three designs are developed whose integrity (with the help of the model) can be shown.

Any assessment of the “cost” of encoding one data structure in another must take into account, among other issues, the intended patterns of traversing the guest structure. Two such “usage patterns,” namely, worstedge traversal and all-edges-equally-likely traversal, are particularly significant, since any bounds on encoding costs relative to these patterns yield bounds relative to large classes of other patterns also. The foregoing remarks are formalized in this paper, and a number of techniques for bounding the costs of encodings relative to these special usage patterns are developed and exemplified. Specifically, data structures are represented here as undirected graphs; and a number of lower bounds on the costs of data encodings are derived by comparing various structural features of the guest and host graphs. Relevant features include both maximum and average vertex-degree, “volume,” and “exposure,” a measure of connectivity.

A model is defined in which questions concerning delay bounded asynchronous parallel systems may be investigated. It is shown that synchronization problems, similar to the “firing squad synchronization problem”, cannot be solved by delay bounded asynchronous systems. Three conditions called persistence, determinacy, and single change are introduced. These conditions are shown to be sufficient to guarantee that a synchronous execution policy can be relaxed to an asynchronous execution policy with no change to the result of the computation. This is a Church-Rosser type theorem, but in addition, the asynchronous execution time is shown to be only (D+1) times the synchronous execution time where D is the delay bound. Finally, a wide class of recognition problems is identified which can be solved by linear asynchronous structures.

Manabrea' s remark, referring to a design option for Babbage' s Analytical Engine, has been cited (Hockney & Jesshope 198 1) as the earliest reference to parallelism in computer design. The fact that Babbage considered parallelism allows us to conj ecture that nearly a century and a half ago he understood the obvious, but nevertheless, Fundamental Law of Parallel Computation: A parallel solution utilizing p processors can improve the best sequential solu­ tion by at most a factor of p. T his law's truth follows from the observation that a speedup greater than a factor of p implies the existence of a better sequential solution. It provides an upper limit on achievable performance that has been difficult to approach in practice, much less to achieve. After only two decades of serious study (Hockney & Jesshope 198 1) and only preliminary analysis of the limits to speedup (Hwang & Briggs 1984 , p. 28) , it is certainly premature to be pessimistic about our ultimate success at attaining the maximum predicted benefits of parallelism. Still, there are reasons to be cautious. As a practical matter the scientific and commercial problems that are most in need of speedup are the so-called compute-bound problems (Bardon & Curtis 1983) since the I/O-bound problems would yield to better data transmission technology not more processing capability (Boral & DeWitt

One of the outstanding contributions during this reporting period has been our work in the energy complexity analysis of VLSI designs. An extensive theoretical analysis has been made of the energy requirements of several classes of functions, in particular transitive and one-switchable. A surprising result of this work is that, for systolic implementations of some of these functions, the average case energy consumption is of the same order as worst case. For this reason the energy optimization of many datapath systolic systems gives negligible returns. Another work in this area analyzes the speed and energy tradeoffs of dynamic and static PLA designs within various application domains. A major project of this reporting period has been the definition of a model for generator construction. The intent of the model is to provide a concise representation that captures the fundamental structural and functional properties of the circuit. With this representation a variety of output descriptions may be derived. During the past six months the model has been refined and a language parser written. Work is currently underway on the backend programs that analyze the model and produce schematics, layouts, and functional descriptions.

This document gives a succinct description of the facilities available with the Poker Programming Environment. The emphasis is on what is available rather than how to achieve particular results. Although the sections are self-contained, so that they may be referred to independently, there are a few things you should know: 1) Poker uses interactive graphics. The graphics are described in Section 2; the interaction is described in Section 3; 2) The usual programming language notion of a source program as a monolithic piece of symbolic text has been replaced in Poker by a database. The way to create, view, and change the database is described in Section 4; 3) Object programs (the compiled database) are executed or emulated by Poker and snapshots of the execution can be continuously displayed; 4) Poker supports a variety of CHiP architectures; the current one can be displayed or changed using the CHiP parameters facility, Section 7; 5) The back page of this document gives a summary of the command; and 6) Other versions of Poker exist; consult Appendix B for your particular system.

This document gives a succinct description of the facilities available with the Poker Parallel Programming Environment. The emphasis is on what is available rather than how to achieve particular results. Although the sections are self-contained, so that they may be referred to independently, there are a few things you should know: 1) Poker uses interactive graphics. The graphics are described in Section 2; the interaction is described in Section 3; 2) The usual programming language notion of a 'source program' as a monolithic piece of symbolic text has been replaced in Poker by a database. The way to create, view, and change the database is described in Section 4; 3) Object programs (the 'compiled database') are executed or emulated by Poker and snapshots of the execution can be continuously displayed; 4) Poker supports a variety of CHiP architectures; the current one can be displayed or changed using the CHiP Parameters facility; Section 7; 5) The back page of this document gives a summary of the commands; and 6) Other versions of Poker exists; consult Appendix B for your particular system.

Parallel computer architecture complicates the already difficult task of parallel programming in many ways, e.g., by a rigid interconnection structure, addressing complexity, and the shape and size mismatches. The CHiP computer is a new architecture that reduces these complications by permitting the processor interconnection structure to be programmed. This new kind of programming is explained. Algorithms are presented for several interconnection patterns including the torus and the complete binary tree and general embedding strategies are identified. (Author)

Between the conception of a real time signal processor and its functional, VLSI realization there is an enormous amount of effort devoted to designing, revising, optimizing and testing. Since the process is cumulative -- later work builds on previous work -- and since the activity becomes progressively more detailed, more constrained and more exacting, it follows that the global design parameters should be fully explored. Global design decisions, when correct, can have a greater effect on performance than many local optimiza-tions. When the decisions are wrong, they can cause continual difficulty. Accordingly, we propose a design methodology based on the Configurable, Highly Parallel (CHiP) architecture family1 that focuses on exploring global design parameters and is especially well suited to the VLSI implementation of signal processing systems.

The main question under study is how wide the corridor width should be for the switch lattice of the Configurable, Highly Parallel (CHiP) computer. (The CHiP computer family is introduced and its use for parallel algorithm composition is motivated.) It is argued on the basis asymptotic analysis that a constant corridor width is preferred even though such lattices cannot make full use of the processor elements for most complex interconnection patterns, e.g., universal interconnection structures like the cube connected cycles and shuffle exchange, and for certain 'simple' ones, e.g., certain planar graphs. (Author)

Publisher Summary This chapter discusses VLSI related topics ranging from models and implementation techniques, through specific algorithms, to a programmable system for a family of algorithms. Very large scale integration provides the technological impetus for algorithmic specialization, because high density, low cost chips make the implementation feasible. The lower the hardware costs become the wider is the range of problems for which specialized hardware is economically justified. Although the availability of VLSI technology may make it practical to have specialized systems, the medium is not perfectly malleable. Many problems must be solved before an algorithmically specialized processor is implemented in VLSI. For example, VLSI technology favors planar architectures with much geometric locality, but these characteristics have not typically been considered. Moreover, they are often difficult to achieve.

Multigauge computers can operate either with their full datapath width or with the datapath split into separate narrower width machines. Such a concept has been previously shown to provide parallelism when the data values are small. This paper reports on the costs of gauge-shiftable computers. Specifically a single chip microprocessor, the 32-bit Quarter Horse machine, is redesigned to be gauge shiftable under software control to two 16-bit microprocessors. A complete accounting of the effects of gauge shifting on computer architecture is thus realized. Care is taken to identify the effects on the design of SIMD and MIMD executions. The general costs of gauge shifting for other implementation strategies are also identified.