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A fully integrated 25 Gb/s low-noise optical receiver is presented which integrates transimpedance amplifier (TIA), continuous-time linear equalizer (CTLE), high-gain and high-bandwidth limiting amplifier (LA), and clock and data recovery (CDR) circuit into a single die. The TIA employs an inverter-based pseudo-differential TIA scheme with input series-inductor peaking, cross-coupled negative Gm pair and negative capacitance to improve the bandwidth, and noise performance, while a MOSFET corner compensation (MCC) circuit compensates for CMOS corner variations. A gain control (GC) scheme is proposed which solves the group delay issue caused by TIA input impedance variations from small input to overload current. Finally, a 2x-oversampling CDR using a bang-bang phase detector is included. The receiver is fabricated in 40-nm CMOS process, and the 850 nm VCSEL-based full-link measurement results show that the optical receiver achieves 44 $\mu \text{A}_{\mathrm {pp}}$ (RSSI Current = 43 $\mu \text{A}$ , ER = 4.94 dB) optical modulation amplitude (OMA) sensitivity (BER

In this paper, a small-signal model of Negative Capacitance FETs (NCFETs) is developed and the analog performance of NCFETs is studied using the developed model. A new ferroelectric factor K is introduced to capture the ferroelectric gain in NCFETs as compared to traditional small signal MOSFET/FinFET models. Using our new NCFET small-signal model, we show analog design trade-offs between various analog benchmarks such as gain, bandwidth, cut-off frequency, and linearity. Additionally, the developed model is used to demonstrate trade-offs in NCFET analog performance as ferroelectric parameters are changed. Results show that if pushed for a higher intrinsic gain via thicker Fe layers in NCFETs, the linearity of the device suffers. This reveals inherent device level trade-off in NCFETs for analog circuit performance.

Industries scaled down the size but the supply voltage was still in the 1 V range for a decade. Reducing power consumption needs supply voltage to be reduced especially for Dynamic Random-Access Memory (DRAM) which is a storage device whose dynamic power consumption is proportional to the square of the power supply. In this work, design of low power consuming DRAM and Static Random-Access Memory (SRAM) with Ferro Electric Field Effect Transistor (FEFET) as transistor nodes which has higher subthreshold swing due to negative capacitance, hence a lower power supply can be applied and changing process parameter to find Static Noise Margin (SNM) of SRAM and characteristics of DRAM. The simulations are carried out with cadence for 32 nm Verilog-a model and are analyzed with Python.

Herein, cadmium bromide thin film devices are designed for possible use in communication technology. The 1.0 μ m thin layer of CdBr2 is sandwiched between two Au (1.0 μ m thick) layers using the thermal evaporation technique under a vacuum pressure of 10-5 mbar. The Au/CdBr2/Au devices are structurally morphologically and electrically characterized. It is observed that the hexagonal cadmium bromide exhibits large lattice mismatches with cubic Au substrates. The randomly distributed nano- rod like grains is accompanied with average surface roughness of ~26 nm. When an ac signal of low amplitude is imposed between the terminals of the Au/CdBr2/Au devices, a negative capacitance effect in the frequency domain of 10-1800 MHz is observed. In addition, analysis of the impedance spectra in the same domain has shown that the device behaves as band pass/stop filters suitable for 4G technology. The microwave based standard analysis of the Au/CdBr2/Au band filters have shown that it displays a notch ( f c o) frequency of 2.0 GHz. The cutoff frequency at f c o reaches 7.86 GHz. The features of the Au/CdBr2/Au devices nominate it for use as microwave resonators and as negative capacitance devices suitable for; 4G technology, noise reduction and for parasitic capacitance cancellation.

This work investigates, for the first time, the impact of different variability sources on the reliability of SRAMs implemented using the Negative Capacitance FinFET (NC-FinFET) technology in comparison to the baseline conventional FinFET technology. Unlike the existing state of the art, our investigation is for NC-FinFETs constructed in a Metal–Ferroelectric–Insulator–Semiconductor (MFIS) structure. Our analysis is based on calibrated TCAD simulations in which baseline FinFETs are calibrated to reproduce Intel 14nm measurements for both I-V characteristics and variation. NC parameters were extracted by fitting the Landau model to an experimentally-measured S shaped polarization-electric field curve. Our key focus is on revealing the individual and combined impact of variability sources on the noise margins of SRAMs. We demonstrate that NC-FinFETs based SRAMs exhibit a higher immunity against variation due to the better electrostatic integrity caused by NC.

This paper reports the design of a tunable active high-pass filter, based on negative circuit elements. The device comprises ordinary inductance and capacitance juxtaposed with negative inductance and negative capacitance, generated by two independent Negative impedance Converters (NIC’s). The filter design model is proposed and numerically verified using a commercial circuit simulator, with stability taken in consideration.

This contribution proposes a band-pass non-Foster negative inductor. Its stability properties are superior to those from standard designs, including possibility of achieving overall negative inductance. Proposed band-pass negative inductor is based on Negative Impedance Converter (NIC) of Open Circuit Stable (OCS) type. Stability analysis revealed that there is inevitable trade-off between generated negative inductance and achieved operating bandwidth.

In an ideal case, a negative impedance converter (NIC) transforms the load impedance or admittance into its negative image. However, due to non-idealities present in electronic circuitry of NIC, there will always be some conversion error. On the other hand, conversion of resonant load is, among others, important for the use in recently introduced self-oscillating antennas based on negative immittance conversion. Namely, it was noticed that operation of such transmitter is limited by the resonant nature of the antenna. Therefore, in this paper, we investigate the influence of NIC dispersion on the conversion of generic resonant load. The effect is analysed both for short circuit stable (SCS) and open circuit stable (OCS) grounded NIC based on operational amplifiers. Transient and S-parameter simulations were performed with the help of circuit theory simulator. It was noticed that both NIC types show lower conversion errors for the frequencies at which the load has capacitive character.

A broadband matching of a highly reactive small transmitting antenna is one of the most challenging applications of non-Foster elements. The difficulties are connected to the assurance of stable operation of negative impedance converter in environment with high-power signals. Recently, the instability-free approach that applies quadrature signals at a transmitting short dipole and mimics broadband cancellation with negative capacitor, has been demonstrated. Here, we propose an extension of this approach to emulation of negative inductance, as well as to the most general case of a complex matching with transformation of antenna radiation resistance. Theoretical analysis is complemented with several proof-of-concept experiments in 10-20 MHz HF band.

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, ION of the order of 100 nA µm−2 and ION/IOFF > 104 at Vd = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.

The current work presents a novel structure of epitaxially grown CuInGaSe2/SiO2 on n-Si substrate using the liquid phase epitaxy (LPE) technique. The electrical and dielectric properties of quaternary alloy CuInGaSe2/SiO2/n-Si were investigated as a Schottky barrier device. The effect of temperature, voltage, and frequency on the electric and dielectric parameters such as dielectric constant ɛ′, dielectric loss ɛ″, dielectric loss tangent tanδ, the real and imaginary part of modulus M′, M″, ac conductivity σac and series resistance Rs were studied by measuring the capacitance–voltage within the temperature range of (303–393 K) and DC voltage range (± 5 V). Both capacitance and conductance were highly affected by varying voltage, frequency, and temperature. Remarkably, capacitance has positive values at high frequencies while it takes negative values at low frequencies. The negative capacitance (NC) was observed for all temperatures. The thickness of the oxide layer was 84 × 10–9 nm. The density of states Nss, Ideality factor, series resistance, shunt resistance, and barrier height were assessed. The impedance spectrum investigation was tailored by suitable equal circuits comprising the contributions of grain and grain boundaries in the conduction mechanism.

In this work advanced TCAD (Technology Computer Aided Design) modeling will be used aiming at investigating the potentiality of Negative Capacitance (NC) devices in non-conventional application domains (e.g., radiation detection). A device-level approach to simulate the electrical characteristics of ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) has been developed. The validation of the models and of the adopted numerical methods relies on the comparison between simulations and measurements of Metal-Ferroelectric-Metal and Metal-Ferroelectric-Insulator-Metal capacitors. The ferroelectric/dielectric interface could be therefore studied before and after X-ray irradiation. The goal will be to investigate the suitability of innovative NC devices to be used in High Energy Physics experiments detection systems, featuring self-amplified segmented, high granularity detectors.

In this study, the temperature effect on Zirconium doped HfO 2 (HZO) based Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) type Fully depleted Silicon on Insulator (FDSOI) negative capacitance field effect transistor (NCFET) has been investigated in ATLAS TCAD. The MIS device simulation has been performed in TCAD and its gate charge (Q G ) has been extracted. The extracted charge is further utilized in 1D Landau-Khalatnikov (LK) model to find the voltage across ferro-electric (V FE ), that subsequently used to add the effect of HZO analytically to the device. Performance parameters like minimum sub-threshold swing (min. SS), off current (I off ) and transconductance (g m ) with variation of temperature (280 K - 340 K with step 20 K) have been predicted. The performance variation of device with temperature has been explained using 1D LK theory.

In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS], σ[Ion/Ioff], σ[Vt]/µ[Vt], σ[SS]/µ[SS], and σ[Ion/Ioff]/µ[Ion/Ioff], and enhanced device performance, which implies that the NC effect can successfully control the variation-induced degradation.

With the advancement in technology and new insights of MOSFET fabrications, power consumption in VLSI circuits has been optimized to a greater extent. In this work, a comparative analysis is done for the intervention of negative capacitance on baseline switching element i.e. MOSFET. Negative capacitance acts as a transformer, that steps up the gate-source voltage ( $V_{GS}$ ) of field effect transistor thus maintaining a high $I_{on}$ current. A thin layer of $Fe$ material is added with the gate stack of MOSFET to form a series combination of Ferroelectric capacitor ( $C_{FE}$ ) and dielectric capacitor. Device characteristics have been plotted and sub-threshold swing (SS) has shown remarkable improvement by the integration of negative capacitance effect as compared to baseline MOSFET. Steeper SS of 50.75 mV/dec is achieved in case of NCFET. This work indicates that NCFET has a great potential to replace the conventional MOSFET device in low power circuits.

Polarization switching in ferroelectric films is exploited in many applications, such as non-volatile memories and negative capacitance field affect transistors. This can be inhomogeneous or homogeneous, depending on if ferroelectric domains are forming or not during the switching process. The relation between the polarization switching, the structural quality of the films and the negative capacitance was not studied in depth. Here, Pb(Zr0.2Ti0.8)O3 (PZT) layers were deposited by pulse laser deposition (PLD) and sol-gel (SG) on single crystal SrTiO3 (STO) and Si substrates, respectively. The structural quality was analyzed by X-ray diffraction and transmission electron microscopy, while the electric properties were investigated by performing hysteresis, dynamic dielectric measurements, and piezo-electric force microscopy analysis. It was found that the PZT layers grown by PLD on SRO/STO substrates are epitaxial while the layers deposited by SG on Pt/Si are polycrystalline. The polarization value decreases as the structure changes from epitaxial to polycrystalline, as well as the magnitude of the leakage current and of the differential negative capacitance, while the switching changes from homogeneous to inhomogeneous. The results are explained by the compensation rate of the depolarization field during the switching process, which is much faster in epitaxial films than in polycrystalline ones.

In this work, negative capacitance effect of MFMIS type FDSOI NCFET is investigated considering two well known thin film ferroelectric materials HZO (Zirconium doped HfO 2 ) and HSO (Silicon doped HfO 2 ). The investigations are carried out in a TCAD environment where the gate charge is extracted from the TCAD simulation and subsequently computed ferro voltage across the ferroelectric capacitor to find the effective gate voltage in the gate-stack. The obtained values are then subjected to variation in ferroelectric thickness to predict the onset of hysteresis for both HZO and HSO ferroelectric materials. It has been observed that the HZO ferroelectric offers superior improvement in sub-threshold slope (SS), peak-gm and off-current at lower ferroelectric thickness with the expense of gate-induced-drain-leakage (GIDL) and lower endurance to hysteresis. On the other hand, the HSO ferroelectric predicts improvement in SS, peak-g m and off-current with superior control in GIDL where the device has higher endurance towards hysteresis in-spite of ferroelectric thickness under sub-10 nm regime.

The main objective of this paper is to develop a driving circuit for a QCM sensor based on the detection of RNA virus. The circuit uses negative capacitance compensation technology, automatic gain control circuit and differential operation circuit, and this structure will improve the starting conditions of the resonant circuit and achieve continuous stability of the circuit oscillation. Thus the QCM front-end oscillation driving circuit can oscillate stably in a liquid phase environment. By connecting the Bessel band-pass filter, The circuit is stable under three harmonics at 15MHz, Removing some clutter in the oscillation process, and the obtained frequency is limited to a certain range, ensuring that the single-chip machine can read out the most accurate crystal frequency. Through the rail-to-rail operational amplifier chip, the frequency signal is fixed within a certain interval to ensure that the microcontroller can read the valid output frequency signal. Further, a frequency counter is used to count and display the read frequencies. Finally, the stability of the circuit is verified experimentally, and the experimental results and the theoretical calculation results of the formula are analyzed for error. When the experiment requires high parameters, the temperature fuzzy self-correcting PID control algorithm is used to control the operating environment temperature of the instrument within a basically constant range to reduce the error.

In this letter, for the first time, we investigate the role of Ferroelectric (FE) spacer in a negative capacitance (NC) FinFET. Using well-calibrated TCAD models, we found that instead of placing a dielectric (DE) spacer, if we use an FE spacer, enhanced electric field due to FE polarization can be achieved, thereby producing a higher ON-current. The fringing fields polarize the FE spacer and result in voltage amplification, which lowers the effective barrier and increases the current driving capability. ON-current of the proposed configuration, i.e., FE spacer at the source (S) side and DE spacer at the drain (D) side, is ~30% higher than the baseline FinFET. In this work, we have also proposed four different spacer placement configurations to realize better performances in terms of higher ON-current, mitigation of negative differential resistance (NDR) and better subthreshold slope (SS), and so on. We found that the optimized performance can be attained by placing an FE and DE spacer at the S and D end, respectively. We also evaluated a design space window for a good capacitance match to achieve NC effect for optimized device design.

Two structures of ferroelectric negative capacitance field-effect transistors (NCFET) show difference in their electrical characteristics. TCAD numerical simulation is used to reveal the origins of these differences from a more physical perspective. It is found that a metal interlayer in NCFETs changes the local charge matching into total charge matching, leading to an increase of the threshold voltage with the drain voltage and a decrease of the subthreshold current. At the same time, the metal interlayer induces a large electric field along the channel direction, especially for ferroelectric materials with small remnant polarizations, hence a higher on state current.

In this work, the electrical performance of the negative capacitance gate-all-around nanosheet junctionless transistors (NS-NCJLT) at advanced technology node is studied. The NS-NCJLT shows better performance than NS-JLT such as the higher driving current and steeper subthreshold slope (SS). Besides, the NS-NCJLT is proved has the best performance after benchmarked against its counterparts based on FinFET and nanowire structures. Then it is found that the smaller-size NS-NCJLT benefits more from NC effect, which indicate it could be applied more appropriately to the 7-nm device and beyond. Finally, we have investigated the influence of self-heating effect on NS-NCJLT. The results show that although the introduction of ferroelectric layer increases the heat conduction path, the electrical properties of NS-NCJLT still be enhanced.

In the contemporary era of Internet-of-Things (IoT), there is an extensive search for competent devices which can operate at ultralow voltage supply. Due to the restriction of power dissipation, a reduced sub-threshold swing-based device appears to be the perfect solution for efficient computation. To counteract this issue, negative capacitance fin field-effect transistors (NC-FinFETs) came up as the next-generation platform to withstand the aggressive scaling of transistors. The ease of fabrication, process-integration, higher current driving capability, and ability to tailor the short-channel effects (SCEs) are some of the potential advantages offered by NC-FinFETs that attracted the attention of researchers worldwide. The following review emphasizes how this new state-of-art technology supports the persistence of Moore’s law and addresses the ultimate limitation of Boltzmann tyranny by offering a sub-threshold slope (SS) below 60 mV/decade. The article primarily focuses on two parts: 1) the theoretical background of negative capacitance (NC) effect and FinFET devices and 2) the recent progress done in the field of NC-FinFETs. It also highlights the crucial areas that need to be upgraded, to mitigate the challenges faced by this technology and the future prospects of such devices.

Over the last few years, there has been increased interest in Vacuum Field Effect Transistors (VFETs) with nanoscale features [1]-[4]. Compared to traditional MOSFETs and FINFETs, VFETs offer advantages in terms of electron velocity, fast switching speed, extreme operating temperatures, and radiation robustness. We calculate the field emission (FE) characteristics of a back-gated nanomembrane VFET making use of the concept of negative capacitance. It is found that the proposed negative capacitance VFET (NC-VFET) has a minimum subthreshold swing (SS) of 34mV/decade, well below the thermionic limit of 60mV/dec at room temperature.

In our work, we demonstrate a 4H-SiC gate-all-around cylindrical nanowire junctionless (GAA-NWJL) metal oxide field effect transistor (MOSFET) with a negative capacitance (NC) in 20 nm gate length. This paper obtains a subthreshold swing (SS) lower than 60 mV/decade, which is the critical point in conventional MOSFETs. Also, a low drain-induced barrier lowering (DIBL) has been achieved at 21 mV/V. A high Ion/Ioff ratio ~ 4 × 1013 and shallow leakage current ~ 8 × 10–19 A are shown. We investigate the influence of the channel length, doping concentration, gate dielectric, and nanowire diameter on the device characteristics and short-channel effects of the GAA-NWJL. Besides, subthreshold slope, DIBL, leakage current, Ion/Ioff ratio, and band-to-band tunneling (BTBT) results have been analyzed. Lead zirconate titanate (PZT), as a ferroelectric material with negative capacitance (NC), is used at the top of the oxide region to obtain an ideal subthreshold swing at sub 60 mV/decade. Because of working in the sub-10 nm, quantum confinement impacts are considered. Furthermore, the 1D Landau–Khalatnikov (L–K) equations are considered in the structure simulations.

Negative Capacitance FET (NCFET) is one of the most promising variants of the emerging steep-slope transistors, able to overcome the ?Boltzmann limit'. The ferroelectric layer in the gate stack brings in new dynamics to the transistor operation by amplifying the surface potential. Steeper subthreshold slope, higher ON/OFF ratio, and the possibility to attain negative output conductance provide unique opportunities for NCFET-based circuit design. However, NCFETs inherently possess additional sources of variation, and hence, the promise of performance benefits in the nominal designs must be examined through extensive variation analysis. The non-volatile ferroelectric FETs (FEFETs) are promising candidates for storage-class memory, whereas the volatile NCFETs are suitable for high-speed SRAM design. In this work, we first draw a contrast between the modeling approaches ideal for the non-volatile FEFETs and volatile NCFETs. We then utilize a compact model for NCFET to analyze the design possibilities in an NCFET-based 6-T SRAM cell compared with its conventional counterpart ? both implemented in the 10 nm technology node. We examine the read, write, and hold performance of the SRAM cells through Monte Carlo variation analysis. We show that, even with additional variation induced spread in the device characteristics, NCFET-based SRAM cell can achieve better Static Noise Margin (SNM) during read/hold modes and allows more aggressive supply voltage scaling. The increased hold stability imposes a penalty in the write performance ? forcing design trade-offs.

A new kind of negative group delay (NGD)/non-Foster circuit using monolithic microwave integrated circuit (MMIC) technology is presented. The proposed design is based on an active transversal filter topology using a distributed amplifier (DA) with a cascode configuration at each stage of gain cells, realized by using WIN's 0.1-um GaAs pseudomorphic high electron mobility transistor (pHEMT) process. Furthermore, a forward-biased Schottky barrier diode (SBD) is utilized as a phase shifter to adjust the absolute phase of S21. By properly applying the gate bias voltage and controlling the phase shifter, the proposed NGD circuit can synthesize a negative capacitance of −0.3 pF with a bandwidth of 500 MHz at around 5 GHz while ensuring unconditional stability. The fabricated MMIC NGD/non-Foster circuit has a footprint of 3. 05×3. 15mm2 with a power consumption of 125 mW. Measurement and simulation results show great agreement with each other.

The article presents the results of a study of the electrical properties of semiconductor perovskite ceramics based on a solid solution of barium-strontium titanate with the addition of the rare earth element of cerium with the initial formula Ba1–x–y SrxCeyTiO3 (x = 0.05, y = 0.003). A scanning electron microscope was used to obtain images of the sample surfaces and the elemental composition data. The measurements were performed by impedance spectroscopy in the temperature range of 348-385 K in the frequency range of 102–106 Hz using an LCR metre. It was found that there is an anomalous behaviour in the dynamic electrical conductivity of the samples in the temperature range close to the ferroelectricparaelectricphase transition. This is expressed by a decrease in the value of the real part of the dynamic conductivity withan increase in frequency. An analysis of the simplified equivalent circuit of the intergranular barrier showed that this anomaly can be explained by introducing an inductive element into the circuit. This element can be considered a “negative capacitance element”. Following the results of the study, a conclusion was made about the generalised character of the phenomenon

The negative capacitance (NC) operation of ferroelectric materials has been originally proposed based on a homogeneous Landau theory, leading to a simple NC stabilization condition expressed in terms of macroscopic quantities. A multi-domain theory, however, has pointed out the importance of microscopic parameters, such as the domain wall energy coupling constant, and it helped explain the somewhat contradicting experiments for ferroelectric capacitors with or without a metal interlayer. In this work we use comprehensive numerical simulations and simplified equations to correlate the macroscopic features of the NC operation to the underlying microscopic picture. We show that, while the domain wall coupling constant plays a critical role in a quasi static operation, the transient NC operation is less sensitive to this parameter. In particular, ferroelectric capacitors with a very small coupling constant can still display a robust transient NC behavior, closely tracking the ‘S’-shaped polarization versus field curve and with negligible hysteresis. Our results have been developed in the framework of a systematic comparison between simulations and experiments, and they provide both a better understanding of the NC operation and a sound basis for the design of future NC based devices.

In this paper, we investigated the double metal negative capacitance field-effect-transistor (DM NCFET) for improved digital and analog performance in comparison to the conventional negative capacitance field-effect-transistor (NCFET) by using a new concept of ferroelectric layer (HfO 2 FE). Visual TCAD software is used to design DM NCFET. The results have been analyzed in form of leakage current (I off ), transconductance (G m ), transconductance generation factor (TGF), Early Voltage (V EA ), intrinsic gain (A v ), unity gain cutoff frequency (f T ) and improved performance of output conductance (G d ), drain barrier induced lowering (DIBL), switching ratio I on / I off , subthreshold swing (SS). Thus, DM NCFET can be suitable for digital and analog circuit applications.

In this work, we examined a new design approach of field-effect transistor with ferroelectric material layer (FE-FET) based on the theory of negative capacitance, which helps in lowering the sub-threshold swing and lift on-off current ratio with small hysteresis. The intensive investigation was performed on a conventional field-effect transistor (FET) and proposed FE-FET device. TGF, g d , Cgg, V A and short channel effect (DIBL, SS, V TH ) and f T are discussed and compared. The results suggest that the proposed device can be used in ultralow power and ultralow voltage that works as a new energy-efficient device because the off current is decreased by one order of magnitude and also subthreshold swing in linear and saturation region is decreased by 7.09% and 16.86% respectively.

Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a simplified model by taking proper approximation in each operating region. This is a surface potential-based compact model, which is suitable for evaluating the I–V characteristics for each operating region. It was validated that the proposed model shows good agreement with the results of implicit numerical calculations. In addition, by using the proposed model, we explored the electrical properties of the NC GAA-FET by varying the basic design parameters such as ferroelectric thickness (tfe), intermediate insulator thickness (tox), silicon channel radius (R), and interface trap densities (Net).

In this paper, the observation of transient negative capacitance signature (NCS) in an organic ferroelectric gate stack (OFEGS) at minimum supply voltage (Vs) of ±0.5 V is investigated employing a well-calibrated Ginzburg-Landau-Khalatnikov (GLK) model in the environment of Sentaurus technology computer-aided design (STCAD). We observe an 88.62 to 94.76 % reduction in the average coercive voltage (Vc) of the proposed OFEGS, which is still a significant challenge for the conventional ferroelectric (FE) lead zirconate titanate. We study the resistor-OFEGS (RC ofe ) series network behaviors in response to a bipolar and unipolar triangular signal. Our findings prove that the presence of NCS is directly correlated with the FE polarization (FEP) switching and not because of any extrinsic defects in the system. The various impacts of Vs, GLK parameters, R, dipole switching resistivity (R ofe ) variations on the NCS response are investigated. The proposed OFEGS can harness the NCS effect at ±0.5 V with minimum energy dissipation of 4.81 × 10-16 J, a challenge for the oxide FE-based gate stacks. Calibrating R to the maximum limit, we can capture the S-shaped ideal Landau path where the NCS is maximum with a small deviation of about ±0.006 V at zero FEP. Finally, an OFEGS based Landau transistor is implemented, providing a minimum subthreshold swing (SS min ) of 38.21 mV/decade, which is 36.32 % lesser than the fundamental SS min limitation of 60 mV/decade. Therefore, the proposed OFEGS with a minimum Vs and remanent polarization (P r =3D 1.244 μC/cm2) could be used as a gate stack for designing sub-60 mV/decade transistor technology.

A systematic device-model calibration (extraction) methodology has been proposed to reduce parameter calibration time of advanced compact model for modern nano-scale semiconductor devices. The adaptive pattern search algorithm is a variant of the direct search method, which explore in the parameter space with adaptive searching step and direction. It is very straightforward, but powerful, in high dimensional optimization problem since adaptive step and direction are decided by simple computation. The proposed method iterates less but shows superior accuracy over the conventional method. It is possible to be applied to a behavioral or empirical model correspond to emerging devices, such as tunneling field-effect transistor (TFET) and negative capacitance field-effect transistor (NCFET) due to its universality in parameter calibration for the model accuracy.

An open-loop baseband filter with bandwidth of 1GHz suitable for a receiver operated in the 5G high frequency band (above 24GHz) is presented. The filter is based on a gain boosted Common Gate topology that implements a 2nd order low-pass filter in the current domain. A frequency-dependent active negative capacitance circuit is used to boost the quality factor of the filter. This not only improves in-band flatness but also increases out-of-band selectivity. A test chip has been realized in 28nm CMOS technology. The filter bandwidth can be programmed from 650 MHz to 1 GHz and the current gain changed by 14 dB, with the power dissipation scaling from 11 mW to 5 mW. In-band IIP3 is +2 dBm and the input noise integrated from 10 MHz to 1 GHz is lower than 170 μV rms .

Electrochemical impedance spectroscopy (EIS) has been extensively used for the detailed investigation and understanding of the plethora of physical properties of variegated electrochemical and solid-state systems. Over the past few years, EIS has revealed many significant findings in hybrid halide perovskite (HHP)-based optoelectronic devices too. Photoinduced ion-migration, negative capacitance, anomalous mid-frequency capacitance, hysteresis, and instability to heat, light and moisture in HHP-based devices are among the few issues addressed by the IS technique. However, performing EIS in perovskite devices presents new challenges related to multilayer solid-state device geometry and complicated material properties. The ions in the perovskite behave in a specified manner, which is dictated by the energy-levels of the transport layer. Electronic-ionic coupling is one of the major challenges to understand ion transport kinetics in solid-state devices. In this work, we have performed impedance measurements in both solid-state (S-S) and liquid-electrolyte (L-E) device geometry to unfold the effect of charge transport layers on the ac ionic conductivity in perovskite materials. We have modelled the impedance spectra using the electrical equivalent circuit (EEC) and compared the behaviour of ions in different controlling environments. It was concluded that the AC as well as dc ionic conductivity and the accumulation of ions in the perovskite material are highly influenced by the nature of the interface in different device geometry. Charge accumulation in the S-S device gives rise to large polarisation, thereby negative capacitance or any inductive loop can be observed in the Nyquist plot while in the L-E device the presence of an electric double layer at the perovskite/electrolyte interface reduces the surface polarisation effect. Ionic conductivity is hopping limited in the low field regime and diffusion limited in the high field regime in the S-S device. Moreover, the perovskite/electrolyte based devices are promising candidates for electrolyte gated field-effect transistors, perovskite-based supercapacitors and electrochemical cells for water splitting or CO2 reduction.

Negative Capacitance Field-Effect Transistors (NCFET) are promising significant power reductions while maintaining performance due to their internal voltage amplification. However, the addition of the ferroelectric layer also introduces a higher gate capacitance, which has to be charged and discharged resulting in higher power consumption. This results in trade-offs when employing NC-FinFET with respect to the thickness of the ferroelectric layer and their operating voltage on power, performance and reliability in circuits. This design-space is currently not explored, as existing research focused on a transistor-to-transistor comparison to show the superiority of NC-FinFET at the same voltage. In this work, we evaluate NC-FinFET employment in a full SRAM memory array (including write driver, sense amplifier, pre-charging, etc.) to obtain circuit delay, read and hold power and reliability metrics. This work shows, that solely evaluating SRAM cells results in inaccurate delay and power estimations compared to a full SRAM array. We explore iso-voltage and iso-performance NC-FinFET operation. Additionally, we explore two new operation modes: operating NC-FinFET within the same overall power consumption (iso-power) and operating at the same noise margins (iso-reliability). This exploration shows, for the first time, how ferroelectric layer thickness plays a role on reliability as a 4 nm layer features a 47% loss compared to FinFET. Lastly, we obtain the activity of a register file in a processor simulator to obtain the ultimate impact on power and energy consumption of employing NC-FinFET in a microprocessor.

We have proposed "PN-Body Tied SOI FET (PNBT-FET)" as a candidate of steep subthreshold slope (SS) devices, such as tunnel FETs and negative capacitance FETs, which will be a key device for expanding ultralow power IoT applications. We have already reported that PNBT-FET has SS below 1mV/dec over several orders of the drain current even with ultralow drain voltage of 0.1V [1] – [2] . We also reported the drain current (Id) enhancement effect on PNBT-FET, at previous IEEE SNW [3] .

This work investigates the source-to-drain tunneling and short-channel effects for MFIS-type InGaAs and Si negative-capacitance FinFETs (NC-FinFETs) using theoretical quantum model corroborated with TCAD numerical simulation. Our study shows that, due to the impact of negative capacitance on the potential profile and tunneling distance between source and drain, the short-channel effects and the source-to-drain tunneling current can be substantially reduced. The gap in DIBL and subthreshold swing between InGaAs and Si devices with extremely short gate length (~12 nm) can become closer due to the NC effect.

The idea of harnessing the negative capacitance signature (NCS) effect in a ferroelectric (FE) material is a recent entry in the world of nanoelectronics. There is an urgent need to harness this effect at a minimum supply voltage (VA). Therefore, in this paper, we have investigated the transient NCS response in a series resistor (R)-organic FE (OFE) (RC OFE ) circuit at ±0.4 V employing a well-calibrated multidomain Ginzburg-Landau-Khalatnikov model in Sentaurus technology computer-aided design (STCAD) environment. A remarkable average coercive voltage reduction of about 69 to 90.16 % is achieved concerning different literature reports. The proposed OFE gate stack (OFEGS) can capture the NCS effect even at ±0.4 V, while its counterpart FE hafnium dioxide (HfO2) based gate stack fails to harness the NCS and behaves like a positive linear capacitor. The various influence of the Landau parameters, R, and switching resistivity (ρ OFE ) on the transient NCS behavior are significantly investigated. We found that the NCS response time (δ t ) and the NCS voltage window (δV NCS ) accentuate as R increases. The δt in the proposed OFEGS is much faster (99.77 to ~99.88 %) than its state-of-the-art counterparts. Finally, our OFEGS can capture the maximum δV NCS by coming close to the ideal Landau path with a negligible deviation of about ±0.009 V at zero FE polarization. Therefore, the proposed device capturing NCS with a small V A of ±0.4 V, total switched charge density of 2.54 µC/cm2, and lower energy dissipation of 0.95 fJ could act as a rescuer for many standard transistors from the Boltzmann’s Tyranny.

This work investigates the switching time in negative capacitance (NC) junctionless (JL) and inversion mode (IM) transistors through calibrated simulations. Results highlight that NCJL devices designed with an optimal underlap of 6 nm and appropriate gate work-function achieve a higher effective drain current than NCIM transistors. Our results show that a higher effective drain current improves the switching time in NCJL devices at a shorter gate length of 14 nm. Besides, the impact of device parameters on the switching time of NCJL and NCIM devices is analyzed. Results reported for the first time provide new viewpoints on designing logic circuits using NCJL transistors with improved switching time.

In this paper, fully-coupled Landau–Khalatnikov (LK) and semiconductor equations are solved in a fully coupled manner to study the temperature effect on negative capacitance (NC) in ferroelectric (FE) devices. The validity of the framework is carefully verified with analytical calculations. LK parameters are calibrated to experiment. The temperature effects (100K to 500K) on the FE capacitors and FE junctionless double-gate field-effect transistor (FE-JL-DG-FET) without an internal metal gate are studied. It is found that the FE effect on negative capacitance increases at a lower temperature in both FE capacitor and FET. High dielectric constant (dielectric constant, e ox = 39) oxide is required to achieve super-steep subthreshold slope (2.9mV/dec) in 300K. If regular silicon dioxide (e ox = 3.9) is used, a temperature as low as 100K is required to maintain the NC effect. It is also found that at high V D , the NC effect disappears earlier than low V D .

The rapid increase in interest on Negative capacitance Field Effect Transistors(NCFETs) is due to its Low power applications. NCFETs stepsup the voltage between the oxide and ferroelectric capacitance due to reversing (i.e, amplification) effect of a ferroelectric (fe) layer[1]. These are designed in a way such that its Subthreshold swing overcomes the boltzmann limit. According to the Boltzmann theorem, carriers that can cross the barrier and increase current by a decade need a gate voltage increase of at least 60 mV[2]. This paper presents a new approach for designing NCFETS, where the target is a low subthreshold swing. The proposed model is validated against several experimental data for an double-gate FET architecture.

Based on the equal strain model of composite materials, the material properties of 1-3 piezoelectric composites are studied, and the active sound absorption property of 1-3 piezoelectric composites is studied by using piezoelectric shunt damping technology. According to the electromechanical relationship of the piezo-composites layer in vibration state and the sound transfer matrix of the medium, the research model is established. In this paper, the relationship between the material properties and the sound absorption property of 1-3 piezoelectric composites is studied, and the active sound absorption property of 1-3 piezoelectric composites is studied by using the negative capacitance and resistance circuit. The results show that: the material parameters of polymer phase in 1-3 piezoelectric composites and the thickness of the composite can affect the sound absorption property of 1-3 piezoelectric composites layer. However, due to the limitation of thickness in practical application, the effect of passive sound absorption of 1-3 piezoelectric composites in low frequency range is worse. The sound absorption property of 1-3 piezoelectric composites can be increased by external negative capacitance and resistance circuit. The absorption coefficient of 1-3 piezoelectric composites layer in low frequency and wide band range can be improved by piezoelectric shunt damping technology.

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness $(t_{FE})$ plays in Negative Capacitance (N C) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of $t_{FE}$ on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., $I_{ON}, SS, I_{ON}/I_{OFF}$ and $C_{gg})$ by varying $t_{FE}$ up to the maximum level at which hysteresis in the I- V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum $t_{FE}$ . We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. Finally, when it comes to circuit's performance, we demonstrate how the considerable increase in the gate's capacitance due to FE seriously degrades the circuit's performance imposing further constraints limiting the maximum $t_{FE}$ . All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are jointly optimized.