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The widely used LED lighting driver is series resonant (SR) converter or parallel resonant (PR) converter, which has a simple and understandable topology. The efficiency of conventional LED lighting in the market is around 90% to 92%. In this dissertation, an improved design with high efficiency reaching up to 97% to 98% based on traditional topology is proposed. Gallium Nitride (GaN) devices instead of standard MOSFETs are used in this novel design, in order to achieve a higher frequency operation up to 1 MHz with less performance loss for the switched mode power supply design. Additionally, magnetic size is reduced significantly by operating the converter at higher frequencies, which is better for applications in very limited space with small form factors. However, hard switching is no longer able to achieve satisfied performance under high frequency operation, hence soft switching is applied in the circuit design instead. This thesis details the design of a digitally controlled and credit card size LED lighting driver. This LED converter is converting from 380 VDC to 300 VDC to drive the new outdoor lighting with high efficiency, designed to work for constant current output (500 mADC) for LED lighting for commercial applications using GaN devices. The LED driver will also feature DALI communication protocol for remote monitoring and control. Master of Science (Electronics)

The technology for obtaining information from big data has broad application prospects. Among them, the information contained in the text is direct and efficient, furthermore the digitizing of the text information is of great significance for improving capabilities of both the multimedia retrieval and scene understanding. Recently, the identification of document text is mature. But the recognition of text in images, especially in natural scene images, which is important and challenging, is still in the stage of research and exploration. Because when dealing with natural scene images, even if using deep neural network models, we still have problems. The reason is that the overall performance of the network depends on the interaction of multiple stages. So that we want to propose a simple, effective and fast network for text detection. This dissertation explores the transition from object recognition to text recognition and the development of natural scene text recognition. A brief review of the principles, structure and design of the deep learning method of text detection, namely the convolutional neural network method. Then we present a simple and useful network that produces fast and accurate text detection in natural scene images. The network can directly predict words or lines of text in any direction and quadrilateral shape in the image, eliminating unnecessary steps. From the experimental results, we can see the accuracy and efficiency of the algorithm, and then propose an improved method in the dissertation. Using the improved method, the calculation speed is improved, the work efficiency is improved, while the accuracy of the text detection result is maintained. By analyzing the experimental results, we confirmed that this is a useful algorithm. Finally, the conclusion and recommendations about the further research will be given. Master of Science (Electronics)

Spiking neural network (SNN), largely inspired by a biological neural network, offers many advantages over the conventional deep neural network (DNN) [1]/ convolutional neural network (CNN) [2] in energy efficiency and latency due to its event based processing, which makes it a good candidate for energy efficient voice classification. Furthermore, the learning mechanism of the SNN typically requires only local information of pre-synaptic neuron and post-synaptic neuron when a spike happens, providing a light-weighted energy-efficient and hardware-friendly solution for the applications of voice recognition and classification. This dissertation reports a digital spiking neuron based on Leaky Integrate-and-Fire (LIF) model [3]. As the basic units of neurons in SNN, several LIF models jointly construct a 3-layer neural network. Subsequently, eight Infinite Impulse Response (IIR) digital filters ranging from 0 Hz to 400 Hz are designed to analyze human voice in both time and frequency domains, which extracts the feature of male and female voices. Two thousands male and female voice clips are used as training sets and five hundred voices are used as test sets in the neural network. The functionality and performance of the proposed digital spiking neuron can be verified by test sets to recognize male and female voice. The obtained results and simulations in MATLAB demonstrate the superiority of the proposed SNN and determine the potential of such systems in voice classification. Master of Science (Electronics)

The focus of this dissertation is to investigate on know how to trim and calibrate Global Navigation Satellite Systems (GNSS) receiver chain of a cellular phone for efficient characterisation. Trimming and calibration is performed on Phase-Locked Loop (PLL), Analog to Digital converter (ADC), Local Oscillator (LO) and Low-Dropout (LDO) Voltage Regulator blocks in the receiver chain. Additionally, resistors and capacitors are also trimmed to improve the performance of the Trans Impedance Amplifier (TIA). A detailed study is carried out in literature survey to explore the existing methods to trim and calibrate the above-mentioned blocks and components in the Radio Frequency (RF) receiver chain. Phase-Locked Loop (PLL) and Analog to Digital Converter (ADC) calibration is done in an automatic manner by using digital trim techniques and auto calibration units upon board power on. Resistor, Local Oscillator (LO) and Low-Dropout (LDO) Voltage Regulator calibration are done manually by enabling and writing the corresponding trim registers installed in the chip after board power on. With technology scaling, design of analog devices has become more complex as it depends on balancing many parameters. Post-production performance calibration is used to balance the parameters. Tuning knobs are added across various blocks in an analog circuit at the design stage to mitigate variations after production. Tests are carried out in Automatic Test Equipment to quantify variations in the performance specifications and these variations are fused in to a non-volatile memory embedded in the chip. The applications of these variations during bench validation is called trimming and calibration. The bench validation process starts with trimming and calibration before actual validation is carried out to achieve improved accuracy. Once the chips arrive from production, they are powered on to read the trim codes from the memory. This procedure is carried out across Typical, Fast and Slow corners. Once the trim codes are read the best code is selected for optimised performance for every design block. In this dissertation I will be discussing the trimming and calibration procedure for Resistor, Capacitor, Phase-Locked loop (PLL), Local Oscillator (LO), Low-Dropout (LDO) and Voltage Regulators. Master of Science (Integrated Circuit Design)

With economic globalization and the rapid development of the Internet, the connections between different countries and languages have become closer and closer, which sharply increase people's demand for cross-language communication. Traditional human translation which has many weaknesses cannot meet the needs of a wide range of translations. Artificial intelligence technology has been applied, Machine translation technology is an effective way to realize automatic translation and solve the increasingly common cross-language communication. The statistic machine translation can previously satisfy the minimum requirement of translation, but it requires many improvements. The work of this dissertation is to explore possible application of deep neural network and combine the current popular Recurrent Neural Network (RNN) system to achieve high performance machine translation. After comparing the advantages and disadvantages of different improvement models for RNN, Long Short-Term Memory (LSTM) [27] which is a more complete experimental algorithm model for the encoding and decoding process is engaged in this dissertation. Two kinds of Neural Machine Translation (NMT) models are available, the classical NMT model with greedy decoding, and the NMT model with attention mechanism [32], both were reviewed and explored in this study. Following which the BLEU i evaluation method is used to index the performance of two models, and the results obtained verify that the NMT model with attention mechanism has 1.9 BLEU value higher than the greedy decoding NMT model in training, and 2.3 BLEU value higher than the greedy decoding NMT model in testing, which directly proves the NMT model of the attention mechanism is improved for the performance of neural machine translation. The translation results have also been compared in three different size of sentences, from which conclusions can be got that normal NMT does well in short sentences only, but lose its power in middle and long sentences, while NMT model with attention mechanism act nicely in all three types of sentences. Whereas, some problems occur like excessive translation, which needs future exploration. Master of Science (Electronics)

With the popularity of the Internet, more and more businesses and transactions rely on the network to complete, and at the same time, anomaly attacks against various network applications are becoming more and more frequent. How to detect and identify various network anomalies has become an unavoidable technical issue. The network attack methods emerge in an endless stream, and the attack methods are constantly updated, making the traditional security mechanisms such as firewalls difficult to detect for many attacks. As an effective defense technology, intrusion detection technology makes up for the shortcomings of traditional security technology and has been concerned by researchers at home and abroad. With the continuous expansion of network scale, the continuous growth of network traffic and the continuous development of hacker technologies, higher requirements are placed on the performance of network anomaly detection. This thesis designs an anomaly attack detection based on self-organizing mapping algorithm to improve the accuracy of anomaly detection technology. Through the unsupervised machine learning method, the daily data of the transportation system is clustered and a training model is established. Finally, abnormal attack detection is performed according to the clustering model. Master of Science (Electronics)

The brain wave signal is derived from the synaptic potential caused by the synchronization of many neurons, reflecting the electrophysiological activity of brain neurons, which carries a large amount of biological information. The information contained in EEG has important research and application value, especially it can provide an important basis for clinical diagnosis and treatment. However, it is not easy to detect EEG signal. The EEG signal is very weak, generally only about 50 μV, and the amplitude range is 5 μV~100 µV. EEG signal scalp and skull usually have a resistance of several thousand ohms, so the front part has a high input impedance. The frequency, generally 0.1~100 Hz, of the EEG signal is low, and EEG signal acquisition in the normal environment is affected by common mode interference such as power frequency interference, since the signal-to-noise ratio is usually lower than -10 dB. Therefore, when we design the acquisition circuit, higher amplification gain, greater input impedance and low-pass filter are the required technical indexes. In general, EEG signal is enlarged by about 20,000 times, the input impedance is greater than 10 MΩ to improve the EEG signal acquisition ability. Besides, the amplifier in circuit is required to have a high common mode rejection ratio (CMRR), which is generally greater than 120 dB, because power frequency interference mainly exists in the form of common mode, and the amplitude is on the order of mV. To satisfy the requirements of EEG signal acquisition circuit, ICL7650 chip is employed in the design, since it has some good characteristics such as high gain, high CMRR, low offset and so on. After accessing information online, a suitable structure of the acquisition circuit based on ICL7650 is determined. Then to verify the function of each module in the circuit. We used Multisim to perform the simulation of circuit. According to the resulted waveforms, the circuit can execute the amplifying and filtering function normally. Master of Science (Electronics)

Neural network computing has attracted a lot of attention as it borrows the concept of human brain to achieve artificial intelligence (AI). AI has been used in many applications such as energy estimation and battery management in smart grid, and image/audio recognition in intelligent robots. The limitation of software-based neural network computing include low speed and high power consumption, making it difficult to be used in real-time and portable applications especially when the required accuracy is high. To address this issue, hardware based neural network computation have been investigated. However, the challenge is to map different neural network topologies to a hardware accelerator platform with fixed processing engine array in an efficient way so that the latency and energy consumption is minimized. Convolutional neural network (CNN) is highly complex. In this dissertation, optimal mapping of different neural network topologies to FPGA (Field-Programmable Gate Array) will be investigated. The main work is to study the neural network topologies, the processing engine array based on FPGA and a methodology to map a specific network topology to the platform. This will include the mapping of computation, data transfer and control part. The main optimization objects include latency and energy efficiency. Some research on training will be introduced, which can achieve by using software Matlab. Training process includes supervised and unsupervised learning. Another focus is the implementation of process engine architecture. Some architectures have been proposed and one preferred architecture was implemented on the hardware platform. In this project, one layer structure is achieved and simulation results by Vivado will be analysed. Master of Science (Electronics)

Diabetes diagnosis and condition surveillance are two main challenges in treatment of this disease. One of the methods is to use plantar pressure which will show different pattern according to different disease conditions of diabetes. One problem of this approach is identifying the activity of the patients since different activity may naturally result in various plantar pressures. This dissertation aims at solving this problem by using accelerometer data to recognize human body activities which include walking, jogging, jumping, going upstairs and going downstairs. Beginning with the preliminary data collection work, several approaches to process raw signals and classify different activities from the acceleration data recorded by accelerometers are proposed and tested by this dissertation, where PCA feature extraction method, time and frequency analysis, SVM classifier and RBF Neural Network are involved. Besides, a window segmentation method and the classification strategy based on small windows are introduced. By combining and doing experiments on these methods, PCA feature extraction method and SVM classifier are proven to have the best performances, which can achieve a classification accuracy up to 92%. While the time and frequency domain features, which has been applied by most of the existing works, show poor performances under the experiment environment in this dissertation. Master of Science (Computer Control and Automation)

With the rising prevalence of industrial Internet of Things (IoT) devices, it has become more important to ensure that IoT devices are secure. A method that attackers use to gain access to the IoT devices is to spoof themselves as the IoT server. Traditional authentication methods need a lot of memory resources, which is unable to meet the needs of lightweight IoT devices. The idea of the new authentication protocol is to use the historical data exchanged between an IoT device (verifier) and a server (prover) as a second authentication factor, in addition to the conventional factor of a shared secret key. The new authentication method needs more memory resources of server instead of IoT devices, which is what people want. However, the historical data authentication factor is considered a big dataset and the retrieve of selected pieces of data from a large data pool usually encounters long latency if the algorithm and implementation are not well optimized. To reduce latency, three methods are proposed in this dissertation. After presenting the new authentication method using historical data and optimizing it, a real system is implemented. Because the IoT devices are normally unable to verify the legality of the server, BeagleBone Black (BBB) (a kind of single board computer) is used to verify. Thus, the communication between the IoT device and BBB and between BBB and server are key problems. A structure named “bridge” is built and in order to insert verifier process, ip_queue in Linux is adopted. Thus, an optimized authentication process using historical data can be run in this system. Master of Science (Electronics)

Human behavior monitoring technology is widely used in medical rehabilitation, health care and human-computer interaction. Human activity recognition based on accelereometer is a new research field of human behavior monitoring. Compared to the human activity recognition method based on vision, it offers numerous advantages such as anti-interference ability, portability, data acquisition free, etc. However, the existing wearable human behavior monitoring system requires a large number of nodes, large power consumption, and poor endurance. Therefore, it is of great significance to design a new wearable human body activity monitoring device that is practical and convenient to use. This dissertation describes the human activity recognition and analysis based on the FPGA (Field Programmable Gate Array) Spartan-6 LX9 Microboard and ADXL345 three-axis accelerometer. In order to reduce the power consumption, MicroBlaze processor embedded in the FPGA Microboard is used to control the three-axis accelerometer. The ability to distinguish slow walking, normal walking and fast walking is dealt with using the proposed walking pattern recognition algorithm based on wavelet energy and IQR (Inter-Quartile Range). Analysis showed that the proposed extraction method can achieve an average recognition rate of 100%, which truly validate the proposed feature extraction method. A recognition algorithm based on standard deviation, skewness, kurtosis and correlation coefficients is also proposed to identity 5 walk pattems, i.e., standing, walking, running, going upstairs and going downstairs. By comparing the K-NN (K-Nearest-Neighbor) and SVM (Support Vector Machines) classifier models, it was found that when using SVM for classification, the behavior recognition rate of standing, walking, running can reached 100%. In other words, human behavior recognition based on three-axis accelerometer is an important research field of activity recognition. It has wide application prospect for wearable human body detection device. Master of Science (Electronics)

With the rapid development of Artificial Intelligence, the Autonomous Vehicle Technology has gained a huge amount of attention. However. it is extremely time-consuming and of high-cost to design, develop, manufacture and test the actual autonomous vehicle in real world. A proper simulation for autonomous vehicle based on physical simulation engine, such as gazebo, which allows match the actual situation and checking of performance before the actual production and manufacturing of the real autonomous vehicle. In this dissertation, the main target was to build a 3D model in a virtual environment based on Gazebo for the target autonomous bus, where several simulated sensors such as Lidar, sonar, camera, Global Position System and Inertial Measurement Unit for sensing object's acceleration velocity will be added to the intended 3D bus model to capture real-time that are generated by simulated sensors. Meanwhile, the Robot Operating System (ROS) will be applied to add the ROS nodes to the 3D bus model for the further data visualization based on 3D visualizer, such as Rviz, and communication between these corresponding nodes of sensors. Lastly. Based on the existing drawbacks of communication mechanism in ROS, a corresponding method has been proposed to improve this defect. Besides, the general simulation performance for this 3D autonomous bus model based on Gazebo and ROS will be analyzed. Master of Science (Electronics)

In recent years, CMOS-based conventional memory technologies including SRAM, DRAM, and Flash memories have become system performance bottleneck due to the speed gap between memory and logic, where they consume a large portion of power within systems, and not only that, they will soon face technology and economic issues as CMOS scaling approaches the fundamental limit. Emerging Non-Volatile Memory (NVM) technologies such as Magnetic RAM (MRAM) and Resistive RAM (RRAM) are recognized as promising candidatures for next-generation memory systems owing to several appealing properties: non-volatile, high density and scalability, fast speed, universal adaptability and multiple-bit capacity. In addition to be memory storage, NVM also offers many unique applications based on its physical properties. In this dissertation, the author has reviewed two typical NVM technologies, including MRAM and RRAM, and their related applications. The MRAM is thereby selected as a case study to explore security application, i.e., Physical Unclonable Function (PUF) circuit design. A modified MRAM model is established by Verilog-A and the MRAM model, which includes statistical distribution of physical parameters for Monte Carlo simulation that models the process variation of Magnetic Tunnel Junction (MTJ) in MRAM. By utilizing the mismatch variation of MTJ device for Internet of Things (IoT) hardware security application, a MRAM based PUF has been designed. Statistical data are generated using the Cadence Measurement Description Language (MDL) with Spectre simulator to perform mixedlanguage Monte Carlo simulation. A dual-mode MRAM architecture, including MRAM arrays and sense amplifier (SA), has also been studied and explored to implement functions of both memory and PUF. The simulation calculated are based on 65 nm CMOS technology and 45 nm radius MTJ. Master of Science (Electronics)

The Internet of things (IoT) is the networked interconnection of every object to provide intelligent service and improve economy benefit. The potential of IoT and its ubiquitous computation reality are staggering, but limited by many technical challenges. One challenge is to have a real-time response to the dynamic ambient change. Machine learning accelerator on IoT edge devices is one potential solution since a centralized system suffers long latency of processing in the back end. However, IoT edge devices are resource-constrained and machine learning algorithms are computational intensive. Therefore, optimized machine learning algorithms, such as compact machine learning for less memory usage on IoT devices, is greatly needed. In this thesis, we explore the development of fast and compact machine learning accelerators by developing least-squares solver, tensor-solver and distributed-solver. Moreover, applications such as energy management system using such machine learning solver on IoT devices are also investigated. From the fast machine learning perspective, the target is to perform fast learning on the neural network. This thesis proposes a least-squares-solver for single hidden layer neural network. Furthermore, this thesis explores the CMOS FPGA based hardware accelerator and RRAM based hardware accelerator. From the compact machine learning perspective, this thesis proposes a tensor-solver for deep neural network compression with consideration of the accuracy. A layer-wise training of tensorized neural network (TNN) has been proposed to formulate multilayer neural network such that the weight matrix can be significantly compressed during training. From the large scaled IoT networks perspective, this thesis proposes a distributed-solver on IoT devices. Furthermore, this thesis proposes a distributed neural network and sequential learning on the smart gateways for indoor positioning, energy management and IoT network security in IoT systems. Doctor of Philosophy (EEE)

With the growing focuses on fitness and Neuromuscular diseases, a type of biomedical devices which can monitor skeletal muscle contraction have become more and more popular. The muscle action potential which can be generated across Sarcolemma is a crucial parameter to help doctors to monitor the muscle contraction and classify Neuromuscular diseases for their patients. The muscle action potential can also help fitness coach to know whether a trainer is using a right muscle. A wireless skeletal muscle contraction monitoring device includes: ① a front-stage acquiring circuit, which can extract the electromyography(EMG) signal from muscle through surface electrodes, ②a wireless communication circuit, which is a Bluetooth module names HC05, ③a Analog to Digital Converter (ADC) circuit which is implemented by msp430 micro controller from Texas Instrument, ④ a signal receiving and processing software – LabVIEW software in Personal Computer which can receive sample data of sEMG signal from the device via Bluetooth communication. This dissertation focused on the wireless communication circuit design, ADC circuit design and LabVIEW software design. In order to detect the muscle contraction, two sensor channels were used by using two electrodes. The data sampled by the front-stage acquiring circuit is converted to a serial digital signal. So a msp430 micro controller which has an ADC function is used. For wireless communication between laptop and the monitoring device, a Bluetooth module is combined with the device. In the meantime, simulation and testing on the front-stage acquiring circuit were carried out to verify the function. Lastly, in this stage of the project, a LabVIEW software is designed to receive the signal data from the monitoring device and to derive the electromyogram waveform for future analysis. The performance of the system is investigated by experiments and tests. Different amplitudes of sEMG waveform represent different muscle movement. Master of Science (Electronics)

Human medical data collection system, especially patient monitoring system is always a challenge for designers. The system should be able to extract weak electric signal from strong common-mode voltage and noise. Besides, conventional electroencephalogram (EEG) monitoring systems are usually bulky, expensive and power hungry, which is not convenient for family use. Therefore, in this project, a portable wireless monitoring device with high common-mode rejection ratio (CMRR) analog-end and high digital resolution is designed. The device mainly contains two parts: the front-end (i.e. analog part) and the back-end (i.e. digital part). The analog part is made up of high CMRR amplifiers, precision operational amplifier and low-pass filter; the digital part mainly assembles the Analog-to-Digital Converter (ADC) and Bluetooth transmission module. The analog electric signal from electrodes can be amplified about 600 times by amplifiers, then the bandwidth is filtered to range 20 – 500 Hz. After being biased, the signal is sampled and converted by SAR ADC and then sent to PC or mobile equipment through Bluetooth module. Finally, the signal received will be observed and analyzed on LabVIEW. The performance of the entire system has been tested by amounts of simulations and analyses from design-stage to testing-stage. The experimental results show that the EEG signal can be detected and processed accurately by this wireless EEG monitoring system. Besides, the device can also be used to detect electrocardiogram (ECG) and electromyogram (EMG) signal. Master of Science (Electronics)

Wireless power transfer (WPT) is a potential technology that enables transmission of electrical power without the necessity of electrical contact. WPT can be employed in a wide variety of applications and this can be achieved due to WPT’s inherent advantages over its wired counterpart. These advantages enable WPT to eliminate numerous drawbacks faced by its wired counterpart. However, even with much research interest in this technology, WPT still need to overcome numerous technical challenges before it can truly be ubiquitous in the modern connected world. This thesis has proposed several approaches to improve WPT’s performance in terms of efficiency, transferred power, etcetera. In addition, a novel control scheme for dynamic WPT (D-WPT) systems without needing external sensors, and this helps solve some complexity and implementation issues of a D-WPT system. WPT systems use inductive coils and its electromagnetic coupling to transfer power wirelessly without electrical contact. These loosely coupled inductive coils are powered by high frequency power sources and cause large leakage inductances and input impedances. By employing compensating capacitors and electromagnetic resonance operation, the input impedance and VA (volt-ampere) rating of the WPT system can be significantly reduced, leading to an increase in the performance in terms of efficiency and power transfer, as well as transfer gap distance. However, there are many different types of compensation circuits available for WPT systems and these compensation circuits perform differently under varied conditions. The thesis dwelled into the circuit analyses on the various compensation circuits and derives the efficiency optimal operating frequencies these WPT systems. Using the optimized operating frequency, the efficiency analysis of these compensation circuits are detailed. Resonant frequency responses of the compensation circuits are used to further differentiate. With these analyses, the efficiency orientated design flow chart for selecting the optimized compensation circuit is derived with consideration for efficiency, load resistances, transferred power, transconductance and voltage gain. Experimental results also verified the usefulness of the flow chart and its respective analyses, which showed efficiency discrepancy of 28% (highest at 500 Ω) equivalent output resistance when comparing between compensation circuits. The LCC compensation circuit is also analyzed and its frequency bifurcation effect is investigated to be significantly mitigated. The LCC compensation circuit also shows significantly higher transferred power and lower harmonic distortion. The concept of Dynamic WPT (D-WPT) is to allow the receiver (Rx) to move freely while receiving power from the D-WPT system wirelessly. The thesis proposes a novel control scheme for the purpose of individual magnetic coupler control using the sensed transient response of the magnetic coupler’s input current. This would improve the D-WPT system’s efficiency, while circumventing the necessity for external positional sensors or auxiliary circuitry. The proposed control algorithm yielded a low standby power to operating power percentage of 7.2% as compared to 44.2% found in existing literatures. Thus, the proposed control algorithm for D-WPT system could be a promising approach to reduce D-WPT system complexity, improve power consumption and EMI/EMC performances during standby mode, as well as power transfer efficiency levels. Doctor of Philosophy (IGS)

Distributed Denial of Service (DDoS) attack has become one of the major threat to current Internet. The attacker firstly gains the control of a large number of hosts. Then by controlling these hosts to send illegal packets to the victim simultaneously, the attacker can easily exhaust the bandwidth or computing resource of the victim. DDoS attack mitigating approaches that apply pre-established defending strategy, functionality or capacity, and guard at fixed locations are costly and not effective. Software Defined Network (SDN) is a new network architecture in which the data plane and the control plane are decoupled. In SDN, the data forwarding function is achieved by using general devices while the control function is implemented by software. Network Function Virtualization (NFV) supports the flexibility in on-demand function instantiation and allocation, and recently finds its applications in handling DDoS attacks. In this dissertation, NFV/SDN is applied into DDoS mitigation. In the framework, network traffic is monitored and analyzed utilizing the SDN features of central control and global network view, and the detection of anomaly traffic will trigger the actions of SDN controller. In this dissertaion we build up an SND environment and demonstrate a DDoS attack on a network topology. By doing simulation experiment, see how we can mitigate it using SDN in real-time. It is shown that the SDN controller can identify the DDoS attackers and disconnect them from the network to prevent any further damages to the network. Master of Science (Electronics)

With the rapid advancement of science and technology, IoT networks have gradually grown to larger scales. In the recent years, overall structure of IoT network has become more complex, and the abnormal behavior of networks has also become increasingly complicated. In order to better improve the effectiveness of the IoT network to prevent anomalies, it is necessary to accurately study and analyse the abnormal behavior of network when anomalous behavior occurs, as well to solve and prevent the anomalies that exist in the network, thereby reducing their impact. This dissertation focused on the detection of abnormality with Wireshark and packet analysis system. An alert system also be developed to make an alert when abnormality happens. In order to be more suitable for IoT network, some IoT data is collected and analysed. From the data obtained, the network features can be used to detect the abnormality. Wireshark which is a freeware is then used to evaluate some conclusions about network packets. To improve efficiency and to reduce time delay, the packet analysis system is introduced to receive the network flow and to analyse data in real time. This will do away with human intervention to allow system automation. After detecting the abnormality of the IoT network, an alert system needs to inform the person in charge to resolve the problem. The system can play the alert music, pop up an alert window and print the alert information on the screen. With the conclusion of data analysis, the trust list can be set up to ease further development. With the two detection methods (the Wireshark detection and the packet analysis system) and the alert system, the IoT network abnormality will be detected easily and resolved timely. Master of Science (Electronics)

In sensing systems, ADCs are widely used in sensor interface circuits to convert analog signals to digital signals. Many of the sensing systems require ultra-low power consumption because of their limited power budget. Therefore, the design of ultra-low power ADC that meets the intended performance is a key design challenge for low power sensing applications, such as in healthcare monitoring (e.g., ECG, EEG, neural signal, etc.) and environment monitoring. Besides, a moderate sampling frequency and resolution can meet the requirement of these sensing applications. Compared to Flash ADC, Pipelined ADC and Delta-Sigma ADC, SAR ADC provides a good compromise among energy efficiency, sampling frequency and conversion accuracy for these sensing applications. In this thesis, SAR ADC is chosen as the main architecture to develop low power SAR ADC and four different designs of SAR ADC are proposed. The first version SAR ADC consists mainly of clock boosting circuit, a subtraction and an addition capacitor array, a time-domain comparator, switching logic, output latches, level shifters and some buffers. To achieve ultra-low power, the proposed ADC operates at 0.5 V, deploying a single-ended structure and top plate sampling technique. In order to improve the linearity of the sampling circuit at ultra-low supply voltage, clock boosting circuit with gate signal swinging from 0 to 2VDD is proposed. A non-binary redundant algorithm is applied to correct the inevitable decision errors in the first few conversion steps. From the chip measurement results, it consumes only 16-nW of power and achieves a SNDR of 50.4 dB, which is equivalent to an 8.08 ENOB, with 1 kS/s sampling rate at 0.5-V supply voltage. The second version SAR ADC was designed to optimize on power efficiency, for sparse signals such as the neural spike. Sparse signals have slow varying or flat characteristic across most of the duty cycle, such that the MSBs are the same if variation between two consecutive samples is small. A novel ADC deploying M-bit ADC, N-bit DAC to realize (M+N-3) bits ADC while reducing the power consumption and area is designed. The adaptive sampling scheme has also been adopted to allow selection of either a higher or lower sampling rate in event of sharp and gradual transitions, respectively. Adaptive sampling not only ensures no overflow of input signal to the M-bit ADC but can further reduce the power consumption. This 8-bit SAR ADC consists mainly of a slope detector, 6-bit ADC capacitor array, 5-bit DAC capacitor array, switching logic, dynamic comparator, latches and 8-bit full adder. The measurement results show that it can realize a SNDR of 45.7 dB, which is equivalent to a 7.3 ENOB, with 125 kS/s sampling rate at 1-V supply voltage. When the input signals are neural spikes, the total power consumption of the proposed ADC (at 2 kHz and 20 kHz sampling rates) is able to save about 88% power compared to the conventional ADC (operating at 20 kHz sampling rate). The third version SAR ADC was designed to optimize on power efficiency in terms of system. A reference-voltage regulator-free SAR ADC with self-timed pre-charging for wireless-powered implantable medical devices was designed. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the power-hungry reference-voltage regulator and the area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Furthermore, with internally generated sampling clock and asynchronous SAR logics, this SAR ADC can operate at a fully asynchronous mode without any external clock source. Fabricated in the 0.18-µm CMOS technology, the proposed SAR ADC achieves a SNDR of 53.32 dB at 0.8 V with 50 mVpp supply voltage fluctuation, while consuming a total power of 2.72 µW at 300 kS/s sampling rate. The total FOM is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm2. The fourth design is a wide input 12-bit SAR ADC with low power and fast convergence digital background calibration. This SAR ADC is able to convert input signal with a range of 0~4.8 V, operating at 1.2-V supply. By omitting the calibration of 3 LSBs’ weights, the number of multipliers or product is reduced to lower the power consumption. Besides, in order to accelerate the convergence of digital background calibration, 10 LSB offset is injected to the first 10000 samples, followed by 15 LSB offset. The ADC is designed and simulated with a 65 nm CMOS technology, and the digital background is implemented in Matlab. With background calibration, the SNDR of the ADC is improved from 59.6 dB to 65.3 dB, operating at 500 kS/s. and power consumption is 8.39 µW. Doctor of Philosophy (EEE)

Recent years, with the development of Convolution Neural Networks (CNN), machine learning has achieved great success in many areas such as speech recognition, vision classifications, face recognition and other kinds of pattern recognitions. In general, CNN is a kind of deep learning, which imitates the way human beings process the signal from nature. The algorithm of CNN mainly includes two parts: multiplication and summation, which is also called a convolution layer. Multiple convolution layers are involved to implement the whole CNN, on each layer, the raw data or the result from the former layer is used to do convolution with the filter of which the factors are gained from the software training. After several layers processing, the final output signal justifies the samples like the voice or images and give people a feedback or send an instruction to other systems. Traditional CNNs usually operate on Central Processing Unit (CPU) or Graphics Processing Unit (GPU); however, as the functions become more and more complex and requirements of performance including power consumption and speed are increasingly high, a new way to realise it on Field-Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC) appeared. It also indicates that CNN is going to be more portable in the future. This dissertation is to provide a general used accelerator of CNN on FPGA; meanwhile a new structure is proposed to balance the performance and the usage of the resources. This work operates on an evaluation board ZYNQ-7 ZC702 of Xilinx. A CNN structure is mapped on the FPGA device, the Acorn RISC Machine (ARM) core is used to control the camera to capture the images and the data flow in this whole system. Master of Science (Electronics)

Most people with diabetes suffer from diabetic foot ulcers and requires amputation if the condition becomes serious. Foot pressure measurement devices can help patients monitor their foot pressure at any time, sending alert to patients when their foot pressure is high. This allows patients to change their behavior to reduce the foot pressure. There are many foot pressure measurement devices, however, the device size of the existing product is large. In this project, a sensor interface system is designed to measure the foot pressure. This sensor interface system consists mainly of a multi-channel Wheatstone bridge, operational amplifier, analog-to-digital converter, multiplexer and voltage regulator. The multi-channel Wheatstone bridge is used to measure the resistance change of the sensors through the measure of the output voltage change of the bridge. The operational amplifier is used to amplify the output voltage of the multi-channel Wheatstone bridge to meet the voltage requirement of the analog-to-digital converter (ADC). The FPGA from digital part determines which sensors are connected to the circuit by controlling the multiplexer. A voltage regulator can supply a stable power to avoid voltage fluctuation using a supply voltage of 3.3V, thus, the power consumption of the sensor interface system is reduced. A PCB has been fabricated to verify the design. The size and performance of this sensor interface system are optimized. Through the PCB testing, the relationship between the sensor resistance and output voltage of the operational amplifier is obtained. The testing results verify that the sensor interface system developed can accurately measure the resistance change of the sensor. Besides, this sensor interface system is connected to the FPGA to control the multiplexer for acquisition of data. Master of Science (Electronics)

A Skeletal Muscle Contraction Monitoring Device that used in sports training is realized through detecting and processing the Surface Electromyography (sEMG) signal in this project. The device is made of: ①a front-stage acquiring circuit, which receives the sEMG signal via surface electrodes,②a processing software – LabVIEW that acquire the sample data of sEMG signal from National Instruments PXI-4462 card used as Analog-to-Digital Converter (ADC). Between the electromyography (EMG) signal and the ultrasonic sensor, the former is chosen for implement to monitor muscle contraction due to its low cost and feasibility. Thereafter, the non-invasive surface EMG electrodes are selected for convenience to use as compared with the invasive needle electrodes. The front-stage acquiring circuit, with common-mode rejection amplifier, precision operational amplifier, high-pass filter and 2-stages low-pass filter, is designed to amplify the sEMG signal by around 600 times and filter it to a bandwidth that is between 20 to 500 Hz, approximately. After hardware circuit processing, the amplified and filtered sEMG signal is converted to digital signal through ADC (NI PXI-4462) and analyzed by LabVIEW to obtain its features for further analysis. The performance of device’s characteristics is investigated by numerous simulations and experiments. And, the results show that a rough sEMG signal acquired from human skin can be detected and observed after amplified and filtered through front-stage circuit. Additionally, the features of sEMG signal are clearly presented in the analyzed results after converted to digital signal and processed by LabVIEW. Experiments and tests were conducted to validate the ability of this device to monitor muscle contractions. Different amplitudes of sEMG represent different muscle movements of human body. Other features of sEMG signal are also analyzed for further application in the area of kinesics and clinical medicine. Master of Science (Electronics)

With the growing focuses on the diabetic foot ulceration, corresponding biomedical devices have become more and more popular. The plantar pressure is a crucial parameter to help patients monitor the walking posture for themselves. A smart sock plantar pressure measurement system was proposed which included pressure sampling circuit, signal processing system and communication with mobile devices. This dissertation focused on the signal processing system design. In order to sample more accurate data, multi sensor channels were designed, which needed a switching control in a fixed frequency. Consequently, a Verilog code for switching control was created. In the meantime, simulation and test with PCB were operated to verify the function. Likewise, the data sampled by the circuit needed to be converted to the digital signal in serial. So an ADC with embedded SPI was used. The Verilog code for SPI control was created. In the meantime, simulation and test with the front-end circuit were operated to verify the function. Lastly, in this stage of the project, a wired communication design was done. The FPGA with UART-USB bridge was used and the Verilog code of UART transmitter was applied. Simulation and test with PC were finished to verify the function. In the future work, a wireless communication will be adopted like Bluetooth. And the error analysis will be further realized to acquire more accurate data. Furthermore, more complex data analysis will be performed to provide users more sufficient pressure information. Master of Science (Electronics)

The advancement in sensing materials has led to the growth of the sensing technologies in flexible and wearable medical applications, especially the pulse and blood pressure monitoring. These technologies offer many key advantages and hence their popularity in recent years. In this dissertation, the author has reviewed three typical sensing technologies, including piezoelectric sensing, capacitive sensing and piezoresistive sensing. The operation principle and pros / cons of the technologies are investigated. Piezoelectric sensing is selected to be used in this project, after a comparison of the sensing performance. A commercial sensor is consisting of a sensor device and an interface circuit, and the key component of the readout circuit is the op amp. In this project, the author contributes to the transistor-level circuit design for op amp. The op-amp design phase includes hand calculations of the op-amp parameters followed by simulations using Cadence tools. Followed by a proper design procedure, a series of parameters are achieved: open-loop gain is over 1700, slew rate is more than 8 V/μs and input offset voltage is about 720 μV. A noise model of the op amp is also analyzed, and some approaches to reduce noise are proposed. Next, the author’s work focuses on the piezoelectric pressure sensor; two conditioning modes had been evaluated; the voltage mode configuration is then selected for the interface circuit design. Apart from transistor-level circuit design stated previously, a board-level circuit design for sensor interface circuit is also conducted. In the board-level circuit design, board-level simulations and system simulations are conducted to ensure the closed-loop circuit works well. A discreet hardware PCB is built and measurement test is carried out. The measured results match with the simulation results, hence the performance of the circuit is functionally proven. Master of Science (Electronics)

The high performance radio-frequency/millimetre-wave filters are highly demanded for modern wireless communication and radar systems. General requirements for high-performance RF filters are low insertion-loss, small form-factor, sharp selectivity, and low manufacturing cost. In the past, substrate integrated waveguide (SIW) has been proven to be effective in integrating planar and non-planar circuits together based on a standard printed circuit board (PCB) to reduce system cost. Inheriting the properties of conventional waveguide, SIW also has good characteristics of low insertion loss, high quality-factor and high power handling capability but with drawback of relative larger circuit size. Meanwhile, defected ground structure (DGS) is an artificial defect on the ground plane. Two unique capabilities of DGS make it a promising solution for filter designs: 1. Prohibiting wave propagation at desired frequencies, namely the stopband property to improve filter selectivity; 2. Slowwave effect for circuit miniaturization applications. This work mainly focuses on the fundamental theory and study of DGS, and its applications to conventional microstrip and SIW filter designs. Several novel DGS structures are proposed and used for high performance miniaturized filter designs. Firstly, a new dual-T DGS is proposed to extend LPF stopband rejection. The DGS is proposed and etched on the ground plane of the transformed radial stub to form a high-performance LPF with wide stopband rejection. Secondly, a new DGS is co-designed with SIR to form a new asynchronously tuned resonator. It is formed by mixed coupled stepped impedance resonator (SIR) and coplanar waveguide SIR (CPW-SIR) is proposed, analyzed, and applied to the 2.4-/5.2-GHz dual-band filter designs. The CPW-SIR is created using DGS on the ground plane. Fractional bandwidth (FBW) design graph is constructed for the dual-band filter synthesis. Two filter prototypes (first-order and fourth-order) are fabricated and measured, which validate our design theory. Thirdly, new DGS structures are developed that form resonators when loaded on SIW technology. A novel back-to-back E-shaped defected ground structure (DGS) for miniaturized dual-band substrate integrated waveguide (SIW) bandpass filter designs is proposed. The SIW loaded by novel DGS supports evanescent-mode wave propagation below the cut-off frequency of SIW, while achieves two transmission poles at the passband and two controllable transmission zero points. Furthermore, the novel loading scheme by loading different-sized DGS resonators on two sides of SIW is proposed for dual-band bandpass filter designs. Meanwhile, the balanced DGSs are investigated for mm-Wave filter applications. Doctor of Philosophy (EEE)

Sensor systems operating over wide temperature ranges are found in many applications such as the wireless sensor nodes, food/chemical analysis and automotive electronics. Silicon technologies have been employed in these areas to help reduce product cost and system volume. However, temperature dependences of both sensors and silicon circuits limit sensing accuracies and even fault on measurements in harsh environments. Such limitations have led researchers to identify new sensor technologies and also interface circuits that can operate and survive in high temperature and high pressure environment while still achieving fine accuracies. Progress in these technologies can very well change the practice of using bulky sensors for sensing automotive engines, industrial gas turbines, aircrafts and well-bore systems, such as the geothermal and oil and gas explorations. In the design of the abovementioned sensor systems, the temperature effects of the sensor devices, the clock reference, and interfacing circuits have significant influence on the sensing accuracies. Such temperature effects are widely found in the reference circuitries, the sensor devices, the readout circuits, etc. Thus, suitable temperature compensation techniques must be applied before the circuits can be used in rugged environments. The sensing accuracy and temperature coefficient are the two key factors for evaluating the efficiency of the temperature compensation techniques. Moreover, the stability of a circuit is another important factor to ensure system survival under various conditions. Consequently, the technique to minimize the temperature coefficient of the sensor is explored through device physics—a pressure sensor device based on acoustic wave microelectromechanical technology that depends on the temperature characteristics of both the Rayleigh wave and the Lamb wave is proposed in this research. An accurate model of the Lamb wave resonator is also developed to allow circuit simulations. An adaptive technique deployed in the resonator oscillator has helped provide stable oscillations to the different resonators, whereby different resonant sensors can use the same oscillator chip. The proposed method has greatly reduced the number of circuit designs and fabrication cycles since a traditional oscillator circuit is only suitable for resonators of the same features. A CMOS dual-mode oscillator using cascaded tuned-amplifier technique has been developed in this research, which presents superior stability. A constant biased varactor technique is proposed to compensate the frequency drift of a LC oscillator by directly nullifying the temperature coefficients of the LC-tank. The compensated temperature coefficient of the LC oscillator, implemented in standard 0.18-μm CMOS technology, outperformed the state-of-the-arts by tens of times. A combination of both the biased varactor temperature nullifying technique and the temperature coherent quantization technique enable the capacitive sensor readout to resist the temperature effects to enhance the accuracies. The proposed works will certainly add value to the silicon technologies in sensor applications across wide temperature ranges. Doctor of Philosophy (EEE)

Wireless power transfer is increasingly attractive to electronic products, especially for implantable devices. One of the challenges is to maintain maximum power transfer efficiency even in dynamic environment (distance, alignment and load). The application of magnetically resonant coupling technology can achieve strong coupling between two coils, where the coupling coefficient between two coils can reach 0.7-0.9 and hence high power transfer efficient is possible. However, the power transfer efficient suffers significantly with a slight impedance mismatch at both the transmitter and receiver in high quality factor (Q) system. This dissertation focuses on the matching network of the receiver where coupling coefficient of 0-0.9 is investigated. The impedance matching network using parallel capacitors with binary value is constructed. An improved auto-tuning algorithm is proposed based on the simulation result that the output voltage and matching capacitance present a parabolic relation. Following which, the algorithm is implemented into digital circuit using Verilog Hardware Description Language (HDL). Mixed-signal simulation (analog and digital circuit) shows that the optimum matching state can be tracked adaptively through the digital circuit. Additionally, a printed circuit board has been successfully designed and built to verify the auto-tuning function of the adaptive matching system in dynamic environment. Master of Science (Electronics)

With the development and optimization of switching power supply for the past few decades, analog control technology has become fairly mature. However, analog control method has its own inherent weaknesses, such as fixed compensation design, which limits the application in multiple occasions. Digital control technology has many unique advantages; such as reprogram ability, reprogram ability, unique noise immunity and so on. Due to these advantages, digital-dominated power management IC becomes the current developing trend. In this dissertation, research and design of digitally controlled DC-DC buck converter are conducted. Firstly, power stage design methodology has been reviewed in detail. Then, parameters of the power stage are calculated based on the specification. For the digital controller design, emulation digital design method has been used; proportional–integral–derivative (PID) control methodology is presented. After the analysis of the system closed loop model in Simulink, PID controller in s-domain is conducted. The controller can be transformed to z-domain directly and digital controller design is completed. Finally, digital intensive buck converter is modeled in Simulink. Master of Science (Electronics)

A normal pulse oximetry sensor require a patient to be wired to a monitor in hospital where a healthcare provider monitors readings continuously. This is a disadvantage to patients who do not necessarily need to be admitted in the hospital, but are in need for pulse oximetric data monitoring. Consider an example of a situation where a person who suffers from congestive heart failure, it is important for this type of patients to be monitored but however it is not always necessary for that patient to be admitted in the hospital. The healthcare industry has been working on all possible improvements and additions to the wired device and has provided alternative to the pulse oximetry sensors such as a mobile wrist watch design or wireless systems operating on the hospital network. A lot of improvement is needed [1]. The healthcare industry has been working on improvements and additions to the current pulse oximetry devices for daily-life use outside the hospital. A mobile wrist watch pulse oximeter design would be ideal for this purpose. However, there are a lot of challenges in developing this kind of wrist watch design such as removing background noise and cancelling moving artifact to improve signal quality and accuracy. In this dissertation, we will first study the conventional transmission pulse oximetry through investigating a design kit offered by Texas Instruments AFE4490SPO2EVM consisting of IC AFE4490 for pulse oximetry and microcontroller MSP430 to perform the back-end data processing and calculation. After this study a prototype reflective pulse oximeter is designed to eliminate the clamp sensor section paired with the kit, towards a chronic monitoring device which can be used in daily life of the patient outside the hospital. Master of Science (Electronics)

The Hard Disk Drive (HDD) industry has, in recent years, struggled with attempting to attain continual growth in storage capacity to meet the needs of a rapidly growing storage demand in the information age. Conventional Perpendicular Magnetic Recording (PMR) is already hitting its limit with areal density growth slowing down considerably in recent years. In moving towards higher densities, PMR faces the problem of simultaneously shrinking the size of bits and ensuring the media remains writable without compromising the thermal stability of its magnetic grains. To overcome this, various novel recording architectures have been proposed, namely Heat Assisted Magnetic Recording (HAMR), Bit Patterned Magnetic Recording (BPMR), Shingled Magnetic Recording (SMR) and Two-Dimensional Magnetic Recording (TDMR). HAMR overcomes the trilemma by injecting thermal energy into a high coercivity and thermally stable media (needed for high density) that would otherwise require an excessively strong head field to write. BPMR organizes magnetic grains into a defined lattice and stores bit on single grains known as islands. SMR targets for a higher track density by writing data tracks using a shingling technique. TDMR uses the same writing mechanism as in SMR. In TDMR however, information is read simultaneously from multiple tracks through the use multiple reader heads. To attain massive storage improvements in the near future, the industry needs to invent new ideas across the entire HDD platform. Development of new recording architectures, concurrent with the development of new trends in signal processing are essential in paving the way to new and intriguing prospects of significant performance gains. As such, the first part of the thesis focuses on a system level study of the recently proposed SMR and HAMR channel. The formulation and evaluation of theoretical models for these emerging recording technologies is essential in enabling an accurate prediction of its feasibility. Magnetic researchers often employ micromagnetic channel models for this purpose. Despite its high accuracy, the micromagnetic model is computationally slow in reproducing the magnetization of grains. This renders it unsuitable for error performance studies. The thesis proposes a Grain Flipping Probability (GFP) channel model as an alternative to the micromagnetic model. The GFP consists of a multi-dimensional look-up table (LUT) that is characterized from micromagnetic simulations. It is highly accurate and is able to reproduce grain magnetizations multiple times faster than the micromagnetic model. With the GFP channel model developed, a novel study of the feasibility of SMR and HAMR is carried out in this thesis from a system’s perspective. Developments of new magnetic recording channels can be synergized with advancements in signal processing techniques to bring about an impactful gain in storage capacity in the near future. The remaining part of the thesis therefore focuses on novel signal processing schemes for magnetic recording channels. The iterative detector-decoder is the standard used in today’s HDD. It comprises of a detector block and decoder block that aims to recover the stored information on a media through repetitive exchange of mutual information between the blocks. The detector operates on a trellis structure while the decoder operates on a factor graph. As the iterative detection-decoding scheme is sub-optimal, recent trend in signal processing research is inclined towards the area of joint detection and decoding where the detector and decoder are regarded as one entity that simultaneously detects and decodes the stored information. In this thesis, two novel joint detection/decoding techniques are proposed – 1) Joint Viterbi Detector Decoder (JVDD) 2) Joint Factor Graph Detector Decoder (JFGDD). The JVDD performs detection and decoding jointly in a single step over a channel trellis that consists of pre-defined parity check nodes. While JVDD has shown to perform well in the simulations carried out in this PhD work, its computational complexity can be a drawback in some circumstances. To manage this, novel error-correction codes coined the JVDD class of codes are proposed for the JVDD. The proposed JVDD codes are analytically optimized in this thesis so as to attain the best performance and lowest complexity for the JVDD. The proposed JFGDD scheme on the other hand, operates on a super factor graph structure that is constructed from a combination of a channel factor graph and a code factor graph. As the conventional detection algorithm is executed on a channel trellis, the thesis proposes an alternative implementation of the algorithm on a channel factor graph instead. The performance of the proposed JFGDD is susceptible to the presence of short cycles in its graph. As such, two novel methods of mitigating short cycles are proposed in this thesis. The first method proposes a non-binary adaptation of the algorithm that will minimize the number of connections and thus cycles in the factor graph. The second method proposes the design of constrained General Partial Response (GPR) targets. Advances in signal processing for HDD should be made not only in the area of detection and decoding but also in the area of equalization. As such, the last part of the thesis proposes novel 2D equalization schemes for SMR and TDMR. The shingling technique of writing data in an SMR or TDMR channel causes the read-back signal to be severely corrupted with inter-track interference (ITI) that arises as a result of the overlapping of adjacent tracks. On the contrary, ITI in the existing PMR channel is negligible and are often ignored. To advance SMR/TDMR as a viable future recording architecture for the industry, equalization techniques should be formulated to exploit the ITI present and enhance the reliability of SMR/TDMR channels. The thesis therefore proposes novel 2D equalization schemes to manage the ITI in both channels. DOCTOR OF PHILOSOPHY (EEE)

The onset of the mobile age and the rapid growth of the mobile technology have initiated a tremendous demand for high density storage and retrieval of huge amount of data. The conventional magnetic recording systems are expected to reach storage density limits. In the recent years, the non-volatile memory (NVM) systems have shown a high potential for future ultra-high density data storage systems. Compared with magnetic recording systems, the NVM systems have numerous attractive features, which include lower power consumption, faster read access time, better mechanical reliability, compactness and shock resistance. Flash memory is currently the most mature storage medium in portable electronic devices and is rapidly being introduced into mobile gadgets and data-intensive computer systems. Current semiconductor market researches has revealed that non-volatile memory devices based in flash technology will reach sales in the order of $26 billion by end of 2010 and $51.2 billion in 2015 [1]. Due to the maturity ofFlash technology, it is proposed to set the benchmark for other emerging NVM technologies. The trend of consumer electronics indicates that constant growing demand for an increase in data storage capacity. Examples are the megapixel race in consumer digital cameras. As an example, the Apple QuickTake 100 launched by Apple in 1994 contained an image sensor with only 0.3 megapixels [2], nowadays cameras like Sony, possess a sensor with a resolution 24.6 megapixels [3]. In the same trend, digital video systems have increased resolution due to the new high definition HD video standards. All these new technologies require a higher amount of storage capacity in order to accommodate their media content, as a result, an increment in the demand for higher capacity non-volatile memories is highly expected. The increasing market demand for high capacities non-volatile memory devices serves as a driving force to incentivize recent outgoing research in the non-volatile field. Nevertheless, the physical constraints of Flash makes additional scaling a tremendously expensive task, therefore we exploit alternative technology to break through what the Flash technology has to offer. The phase-change random access memory (PCRAM) is one of the most promising alternative technologies for NVM and is one of the promising candidates to replace Flash. It is envisage that Phase Change Memory (PCM) technology will eventually become a mainstream NVM technology. Hence development o f coding techniques for PCM is focused in this work. While the technological innovations in the design and development of storage media and system are key to achieving high capacity storage systems, the role of advanced coding techniques is increasingly becoming crucial as a cost-effective means of improving density. Despite the favoured position of NVM in the mobile sector, there are poor reliability concerns related to such memories. These poor reliability issues were contributed from resistance drift over time, cells that are stuck in a particular state and inter-cell coupling. This dissertation applies variants of data storage codes to combat some of these reliability issues. Specifically, the core of the work is focused on two sets of issues - asymmetric errors caused by a shift in the cell’s resistance over time and the failure contributed from the limitation of the maximum number of rewriting operations of a PCM cell. Write-once Memory (WOM)-codes were proposed as an efficient storage codes in extending the lifetime of PCM cells, by minimizing the number of memory degrading reset cycles. An efficient code construction method is briefly described before a critical criterion is proposed to design WOM-codes with high rates. From the WOM-rate analysis, the WOM-codes designed have an improvement of 2% for the unrestricted codes and 1% for the restricted codes. Subsequently, a novel construction method is proposed to achieve high rate non-binary WOM-codes that have a shorter codeword length compared to the best known WOM-codes. Achieving high WOM-rates with shorter codeword length is beneficial as coding efficiency is maximized with less complex encoding and decoding operations. A newly designed two-write 4-ary WOM-code, which is proposed in this work achieves an improvement in coding efficiency of O.2%. Next, the work is focused on proposing solutions to combat asymmetric errors. A novel scheme known as rank modulation (RM) was recently proposed for this purpose. As these codes are currently encoded and decoded based on a look-up table (LUT), a novel enumerative coding scheme is proposed. The enumerative coding scheme proposes to compute the lexicographic index analytically rather than adopting a brute-force enumeration technique. This results in a desirable reduction in encoding and decoding complexity. Additionally, a hybrid RM scheme is proposed with the motivation of providing a method of constructing WOM-codes without having to sacrifice as much code rate as the state-of-the-art RM codes, and yet able to provide better performance. DOCTOR OF PHILOSOPHY (EEE)

Video analysis has become a hot research topic recently due to its huge potential for application in intelligent monitoring for security and automatic control. Currently, most video analysis systems are implemented using software, which limits the speed and size of the system. In the near future, video analysis is likely to be integrated in camera for intelligent monitoring system. It is therefore worth exploring hardware solution for achieving small real-time video analysis systems. In this dissertation, we propose to achieve small real-time video analysis systems using FPGA-based hardware. During the project, the video analysis algorithms will be partitioned into software and hardware by considering its control complexity and internal parallelism. The algorithm parts with high control complexity will be partitioned in software for flexibility, while the parts with high parallelism will be partitioned into hardware for speed acceleration. Based on the partition, software and hardware cooptimization will be performed by modeling and simulation of the mixed system to reduce the complexity and improve the performance. After that, the proposed system will be implemented on FPGA where the hardware part is implemented using reconfigurable logic arrays, and the software part is implemented using hard DSP core in the FPGA. For the software to be implemented, we use the tool MATLAB. Master of Science

In today’s audio power amplifier industry, the Class-D amplifier is extremely prevalent concept because of its high power efficiency and small size. A typical Class-D amplifier is made of three stages: a pulse width (PWM) modulator stage, an output power stage and an inductor-capacitor (LC) low pass filter stage. With the development of digital signal processing and digital storage technology, the PWM modulator or feedback controller can be constructed using digital methods, to yield a fully digital Class-D amplifier. In this dissertation, an open-loop single-end Class-D power amplifier is first designed and simulated using Cadence simulation tool, and based on Global Foundries 0.18um CMOS technology. Then, a feedback digital Proportion Integration Differentiation (PID) controller is designed and simulated using MATLAB, to equip the designed Class-D amplifier so as to reduce the noise and to ensure stability of the circuit. In all, this dissertation proposed a novel Class-D amplifier with digital PID controller to drive an 8-Ohm speaker. The efficiency of this Class-D amplifier is high and the total harmonics distortion (THD) is less than 0.5% at 10 kHz. Master of Science (Computer Control and Automation)

This research is to create an effective GPS Projectile Vehicle Tracking System so that the police can use it to track suspect vehicles and speeding violators. The tracking system uses a GPS receiver to receive satellite signals, and then transfers the location information as SMS via mobile communication to an Android tablet. The Android tablet receives the SMS with location information and then shows the location in the Google map. In this dissertation, the tracking system is proposed for the police to fulfill the function of tracking the target vehicles. Also, it will be designed security and developed more functions to help police identify accurate location, improving police efficiency and catch more suspect and speeding vehicles. Master of Science (Electronics)

This dissertation introduces an Android app which is used for monitoring the sensor data. A sensor detects the gap of cylinder and the data will be sent to an Android embedded computer using Modbus protocol, to display on a 2D graph. The project will allow users to set the interval time to receive the gap sensor data. At any time, it can show the future gap trend on the 2D graph using the Least Square Method algorithm. When the gap value reaches 0.6 mm, it will generate both the alert message and voice. A sensor is used in this project to detect the distance variable and to provide a corresponding output, generally as an optical or electrical signal. Next, the signal is transformed into digital signal which can be analyzed and monitored easily. For the sake o f convenience, the data will be generated from a software. The hardware platform for data monitoring in this dissertation is the SONY L36H, 4.3 Android version. The software development environment is Android Studio, developed by Google Company. The simulated data is generated from Modbus Slave software, using TCP communication protocol. To achieve data conveying, both the devices have to be under the same network, namely, the same Wi-Fi, to get the same IP address. Master of Science (Electronics)

The implantable and body-worn bio-medical devices have been the focused applications in the wireless body area network. To prolong the lifetime of these devices, we expect the circuits to be energy efficient, hence minimum power consumption and also increase data rate. In this thesis, the design and simulation results of a novel frequency shift keying (FSK) transmitters are presented. The first circuit is a 30 to 120 MHz FSK transmitter for wireless body area communication. Unlike the conventional transmitter, multiple injection locked modulation scheme is employed to achieve the FSK modulation. Using this method, both frequencies of the FSK transmitter are locked to the reference frequency. With injection lock, the frequency drift of a free running oscillator can be eliminated. A 9-bit ultra wide-band digitally controlled oscillator (DCO) is employed in this work. The DCO is controlled by a digital-to-analog converter (DAC) for frequency calibration and modulation of frequency. With 4-bit fine tuning and 5-bit coarse tuning, the DCO can cover a wide band from 30 to 120 MHz or even higher frequencies depending on the process parameters. In addition, a 9-bit MUX is used as the control circuit for the DAC. Implemented in 0.18-μm CMOS process, the transmitter is able to achieve a maximum data rate of 5 Mbps, with a core power consumption of 146 μW under 1.2-V power supply. Master of Engineering

The low-density parity-check (LDPC) codes are by far the best error-correction codes discovered till date, providing exceptional performances that verge on the theoretical boundary, otherwise known as the Shannon limit. Yet, in the process of manipulating its enticing features, modern LDPC applications, explicitly the non-volatile memories (NVM), are more often than not encumbered by its very decoding mechanism of recursive nature, which fuels the capacity-approaching performances of the LDPC codes. This thesis therefore demonstrates numerous propositions pertaining to cost-effective high-throughput implementation of the LDPC decoders on field-programmable gate-array (FPGA) hardware, alongside ingenious techniques to compensate for certain performance loopholes in LDPC decoding. Moreover, the possibility and potential of amalgamating two or more of the proposed works have been accomplished and substantiated in this thesis, rendering a concerted effect of high-throughput decoding and low-complexity realization while retaining outstanding decoding performances. Doctor of Philosophy (EEE)

The monolithic microwave integrated circuit (MMIC) has the advantages of higher performances, in terms of frequency, power consumption, functional stability, compact physical size and hence greater integration. MMIC building blocks with excellent performances provide the possibility of realizing high speed sub-terahertz communication systems. In the first part of this research, a distributed amplifier and a distributed mixer with ultra-broad operation bandwidth are designed and analyzed. By deploying various loss compensation techniques, the proposed designs obtain an operation band up to over 100 GHz, with good amplifier gain and good conversion gain for the distributed mixer. In the second part of this research, three function blocks of frequency converters are proposed. By breaking through the limitation of the fabrication technology, the frequency quadrupler gains a 2.1 dBm output at 140 GHz; and the two frequency modulators successfully achieved modulated output signals at 170 and 340 GHz, respectively. To further explore the terahertz MMIC design, new generation of technology, GaN on silicon devices, are characterized in the last part of the research; where the results obtained shall promise a brighter future for the MMICs. Doctor of Philosophy (EEE)

Vehicle tracking based on Global Positioning System (GPS) was first developed in 1960s, which has brought a certain stage of development in vehicle anti -theft evolution. However, the common vehicle tracking system is not able to meet the basic requirements of the Singapore Police Force (SPF) to track the suspected vehicles. The SPF has requested for a comprehensive, simple and yet low cost tracking system to track runaway vehicle. In this dissertation, a GPS projectile vehicle tracking system to fulfill the function of tracking the target vehicle is specially developed for the SPF. The system can be divided into two parts: Tracking Device and Control Device. The development of the two devices is based on the Android Application (App) development, which offers a low cost and convenient method for the project. In this project, two Apps are successfully developed: the first App is to acquire the GPS information of the target vehicle and send SMS to the Control Device, while the second App is able to convert the GPS information into display on the Google Map. The connection between the two devices is simply through SMS. Furthermore, the specific SMS is able to activate the Apps in both devices, which allows the system to be a highly automated. The testing of the two devices is successful to fulfill the requirements of the SPF. Master of Science (Electronics)

Arithmetic addition is a major and fundamental operation in digital signal processing DSP algorithms. Adders are one of the key computing components in DSP core and accelerator designs [ 1]. Thus, arithmetic adder is the key circuit components contributing major computation energy and creating a bottleneck in circuit performance in vehicle sensor node systems. It is therefore essential to design a good adder circuit to improve the overall performance of sensor node systems. In order to design an adder, different adder algorithms are considered so as to determine the suitable adder algorithm. Algorithms such as Radix-2 Kogge-Stone Adder, Radix-4 Kogge-Stone Adder and Brunt-Kung Adder are discussed and compared. The conclusion drawn from the comparison is that the Radix-2 Kogge-Stone Adder is an ideal addition algorithm to calculate large bits addition. After choosing the adder algorithm, the next issue is transistor-level schematic implementation. The whole adder algorithm can be constructed with logic gates. With the implementation of each logic gate in adder algorithm, the transistor-level schematic for the whole adder structure can be built through simulation. The simulation results were derived from Mentor Graphics Modelsim simulation and Cadence Virtuoso simulation. Mentor Graphics Modelsim simulation is to testify the logic feasibility of the adder algorithm while Cadence Virtuoso simulation is used to test the time delay of the adder circuit as to calculate the power consumption of the adder designed. When the adder is designed and simulated, the adder is needed to taken into electrical vehicle application. First, an algorithm called Sum of Absolute Difference which is used to calculate the vehicle speed is proposed. The sensor node architecture is designed. Since arithmetic adders are the key computing components in sensor node system, the Radix-2 Kogge-Stone Adder designed in this dissertation can be used to improve the overall performance of the system. Master of Science (Electronics)

Paralysis has impacted the lives of millions of people, limiting not just their movement and quality of lives but also their mental health. Cortical neural prosthetics is a possible way to cure and if not help these paralyzed patients—by capturing patients’ thought straight from their brain, then processing the information and translating them to electronic control signals to the assistive technologies such as computer interfaces, robotic arms and nerve stimulators. By using these implantable microelectromechanical system (MEMS) electrode arrays that are implanted into the brain, researchers are able to watch the simultaneous activities of many neurons, to understand and appreciate the brain functions. The immediate mission of this research is hence to record neural signals from the human brain, not just adequately but appropriately. In the design of neural recording interface, the neural amplifier must have an input-referred noise that is low enough to detect the weak neural signals, and the power dissipation needs to be ultra-low to avoid tissue damage. Thus, the trade-off between noise and power becomes very important. A noise efficiency factor (NEF) is used to evaluate this trade-off and a lower NEF means better noise-power trade-off. Based on the proposed noise reduction technique, the low noise front-end amplifier developed in this design is able to achieve less than 4 µVrms noise with about 1 µW power consumption over a 5-kHz signal bandwidth. The NEF of the front-end amplifiers developed ranges from 2.2 to 3.6, which are among the lowest reported to-date. Balanced MOS-bipolar active pseudo-resistor structure has been adopted in the neural recording amplifiers to realize the ultra-low high-pass cutoff frequency and good signal linearity. For chronic neural recording, the impedance of the implanted electrode interface with the tissue will increase with time, which must be considered during neural recording amplifier design because the amplifier interfaces directly with the electrode. To further enhance the recording quality of the neural amplifier, another impedance-boosting neural amplifier is developed to boost the input impedance of the amplifier by ten times, which greatly removes the interference arise from the electrode mismatch. The signal to noise ratio does not degrade much even with long term neural recording, and the reliability of the neural recording system is demonstrated to be better than the classic design represented by Harrison’s work. Multi-channel recording is essential because a good amount of useful information can be simultaneously recorded from a large population of neuronal cells and their networks to enable more robust and sophisticated control of prosthetic devices. A 100-channel neural recording interface integrated circuit (IC) is fabricated and verified through hardware measurements. To further reduce the overall power consumption of the neural implant, a neural recording interface IC intended for simultaneous neural recording with action potential (AP) detection for data compression in wireless multichannel neural implants is presented. The proposed neural recording interface IC detects the neural spikes and sends only the preserved AP information for wireless transmission in order to reduce the overall power consumption. Wireless transmission of the recorded neural signal waveform is enabled only during the presence of neural spikes, and hence, the data rate can be effectively reduced by more than ten times when compared to the conventional wireless neural recording system. Furthermore, the complete neural AP information can be securely preserved with adaptive AP recording windows. DOCTOR OF PHILOSOPHY (EEE)

Low-density parity-check code (LDPC code) is a kind of linear block error-correcting code defined by sparse matrices. When the code is long enough, the performance of LPDC codes is even better than Turbo codes, which has made it a strong competitor of the fourth-generation communication systems ( 4G). It has been adopted by many advanced standards, such as digital video broadcasting (DVB-S2). In recent years, LDPC codes have become one of the hottest topics in the field of error-correcting codes. This dissertation shows studies on the theory of encoding and decoding algorithms of LDPC codes and its hardware design and implementation. The main decoding algorithms introduced in this dissertation are Bit-Flipping algorithm, Sum-Product algorithm and Min-Sum algorithm. These algorithms decide the architecture and performance of the decoder. There are mainly three architectures. They are fully parallel, row-parallel and block-parallel architectures. Current research work on LDPC decoders mainly focuses on four aspects: structured LDPC codes, error floor reduction, reconfigurable decoder design and routing congestion reduction. According to the Tanner graph, the processors of the rows and columns are connected directly in a fully parallel decoder, which could provide high through puts. However, implementing the decoder is quite challenging due to the high interconnect complexity in terms of row and column processors. To solve this problem, a method called "Split-Row" is proposed, which significantly reduce processor logical complexity, local and global interconnections. Finally, a fully parallel decoder is implemented by using Verilog HDL, according to corresponding structures. Master of Science

According to the International Technology Roadmap for Semiconductors, silicon-based semiconductor processes are opening doors for millimeter-wave and Terahertz (THz) applications in integrated circuits. Stable and precise millimeter-wave and THz frequency sources are the key and challenging components for the aforementioned high frequency systems. The scope of this thesis is to design frequency multipliers with high efficiency and multiplication factor to multiply the fundamental signal of the frequency phase-locked loop (PLL). The multiplier cores in prior PLLs employ methods of Class-B/C amplifier, mixer, linear superposition technique and travelling-wave multiplier. These techniques present low power efficiency, low conversion efficiency, low output power and small multiplication factor. Suffering from these drawbacks, several multiplier cores are required to be cascaded to achieve a high multiplication factor. Additional power amplifiers are also indispensable among the stages to compensate for the power losses. These solutions inevitably lead to larger system and greater power consumption. This thesis presents a novel phase-controlled multi-push technique that can directly synthesize the Nth harmonic to achieve not just superior power efficiency but also boosting the power efficiency to 50% in an ideal situation. The proposed phase-controlled multi-push multiplier generates harmonics by adding the outputs of the proposed W-shaping phase-controlled cascodes. The W-shaping phase-controlled cascode is a basic element of the phase-controlled multi-push multiplier that generates output waveform shaped like the alphabet "W". The proposed approach had been applied to construct both a tripler and a quadrupler. The two circuits had proven the concept and verified their operating conditions, and will be detailed in this thesis. A 121-to-137 GHz frequency quadrupler based on the proposed phase-controlled multi-push technique was demonstrated using a 0.13-m SiGe BiCMOS process. The DC power consumptions of the fabricated quadrupler core and input buffers are 6.4 mW and 28.8 mW, with power efficiency of 9% and 1.6%, respectively. This work has been presented at the 2012 International Solid-State Circuits Conference (ISSCC). Additional design considerations, i.e., effects of phase mismatch, and developments, such as the extension of concept to implement other multiplication factor, have also been conducted at such high frequencies. Master of Engineering

Recently, wireless sensor node systems are widely used in many applications, including healthcare, industry and environment monitorings. Specifically, wireless image sensor nodes are widely used in smart buildings for security monitoring. Energy-efficient DSP processors can be designed and utilized in wireless image sensor nodes to perform image analysis and compression. However, discrete cosine transform (DCT), which is the key component in image compression process, is very time consuming and power hungry. In this study, several fast DCT algorithms are studied and compared. Classical fast DCT algorithms such as the l l-multiplication 8-point DCT algorithm are able to reduce the numbers of addition and multiplication so that the required computation can be minimized, thereby improving on the energy efficiency. The energy efficiency can in fact be further improved using the integer DCT algorithm that has shorter integer arithmetic operations and hence lesser hardware resource, faster computation and lower power consumption. Furthermore, adders and shifters are used to replace multipliers to achieve a higher speed and also lower energy consumption. In this dissertation, a new integer DCT processor is designed with a higher throughput rate as compared to the conventional hardware design. Matlab and RTL simulation had been conducted to verify the functionality of the proposed integer DCT processor design. The analysis and discussion conducted that the proposed energy-efficient integer DCT processor obtained a doubled throughput rate and is hence suitable for use in wireless image sensor node systems in the smart building applications. Master of Science (Electronics)

Wireless implantable medical devices have transfigured the field of biomedical engineering with the invention of adequate power supplies. Conflicting the commonly used RF and inductive methods, ultrasonic transmission of power circumvents problems associated with low inefficiencies and electromagnetic coupling offering application for a selection of data frequencies. Moreover, it prevails over the demerits of wireless power transfer through inductive coupling. In this dissertation, the candidate explored a novel ultrasonic link for wireless power and data transfer deep in the body, integrated with MEMS ultrasonic transducers, especially intended for neuro-stimulator that is to be implanted deep in a patient's body to function as, for example the pacemaker, bladder pressure sensor, implantable blood flow monitoring system, neural stimulation system, defibrillators, circulatory assist devices, etc. Master of Engineering

Applications of signal processing have engendered numerous breakthroughs in science and technology, transforming mundane lifestyles to a whole new dimension of comfort and indulgence that includes mobile broadband, high definition streaming, etc. One important aspect of signal processing that contributed to such luxuries is the channel coding, which is evident in our daily usage, ranging from mobile phone to satellite communications. Recently, a special class of block codes, known as Low Density Parity Check (LDPC) codes, has piqued interest upon many researchers for its capacity approaching performance as well as the speed of its decoding algorithm that transcends most existing channel codes. Master of Science (Signal Processing)

101 p. Avalanche photodiodes (APD) are photodetectors which have higher internal gain compared to the other photodiodes. This is due to impact ionization therefore more sensitive compared to other semiconductor. The project concentrates on the noise measurement circuit for the APD. Master of Science (Consumer Electronics)

89 p. The volume of data over telecommunication network has put greater demands for faster communication channels to allow more data to be transferred in given time. Among all the communication medium optical transmission through optical fibers achieves highest bandwidth. Synchronous optical network (SONET) standard in North America and Synchronous Digital Hierarchy (SDH) standard in Europe are results of constant growth and development in optical communications. Master of Science (Integrated Circuit Design)

186 p. As the clock frequency scales, the pipeline depth increases and the number of logic gates per stage decreases. The System-on-Chip (SoC) designs will therefore integrate tens of millions of transistors on one chip. But the packaging and cooling designs have only a limited ability to remove the excess heat produced by the systems. All these factors have resulted in power consumption to be considered as one of the main problems in achieving high performance designs. The energy consumption of the clocking sub-system that is composed of the clock distribution networks (buffers and wires) and clock storage elements (flip-flops and latches) is about 30% to 60% of the total system energy. For this clock system power, 90% is consumed by the flip-flops themselves and the last branches of the clock distribution network that drives the flip-flop directly. As clock frequency increases, the latency of the flip-flop will play an even greater role in the overall cycle time. As a result, it is essential to continue venturing into higher-end approaches and realizing more refined solutions to achieve low-voltage/lowpower design while sustaining high-speed performance and small-area consumption. In this thesis, several innovative flip-flop designs for low-voltage low-power environments used are described. DOCTOR OF PHILOSOPHY (EEE)