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In this paper, we adopted thermally stable HfOxNy as gate dielectric for TiN/HfOxNy/AlGaN/GaN heterostructure field-effect transistors (HFETs) application. It demonstrated that the surface morphologies, composition, and optical properties of the HfOxNy films were dependent on oxygen flow rate in the O2/N2/Ar mixture sputtering ambient. The obtained metal–oxide–semiconductor heterostructure field-effect transistors by depositing HfO2 and HfOxNy dielectric at different oxygen flow rates possessed a small hysteresis and a low leakage current. After post deposition annealing at 900 °C, the device using HfOxNy dielectric operated normally with good pinch-off characteristics, while obvious degradation are observed for the HfO2 gated one at 600 °C. This result shows that the HfOxNy dielectric is a promising candidate for the self-aligned gate process. [ABSTRACT FROM AUTHOR]

In this study, a low-temperature annealed ohmic contact process was proposed on AlGaN/GaN heterostructure field effect transistors (HFETs) with the assistance of inductively coupled plasma (ICP) surface treatment. The effect of ICP treatment process on the 2DEG channel as well as the formation mechanism of the low annealing temperature ohmic contact was investigated. An appropriate residual AlGaN thickness and a plasma-induced damage are considered to contribute to the low-temperature annealed ohmic contact. By using a single Al layer to replace the conventional Ti/Al stacks, ohmic contact with a contact resistance of 0.35 Ω·mm was obtained when annealed at 575 °C for 3 min. Good ohmic contact was also obtained by annealing at 500 °C for 20 min. [ABSTRACT FROM AUTHOR]

Self-aligned-gate heterostructure field-effect transistor (HFET) is fabricated using a wet-etching method. Titanium nitride (TiN) is one kind of thermal stable material which can be used as the gate electrode. A Ti/Au cap layer is fixed on the gate and acts as an etching mask. Then the T-shaped gate is automatically formed through over-etching the TiN layer in 30% H2O2 solution at 95 °C. After treating the ohmic region with an inductively coupled plasma (ICP) method, an Al layer is sputtered as an ohmic electrode. The ohmic contact resistance is approximately 0.3 Ω·mm after annealing at a low-temperature of 575 °C in N2 ambient for 1 min. The TiN gate leakage current is only 10−8 A after the low-temperature ohmic process. The access region length of the self-aligned-gate (SAG) HFET was reduced from 2 μm to 0.3 μm compared with that of the gate-first HFET. The output current density and transconductance of the device which has the same gate length and width are also increased. [ABSTRACT FROM AUTHOR]

An Al-based ohmic process assisted by an inductively coupled plasma (ICP) recess treatment is proposed for AlGaN/GaN heterostructure field-effect transistors (HFETs) to realize ohmic contact, which is only needed to anneal at 500 °C. The recess treatment was done with SiCl4 plasma with 100 W ICP power for 20 s and annealing at 575 °C for 1 min. Under these conditions, contact resistance of 0.52 Ωmm was confirmed. To suppress the ball-up phenomenon and improve the surface morphology, an Al/TiN structure was also fabricated with the same conditions. The contact resistance was further improved to 0.30 Ωmm. By using this plasma-assisted ohmic process, a gate-first HFET was fabricated. The device showed high drain current density and high transconductance. The leakage current of the TiN-gate device decreased to 10−9 A, which was 5 orders of magnitude lower than that of the device annealed at 800 °C. The results showed that the low-temperature ohmic contact process assisted by ICP treatment is promising for the fabrication of gate-first and self-aligned gate HFETs. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) metal-oxide-semiconductor field-effect transistors (MOSFETs) with boron field implantation isolation and mesa isolation were fabricated and characterized. The process of boron field implantation was altered and subsequently conducted after performing high-temperature ohmic annealing and gate oxide thermal treatment. Implanted regions with high resistivity were achieved. The circular MOSFET fabricated in the implanted region showed an extremely low current of 6.5 × 10−12 A under a gate voltage value up to 10 V, thus demonstrating that the parasitic MOSFET in the isolation region was eliminated by boron field implantation. The off-state drain current of the rectangular MOSFET with boron field implantation was 5.5 × 10−11 A, which was only one order of magnitude higher than the 6.6 × 10−12 A of the circular device. By contrast, the rectangular MOSFET with mesa isolation presented an off-state drain current of 3.2 × 10−9 A. The field isolation for GaN MOSFETs was achieved by using boron field implantation. The implantation did not reduce the field-effect mobility. The isolation structure of both mesa and implantation did not influence the subthreshold swing, whereas the isolation structure of only the implantation increased the subthreshold swing. The breakdown voltage of the implanted region with 5 μm spacing was up to 901.5 V. [ABSTRACT FROM AUTHOR]

We report a new approach in fabricating a self-aligned gate GaN MOSFET. The fabrication technique is based on a double-layer photoresist (PR) and low-temperature-Ohmic formation process assisted by an inductively coupled plasma (ICP) dry etching process. In this process, the active region was automatically defined by the combination of a subsequently developed positive PR and the existing negative PR pattern. The Al Ohmic electrodes on the ICP-treated active region were formed by a lift-off process followed by 500 °C N2 1 min annealing. The specific contact resistance of 4.8 × 10−6Ω cm2 was obtained in this process. Operation up to a gate bias of 30 V was confirmed. The maximum output current of 98 mA mm−1 and field-effect mobility of 110 cm2 V−1 s−1 were observed in the device with a gate length of 4 μm. Some non-ideal effects in this device, including the negative threshold voltage, larger off-state leakage and unsaturated on-state drain current, were also observed and analyzed. Some possible ways to improve the performance of the device were proposed. [ABSTRACT FROM AUTHOR]

In this paper, the influence of deposition conditions and post annealing upon the device performance of sputtering-deposited TiN/AlO/AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors is reported. The metal-oxide-semiconductor structure on GaN with AlO deposited in a medium O2/Ar ratio possessed the smallest interfacial state density and reverse leakage current. Metal-oxide-semiconductor heterostructure field-effect transistors with a small hysteresis and a low leakage current were obtained by depositing AlO with a medium O2/Ar ratio and post-annealing at 600 °C for 1 min. After annealing, the maximum transconductance shows some decrease, resulting in a decrease of saturation drain current. [ABSTRACT FROM AUTHOR]

The miniaturization of the pH sensor has been improved with the development of the silicon ion-sensitive field-effect transistor (ISFET). Gallium nitride (GaN) is a possible candidate for developing a pH sensor owing to its superior resistance to environmental effects, superior conductivity, wide bandgap and chemical stability compared with silicon. In this study, a pH sensor fabricated on an AlGaN/GaN heterostructure was developed and its sensing characteristics were evaluated at temperature range from room temperature to 80 °C. The sensor shows good pinch-off and transfer characteristics at each temperature point in three standard buffered solutions. The drain current decreased and the threshold voltage showed a positive shift with pH increasing. Drain current decrease and positive threshold voltage shift were also noted with increasing temperature. The pH sensitivities (ΔV/pH) are 52.3, 57.2, 64.2, and 69.5 mV/pH at temperatures of 20, 40, 60, and 80 °C, respectively, which are close to the theoretical values at all the temperature points. [ABSTRACT FROM AUTHOR]

Side-gating effects on AlGaN/GaN heterojunction FETs (HFETs) are simulated using a two-dimensional device simulator incorporating the Shockley–Read–Hall (SRH) model for deep traps. With the trap parameters obtained from experiments, the simulation results are in agreement with the experimental results including the “half-recovery” from the side-gating effect and the current reduction in the recovery process from positive side-gate bias application. The simulation indicated that the finite thickness of semi-insulating i-GaN layers suppresses side-gating effects on AlGaN/GaN HFETs with thin i-GaN layers. [ABSTRACT FROM AUTHOR]

GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with recessed gate on AlGaN/GaN heterostructure are reported in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. Negative threshold voltages were commonly observed in all devices. To investigate the reasons of the negative threshold voltages, different oxide thickness, etching gas and bias power of inductively-coupled plasma (ICP) system were utilized in the fabrication process of the GaN MOSFETs. It is found that positive charges of around 1 x 1012 q/cm² exist near the interface at the just threshold condition in both silane- and tetraethylorthosilicate (TEOS)-based devices. It is also found that the threshold voltages do not obviously change with the different etching gas (SiCl4, BCl3 and two-step etching of SiCl4/Cl2) at the same ICP bias power level (20-25 W) and will become deeper when higher bias power is used in the dry recess process which may be related to the much serious ion bombardment damage. Furthermore, X-ray photoelectron spectroscopy (XPS) experiments were done to investigate the surface conditions. It is found that N 1s peaks become lower with higher bias power of the dry etching process. Also, silicon contamination was found and could be removed by HNO3/HF solution. It indicates that the nitrogen vacancies are mainly responsible for the negative threshold voltages rather than the silicon contamination. It demonstrates that optimization of the ICP recess conditions and improvement of the surface condition are still necessary to realize enhancement-mode GaN MOSFETs on AlGaN/GaN heterostructure. [ABSTRACT FROM AUTHOR]