Search

Abstract: We propose a novel resistive switching device with a W/CeO2/Si/TiN structure by incorporating a very thin Si buffer layer in the interface, the memory performance of this device such as forming voltage, operation power, and window and endurance characteristics were found to be remarkably improved compared with the performance of the device without the Si layer. This improvement was attributed to the formation of Ce-silicate and thus proper introduction of oxygen vacancies at the interface. The gradual reset process of the W/CeO2/Si/TiN device under sweeping voltage was quantitatively analyzed by parallel conductive filaments model. Our results provide a guideline for the operation voltage control for further optimizing device performance and give new insights into the gradual reset process. [Copyright &y& Elsevier]

Abstract: The effects of controlling InGaAs substrate temperature during electron beam deposition of HfO2 on electrical characteristics of W/HfO2/n-In0.53Ga0.47As capacitors are investigated. It is found that by depositing a thin HfO2 layer at the interface when substrate temperature is raised to 300°C, frequency dispersion at depletion and accumulation conditions is reduced and interface state density is lowered regardless of the HfO2 thickness. Cross-sectional transmission electron microscopy images have revealed that the formation of mesoscopic voids in the InGaAs substrate near the interface is suppressed with HfO2deposition at 300°C at the interface. A band diagram with an additional bulk trap energy level has been proposed to explain the frequency dispersion and conductance peaks at accumulation condition. [Copyright &y& Elsevier]

Abstract: The roll-off and roll-up behavior of flatband voltage (V fb) on equivalent oxide thickness (EOT) of La2O3/silicate capacitors have been characterized by X-ray photoelectron spectroscopy and modeled by the fixed charges. It has been revealed that the thickness of the reactively formed silicate layer is dependent on the La2O3 thickness initially deposited on the wafer. When the La2O3 thickness is over 3nm, the silicate layer has been found to be formed with a constant thickness of 1.6nm. However, while decreasing the La2O3 thickness to 1nm, the thickness of silicate layer decreases due to the reduction of radical oxygen atoms originated from the La2O3 layer, resulting in the formation of La-rich silicate. The V fb roll-off behavior can be attributed to the enhanced generation of positive fixed charges induced by the diffusion of metal atoms from the gate electrode into the silicate layer. On the other hand, the V fb roll-up behavior can be explained when the initially deposited La2O3 layer has been all converted into silicate. [Copyright &y& Elsevier]

Abstract: N-type metal–oxide–semiconductor field-effect transistor (MOSFET) with an equivalent oxide thickness (EOT) of 0.37nm has been demonstrated with La2O3 as a gate dielectric for the first time. Despite the existence of parasitic capacitances at gate electrode and inversion layer in the channel, a sufficient drain current increment in both linear and saturation regions have been observed, while scaling the gate oxide from 0.48 to 0.37nm in EOT. Therefore, continuous scaling of EOT below 0.5nm is still effective for further improvement in device performance. [Copyright &y& Elsevier]

Abstract: The chemical bonding states and electrical characteristics of SrO capped La2O3/CeO x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5nm has been demonstrated. A strongly degraded effective electron mobility of 78cm2/Vs at 1MV/cm has been obtained, which fit well with the general trend in small EOT range below 1nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling. [Copyright &y& Elsevier]

Abstract: The study on post metallization annealing (PMA) in electrical characteristics and interfacial properties of La2O3/Ge structures has been conducted. The PMA treatment in N2 ambient induces the growth of interfacial Ge oxide layer accompanied with decrease of capacitance value and interface trap density. The interface-layer growth is caused by the oxidation of Ge substrate due to the hydroxyl group absorbed in La2O3 from the ambient. The metal electrode capping might prevent the hydroxyl from evaporating during annealing, which enhances the interface reaction. On the other hand, leakage current increment has been observed for the sample with PMA in case of using Pt gate electrode. It is due to the diffusion of Pt and/or Ge and a Pt-germanide formation in La2O3 film during PMA. This leakage current increment can be suppressed by using Ta or W electrode which has less reactivity with Ge than Pt at high temperature. [Copyright &y& Elsevier]

Abstract: The origin of flat band voltage (V FB) shift with La2O3 insertion for HfO2 gate dielectrics has been carefully examined. By separating the effect of the fixed charges located at each interface by thickness-dependent V FB evolution, total voltage shifts (dipole) at metal/high-k and high-k/SiO2 interfaces have been estimated. Using stacked capacitors of La2O3 and HfO2, it can be concluded that V FB is mainly determined by the high-k on SiO2. Therefore, the dipole at La2O3 and the interface has an additional dipole of 0.36eV compared with that of HfO2/SiO2. The same trend has also been obtained with a high-k on a Si substrate without a SiO2 layer. A simple model using electronegativity has been proposed to explain the V FB shift. [Copyright &y& Elsevier]

Abstract: The electrical characteristics and interfacial properties of La2O3/Ge structures under various post-deposition annealing (PDA) conditions are studied. We found that the interfacial Ge oxide layer reduced the Dit, while redundant growth of the oxide led to increment of CET. In order to satisfy small CET and low Dit, appropriate interfacial layer (IL) thickness is assumed to be 1.0-1.5 nm. On the other hand, Ge sub-oxide in the IL caused to increase hysteresis. Instead, by introducing the Ge chemical oxide, an interfacial La-germanate layer formed with PDA at 500 °C in N2, which could reduced both the hysteresis and Dit. [Copyright &y& Elsevier]

A simple yet accurate model for the postbreakdown output characteristics of advanced n-MOS transistors with metal gate (W) and high-κ (La2O3, equivalent oxide thickness=0.6 nm) gate insulator is reported. The model specifically deals with the so-called linear response regime in which the transistor action is no longer operative after the failure event. By analyzing three particular cases of interest, it is shown that the proposed model is able to account for the conduction characteristics corresponding to failure sites located both at the center of the channel region and close to the source and drain contacts. A compact model for the bulk-drain current is included in order to simulate the departure from linearity occurring at the negative drain bias. [ABSTRACT FROM AUTHOR]

This letter reports the subthreshold characteristics of MOS transistors with the novel \CeO2/\La2\O3 stacked gate dielectric. We found that the top \CeO2 capping layer does not only improve the bulk properties of \La2\O3 by reducing the oxygen vacancies as a result of the reduction reaction of \CeO2 but also reduces the \La2 \O3/\Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements. [ABSTRACT FROM AUTHOR]

Through scanning tunneling microscopy, the rate of electrical stress induced trap generation in the vicinity of the tip/high-κ interface of the Sc2O3/La2O3/SiOx gate stack is observed to be much higher than that at the SiOx/Si interface, implying that the former is more susceptible to electrical stress induced wear out. This polarity dependence is discussed in the context of current trap generation models and is shown to be best explained by anode hot-hole effect induced by inherently lower surface plasmon threshold energy at the metal/high-κ interface and a higher hole trapping rate in the relatively thick high-κ. [ABSTRACT FROM AUTHOR]

Abstract: The flat band voltage shifts of HfO2/SiO2/nSi capacitors with ultra-thin La2O3 insertion at HfO2/SiO2 interface have been confirmed using hard X-ray photoelectron spectroscopy (HX-PES). By increasing the amount of La2O3 insertion, the binding energy of Si 1s core spectra increases, which means that the surface potential of Si substrate also increases. A voltage drop difference of HfO2 and La2O3 at SiO2 interface can be estimated to be 0.40V. [Copyright &y& Elsevier]

From scanning tunneling microscopy, we present unambiguous evidence of thermally induced localized conduction paths exhibiting an asymmetrical conduction property in the high-κ gate stack. The tunneling current under gate injection biasing is found to be much larger than that under substrate injection biasing after a 700 °C postdeposition anneal, i.e., the localized paths exhibit a much lower resistance under gate injection biasing. This finding provides a phenomenological explanation for the polarity dependent breakdown of the high-κ gate stack as observed from electrical stressing of large-area metal-oxide-semiconductor capacitors. [ABSTRACT FROM AUTHOR]

The tunneling current versus voltage characteristic of the Sc2O3/La2O3/SiOx high-κ gate stack is examined using scanning tunneling microscopy in ultrahigh vacuum. Different measurement bias polarities allow information on the location (i.e., in the high-κ or interfacial SiOx layer) of the electronic traps to be extracted. Two types of localized leakage sites may be distinguished. Lowering of the electron barrier height and trap-assisted tunneling are proposed as the two leakage mechanisms. [ABSTRACT FROM AUTHOR]