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This paper presents the design, simulation of performance, and layout of a one-bit comparator for a pipeline analog-to-digital converter. It has been designed for the low critical temperature technology of the European Fluxonics Foundry and the part excluding the digital readout has been fabricated. Simulation shows that the incoming signal amplitude is reduced by a nearly constant amount above the threshold of the comparator, which is seen as a decrease of about 38% of the power transmission coefficient at the carrier frequency.

We have designed and demonstrated an Arithmetic-Logic Unit (ALU) based on RSFQ technology as a required step toward building an 8-bit RSFQ processor datapath. The circuit was designed and fabricated with HYPRES' standard 4.5 kA/cm2 process. The target clock frequency of the ALU is 20 GHz. In this paper, we present the design and functionality (low-speed) test results of the 8-bit ALU.

This paper investigates the trade-off between speed and accuracy of a Josephson comparator by numerical simulations. The accuracy is quantified by the width of the gray zone whereas the speed is determined by the switching time of the comparator cell. In contrast to previous studies, both performance parameters are simultaneously evaluated. It turns out that there is an inherent compromise between speed and accuracy that is robust against modifications of circuit parameters. Eventually, a new comparator topology is proposed to improve the accuracy while maintaining a reasonable switching speed.

Josephson junctions with non-hysteretic current-voltage characteristics form the basis of most superconducting electronic circuits including RSFQ logic and programmable Josephson voltage standards. In contrast to conventional SIS devices, Nb/Al-AlOx-Nb (SNIS) junctions with an additional comparatively thick Al interlayer and a comparatively thin barrier AlOx are intrinsically shunted at T ≥ 4.2 K . In this contribution, we provide experimental and theoretical arguments proving that this finding is mainly explained by a broad distribution of highly-conductive barrier transparencies with a significant effect from nearly ballistic modes. An additional advantage of the proposed SNIS junctions is possibility to tune the critical voltage value by modifying Nb and/or Al film thicknesses. With observations of wide Shapiro steps up to 1.25 V at 6.3 K we show that this type of Josephson junctions can be successfully used at temperatures above 4.2 K. The presence of well-developed quantized voltage features even at 7.2 K means that Nb/Al-AlOx-Nb devices can successfully operate far above the liquid helium temperature and, in principle, are compatible with two-stage cryocoolers.

Development of an efficient processor architecture with appropriate clocking mechanisms and datapath organization is one of the most challenging design issues for 32-/64-bit RSFQ processors. The cell-level design of a 32-bit RSFQ dual-lane integer processor has been developed at Stony Brook University in an effort to identify and study techniques capable of tolerating significant delay variations in future wide datapath superconductor processor circuits. Several key processor blocks have been designed and quantitatively evaluated at the cell-level, specifically: an instruction buffer, an instruction decoder, a multi-ported register file, a wave-pipelined arithmetic-logic unit, and an intra-processor data routing interconnect. Simulation and analysis of these blocks have been done using a generic VHDL cell library developed at Stony Brook University with cell parameters tuned to Hypres' 1.5 μm, 4.5 kA/cm2 process. After assembling these blocks together into a 32-bit processor datapath, an iterative approach has been used to optimize the design and reach a 20 GHz processing rate. Overall, the datapath has the total latency of ~ 972 ps with the design complexity exceeding 50 K Josephson junctions.

NbN RSFQ circuits operating at 9 K reduce the cooling constraints especially for portable, remote, telecoms or medical imaging applications. We have developed a test-bed to study the operating temperature of the various mixed RF and digital circuit blocks of NbN `HyperSCAN' project test vehicle 1 cm2 chips. The use of a widespread helium cryostat (`Orange-ILL') allows us to stabilize the chip temperature in the range 2.9 K-20 K with thermal oscillations lower than 0.1 K. The chip is mounted on a PCB and shielded from the external field: the PCB provides a multi-connection packaging used in order to study temperature and frequency operation of 30 GHz NbTiN CPW filters, RSFQ gates, analog SQUID and NbN/TaN/NbN SNS junctions arrays. The comparison between electrical simulations and tests is made on flexible, ~ 56 cm long, micro-strip line ribbon cable carrying 32 signals each including bias lines, in the range of DC-3 GHz, combined with 4 semi-rigid ~ 40 GHz coaxial cables. By removing spurious resonances, it is expected to take full benefit of the large bandwidth, low insertion loss and low thermal conductivity of the set-up. We emphasis on the flexibility, large yield, reliability and reduced cost of such packaging coupled to He cooling exchanger for applying to testers and to future 9 K NbN multi-ADC green and remote systems when only low electrical power sources are available.

We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 kA/cm2 and advanced 10 kA/cm2 processes and successfully tested at high speed.

A digital SQUID magnetometer measures the magnetic field amplitude by counting integer magnetic flux quanta within its superconducting input loop. Although resolution is limited in comparison to analog SQUID systems, the digital SQUID is able to outrange its analog counterpart with regard to parameters such as slew rate and dynamic range. In this work we evaluate the performance of a digital SQUID based on a three-level logic. Due to this basic principle, we face a combination of two comparator grayzones leading to hysteretic behavior of the sensor that produces a “dead zone” in the signal reversal point. The dependence of the comparator threshold on design parameters is investigated by simulation studies and reconfirmed by experimental results. We were able to reach a total dynamic range of more than 540,000 flux quanta (about 19 bit) with a linearity error of about 5 bit due to the mentioned hysteretic behavior. We discuss the results of our investigations and provide guidelines to extend dynamic range and linearity for future sensor designs.

Research has been done on the metaheuristic optimization of RSFQ circuits, but these are typically limited to single criteria (e.g., yield). The importance of using multiple criteria and the relevance of each of the criteria is discussed. The application of data envelopment analysis (DEA) and an interactive normalization technique as multi-criteria evaluation methods for the optimization of RSFQ circuits are investigated. We find that these evaluation methods each have clear advantages and disadvantages over each other. The normalization technique requires the analysis designer to have a good understanding of circuit design to be accurate, while the DEA method may yield many results that are ranked equally efficient.

The Fast Fourier Transform (FFT) is extensively used in image processing, wireless communication, and other applications. Some applications that involve very complicated, real-time FFT processing require specialized hardware for performing high-speed FFT processing. We have been developing high-speed FFT processors based on single flux quantum (SFQ) circuit technology. In this study, we developed a butterfly processing element for FFT processors that uses SFQ circuits. The butterfly processing element consists of complex number adders, subtractors, and multipliers. The circuit structure was modified compared to that of previous SFQ FFT processors to reduce latency. Several buffer circuits were inserted in the multipliers to compensate for timing jitter accumulation and discrepancies due to signal propagation delay. We designed and implemented a four-bit bit-serial butterfly processing element that contains 5763 Josephson junctions using the ISTEC Nb 2.5-kA/cm2 standard 2 process and the CONNECT cell library. Correct operation of the butterfly processing unit was experimentally confirmed at a clock frequency of 25 GHz.

Figures of merit connecting processing capabilities with power dissipated (OpS/Watt, Joule/bit, etc.) are becoming dominant factors in choosing technologies for implementing the next generation of computing and communication network systems. Superconductivity is viewed as a technology capable of achieving higher energy efficiencies than other technologies. Static power dissipation of standard RSFQ logic, associated with dc bias resistors, is responsible for most of the circuit power dissipation. In this paper, we review and compare different superconductor digital technology approaches and logic families addressing this problem. We present a novel energy-efficient single flux quantum logic family, ERSFQ/eSFQ. We also discuss energy-efficient approaches for output data interface and overall cryosystem design.

Rapid single flux quantum (RSFQ) electronics is characterized by a very low switching energy. This advantage leads to a noise susceptibility, which becomes a challenge for large-scale circuits as well as for circuits using Josephson junctions with reduced critical current density. We demonstrate an improved operation range and advanced noise immunity of basic cells resulting from an implemented phase shifting element. One of those elements is the π-phase shifter. It consists of a single flux quantum trapped in a superconducting loop. The π-phase shifter can be easily produced in standard niobium technology without any process modifications. Utilizing a mature process brings advantages concerning the reliable fabrication of complex circuits.

NbN-TaN-Nb(Ti)N non-hysteretic SNS Josephson junctions with TaXN barriers tuned through nitrogen content at metal-insulator transition have been produced in a reliable way with characteristic voltage RNIC above 1.5 mV at 9 K. Barriers are typically 7-10 nm thick and Jc in the range 5 to 25 kA/cm-2 making feasible LSI RSFQ ADC circuit integration by using the lithographic tools of the Leti C-MOS platform. Junction tri-layers, NbTiN ground-plane and wiring levels have been reactively sputtered and optimized at 300°C in a reproducible way on 8-inch oxidized silicon wafers. A deep UV stepper combined with SF6 gas mixtures RIE has been used to achieve low spread lithography in junction diameters of 716 nm (3σ ~ 40 nm), of 465 nm (3σ ~ 84 nm) across the 8-inch. A well controlled CMP planarization process has been developed on thick PE-CVD silica layers deposited on each superconducting nitride layer. On-line FIB-SEM observations and electrical characterizations associated to the development of a technology test vehicle demonstrate the feasibility of the complete process. The reliable production of nitrides LSI RSFQ circuits such as ADCs and integrated imagers operating in a relaxed cryogenic environment in the 6-10 K temperature range is foreseen to open new telecoms and medical applications. Moreover, a new MgO-AlN-MgO layered insulating barrier junction is shown to operate above 10 K and will be developed for analog front-end circuit parts.

We present a novel, resistor-free approach to dc biasing of RSFQ circuits, known as Energy-efficient RSFQ (ERSFQ). This biasing scheme does not dissipate energy in the static (non-active) mode, and dissipates orders of magnitude less power than traditional RSFQ while operating. Using this approach, we have designed, fabricated and successfully tested at low and high speed a D flip-flop with complementary outputs and several static frequency dividers. We present the method, demonstrate experimental results, and discuss future implementations of ERSFQ.

We implemented small superconducting loops containing a frozen single flux quantum in single flux quantum (SFQ) electronics. Such an element acts as a π -phaseshifter which is the missing complementary circuit element in SFQ electronics and can significantly improve the circuit reliability and robustness. We designed a four bit ripple counter including toggle flip-flops (TFF) with these π -phaseshifters. We analyzed the circuit stability by means of bit error rate (BER) measurements versus bias supply. The measured operation range of the counter in standard SFQ technique was ±14% and could be improved to ±24% for the new version utilizing π -phaseshifters. These results are a clear proof for a more robust circuit realization achieved without any additional power consumption. Furthermore, it supports the reduction of present power consumption in SFQ circuits by using smaller switching energy as well as the development of more complex circuits because of a reduced sensitivity against technological parameter spread.

We have been studying a superconducting quantum-computing system where superconducting Josephson-junction quantum bits (qubits) are controlled and read out by rapid single-flux-quantum (RSFQ) circuits. In this study, we designed and fabricated an on-chip RSFQ microwave pulse generator (MPG), which generates microwave pulses with the time resolution of sub-ns for precise control of qubit states. The output microwave amplitude of the MPG can be amplified to more than 350 μV using a multi-flux-quantum (MFQ) driver, which increases the number of the propagating single-flux-quantum (SFQ) pulses. Fundamental properties of the MFQ driver and the RSFQ MPG were measured at 4.2 K. It was confirmed that the MFQ driver can amplify an SFQ pulse up to six MFQ pulses and the irradiation time and the amplitude of the output microwave of the RSFQ MPG can be controlled adequately.

Superconducting Quantum Interference Devices (SQUIDs) are known to be the most sensitive magnetometers, used in a wide range of applications like biomagnetism, geomagnetism, Non Destructive Evaluation (NDE), metrology or fundamental science. For all these applications, the SQUID sensor is used in analog mode and associated with a carefully designed room-temperature control and/or feedback electronics. Nevertheless, the use of SQUID sensors in digital mode is of high interest for several applications due to their quantum accuracy associated to high linearity, and their potentially very high slew rate and dynamic range. The concept and performances of a low-Tc digital magnetometer based on Single-Flux-Quantum (SFQ) logic, fabricated at the FLUXON-ICS Foundry located at IPHT Jena, Germany, are given after a presentation of the context of development of superconductive digital magnetometers. The sensitivity, limited to one magnetic single flux quantum, and a dynamic range of 76 dB, that corresponds to an upper limit of the magnetic field amplitude higher than 5 μT, have been measured along with overnight stability. The dynamic range of about 2800 magnetic flux quanta Φ 0 has been experimentally observed with an external magnetic field. First signatures of magnetic fields have been observed simultaneously with the ones of analog SQUIDs in the low noise environment of the Laboratoire Souterrain a Bas Bruit (LSBB) located in Rustrel, Provence, France.

We have been studying a superconducting quantum-computing system where superconducting qubits are controlled and read out by rapid single-flux- quantum (RSFQ) circuits. In this study, we designed and fabricated an RSFQ microwave chopper, which turns on and off an externally applied microwave to control qubit states with the time resolution of sub-nanosecond. The chopper is implemented in a microwave module and mounted in a dilution refrigerator. We tested the microwave chopper at 4.2 K. The amplitude of the output microwave was approximately 100 μV which is much larger than that of previously designed chopper. We also confirmed that the irradiation time can be controlled by RSFQ control circuits.

Rapid single flux quantum (RSFQ) circuits create high interest in cryogenic amplifiers as interface to commercial room temperature electronics. The requirements for the amplifiers are an extremely high bandwidth (SFQ pulses with t rise = t fall = 10 ps ), high voltage gain of about 10 4 (common RSFQ output voltage level of about 200 μ V ), low power consumption (cryogenic environment at 4 K) and low noise. Hybrid amplifiers, based on commercial available p-HEMT transistors, can solve the problematic high-speed interface. In this paper, we present measurement results of a hybrid four stage coplanar amplifier in combination with a RSFQ Toggle Flip-Flop (RSFQ T-FF) and a Josephson array quantizer (JA-Q).

Cryoelectronic integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology are promising candidates for realizing systems exhibiting very high performance in combination with very low-power consumption. Like other superconductive logic circuits, they are characterized by a high switching speed. Their unique feature consists in the particular representation of binary information by means of short transient voltage pulses. The development of RSFQ circuits and systems requires a comprehensive design approach, supported by appropriate tools. Within the recent years, a dedicated design infrastructure has been developed in Europe in close association with a foundry for digital RSFQ integrated circuits. As a result, RSFQ technology has matured to such a level that engineering efforts enable the development of integrated circuits. In the contribution, the basic features of the RSFQ circuit design are addressed within the context of technical and infrastructural issues of implementation from a European perspective.

The state-of-the-art Rapid Single Flux Quantum (RSFQ) circuits consists of Josephson junctions (JJ), inductances and bias current sources, whereat the inductances are practically used as functional elements. Even more, their value defines the functionality and therefore the conventional design process requires strict conditions for the wiring between JJs. The present design and optimization process does not take into account distributed microwave properties. This becomes an important issue for high-dense ultra fast applications above 100 GHz, but also for circuits dedicated to control quantum electronics with reduced critical current density. We discuss different wiring configurations and analyze their properties. We present our theoretical and experimental results about the influence of the line impedance to the operation of RSFQ circuits. The impedance matching between the connecting microstrip-lines and the JJ is a key issue for the correct operation. We performed circuit simulations and collected experimental data of correct and incorrect operating circuits to derive a design criteria. The critical reflection coefficient is 0.35 and the particular design must use a smaller value to ensure pulse transfer and a larger value for storage of SFQ pulses, respectively.

State-of-the-art RSFQ circuits consist of Josephson junctions, inductances and bias current sources, where the inductances are practically used as functional elements. Even more, their value defines the functionality and therefore the conventional design process requires strict conditions for the wiring between Josephson junctions. The present design and optimization process does not take into account their parasitic capacitances to ground. This becomes an important issue for ultra fast applications above 100 GHz, but also for circuits dedicated to control quantum electronics. We report on a theoretical and experimental investigation of the influence of ground capacitances. The impedance matching between the connecting microstrip lines and the Josephson junction is a key issue for the correct operation of these circuits. We performed circuit simulations and collected experimental data of correct and incorrect operating circuits to derive design criteria. The critical reflection coefficient is found to be 0.35 and the particular design must use a smaller value for transfer and a larger value for storage of SFQ pulses, respectively.

We report fabrication and characterization of epitaxial NbN/TaN/NbN Josephson junctions grown by pulsed laser ablation. These SNS junctions can be used as elements of rapid-single-flux-quantum (RSFQ) logic, which is a promising technology for high speed digital electronic devices. The NbN/TaN/NbN trilayer films were prepared on a single crystal MgO substrate by pulsed laser ablation, and patterned into junctions using a novel process utilizing e-beam lithography, chemical vapor deposition and e-beam evaporation. The quality of junctions was tested by measuring the temperature dependence of the junctions' IcRn values, observed to be quite close to theoretical values.

The connection of RSFQ circuits with commercial room temperature electronics and amplifying SFQ pulses with high data rates require cryogenic interface amplifiers. Such amplifiers should provide extremely high bandwidth, low noise and low power consumption at the same time. Various hybrid amplifiers based on commercial p-HEMT transistors in an embedded microwave design were designed and characterized. Towards the p-HEMT transistor characterization at cryogenic temperature the biasing settings according to an optimum between voltage gain and low power consumption were determined. Thus a total power consumption of 2 mW and a voltage gain of 12 dB per single stage were achieved. For a preamplifier and an amplifier concept a multiple number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers, the combination of an amplifier with a RSFQ circuit at 4.2 K showed their good performances without any disturbance of the RSFQ circuit. Due to the losses between the stages a total gain of 25 dB with a four stage amplifier was achieved; pulse rates went up to 3 Gb/s. The total power consumption was in the range of 8 mW. Further increase of data rates will be achieved by improving the matching between RSFQ output stage and amplifier.

We have developed a sub-mum Nb/Al-AlNx/Nb Josephson junction and integrated circuit fabrication process using deep-UV lithography and inductively coupled plasma etch tools. The baseline process consists of 11 masking steps including ground plane, PdAu resistor, Nb/Al-AlNx/Nb trilayer, and two additional Nb wiring layers. The AlNx tunnel barriers are grown with plasma nitridation. These junctions exhibit low subgap leakage even at current densities exceeding 100 kA/cm2. The critical current spread of a series array of 50- kA/cm2, 0.6 mum diameter junctions is under 3%. For very high current density applications, these junctions are a good candidate to replace Nb/Al-AlOx/Nb junctions particularly in future generations of very high speed, rapid single flux quantum logic circuits. In this paper we discuss our baseline fabrication process and device characterization including junction capacitance extraction from direct measurements of the Josephson plasma frequency.

We propose a single-flux-quantum (SFQ) based readout circuit for a transition edge sensor (TES) array for X-ray radiation detection. Utilization of SFQ circuits for this purpose enables large-scale integration of TESs due to very high speed processing ability of the received signals and using an already established integrated circuit design environment. We utilize the cooling time dependence of the TES on the incident X-ray energy. Time to digital conversion is made by using an SFQ based quasi-one-junction SQUID (QOS), which works as a 1-bit comparator with an adjustable current threshold level, and an SFQ based high speed counter. The readout system is composed of two separate chips that are connected to each other with flexible superconducting wiring. The QOS-multiplexer chip is directly connected to the TES array and it performs the digital conversion of the TES output. The demultiplexer-counter chip, which will be placed at elevated temperatures, receives the multiplexed SFQ pulses and determines the duration of the TES output which is above the predetermined threshold level. Final goal of this work is to readout more than 10 k TES pixels and in this paper, feasibility of the system and current status of the development process is demonstrated.

An increase in bias currents supplied to single-flux-quantum (SFQ) circuits is a rising problem in building large-scale integrated SFQ circuits, because the magnetic fields generated by bias currents and ground return currents affect the circuit operation. Current recycling technique, which can drastically reduce the total bias current of SFQ circuits, is expected to be a very effective solution for large-scale SFQ circuits. To realize the current recycling technique, signal transmission between SFQ logic circuits located on different ground planes is required. Two types of inductively coupled pulse transfer circuits were examined in this study. One is composed of a simple JTL driver and a DC-SQUID receiver whose junctions are slightly under-damped to enhance the magnetic sensitivity of the SQUID. The other circuit is composed of an SFQ driver based on a delay flip-flop (DFF) and a SQUID receiver. The advantage of the DFF-based circuit is that the coupling time between the driver and the receiver can be increased to ensure appropriate switching in the receiver junction. Two types of transfer circuits were implemented using the SRL 2.5 kA/cm2 Nb process and their correct operation was experimentally confirmed. Circuit structures for effective coupling of the SFQ pulse transfer were also investigated. It was shown that a ground plane boundary should be separated from a ground plane hole underneath coupling inductors to obtain high coupling factors.

This paper investigates the robustness of different ground plane configurations of superconducting circuits against magnetic flux trapping. The robustness of the circuit is determined by the change of the error rate at a specific operating point under the influence of an external magnetic field. A large number of thermocycles are used to determine the statistic properties of the error rate. The proposed measurement setup allows a fast scan of a two-dimensional operating area.

The rapid single flux quantum electronics is characterized by a low switching energy, which makes it susceptible to noise introduced bit-errors. For industrial applications a certain noise immunity is required which is still a challenge especially for circuits of higher complexity. We analysed the influence of each individual resistor in a toggle flip-flop circuit to the overall bit-error rate. The shunt resistors of comparator structures are the dominant noise sources and bias resistors have almost no influence.

Reduction of total bias current using the serial biasing technique is required for RSFQ-based digital-RF receiver realization. This will have a major impact on reducing the size, weight and power consumption of the complete cryocooled receiver system. The approach is based on partitioning a homogeneous design into several isolated islands biased in series and transmitting SFQ pulses between islands, over moats through inductively-coupled driver-receiver-pairs (DRPs). Experimental data on testing of 100 DRPs connected in series are reported and bit-error-rate estimates are given. Our goal is to serially bias two sets of homogeneous circuit blocks in the digital-RF receiver design: (1) digital decimation filter (DDF) bit slices, and (2) output drivers. The correct operation of test chips containing four bit-slices of a second-order DDF, partitioned into 2 and 4 islands, are demonstrated. Results of 8 output drivers, serially biased on 2, 4, and 8 islands, are reported. Design issues of scaling to a digital-RF receiver, containing 18-20 DDF bit slices and 16 output drivers are discussed.

A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a Nb IC test chip, with cells that include a high-speed rapid single flux quantum (RSFQ) binary counter. For 650 W total compressor power, extended stable operation of the counter at T=4.5 K was demonstrated with a clock frequency up to 46 GHz, with 25 mW of excess cooling capacity on the coldest stage. The thermodynamic, electromagnetic, and mechanical performance are promising for the development of an improved compact cryocooler for practical superconducting electronic applications in fields such as wireless communications.

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2 HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed.

We present a new kind of rapid-single-flux-quantum (RSFQ) output driver together with a pseudomorphic high electron mobility transistor (p-HEMT) amplifier both operating at liquid helium temperature. The passive interconnect including the interchip connection between the RSFQ output driver and the first transistor stage of the semiconductor amplifier is the key element for signal matching and was optimized for minimizing the reflections to the RSFQ circuit. The RSFQ output driver is based on a single-flux-quantum to dc converter and a voltage doubler. The circuit is realized in the Niobium based 1 kA/cm2 process of FLUXONICS Foundry and provides up to 438-muV output voltage. We demonstrate high-speed experiments of the output driver in combination with two different semiconductor amplifier circuits at liquid helium temperature. The output voltage of a 2-Gb/s data stream was measured to be about 3.5 mV.

Superconductive single flux quantum (SFQ) circuits, which perform their circuit operations by controlling propagations of flux quanta in connected superconducting rings, can operate at the frequency of several tens GHz with ultra low power dissipation. The SFQ circuit is thought to be an attractive candidate for fundamental elements of future high-end information processing systems. This paper reports the development of SFQ microprocessors for high-end computation systems.

In this paper, we investigate the application of the asynchronous logic approach for the realization of ultra high-speed digital electronics with high complexity. We evaluate the possible physical, technological, and schematical origins of restrictions limiting such an application, and propose solutions for their overcoming. Although our considerations are based on the rapid single-flux quantum technique, the conclusions derived can be generalized about any type of digital information coding.

Direct measurements of propagation delay of single-flux-quantum (SFQ) circuits were performed using SFQ double-oscillator time-to-digital converters. The propagation delay of several SFQ logic gates in our cell library named CONNECT were measured in picosecond resolution. Small discrepancy in the propagation delay of picosecond level was observed between measurement and circuit simulation results. The discrepancy is well explained assuming the parasitic inductance around shunt resistors of Josephson junctions.

This paper presents the history of superconductor digital circuits starting from several years after the discovery of the Josephson junction in 1962. The first two decades were mainly devoted to developing voltage-state logic, which is similar to semiconductor logic. Research on circuits employing the manipulation of single magnetic flux quanta resulted in a form called RSFQ in the mid-1980s; this is the basis of superconductor logic systems of today. The more difficult problem of random access memory is reviewed. We analyze the present status of the field and outline the work that lies ahead to realize a successful superconductor digital technology.

We propose a desk-side supercomputer with large-scale reconfigurable data-paths (LSRDPs) using superconducting rapid single-flux-quantum (RSFQ) circuits. It has several sets of computing unit which consists of a general-purpose microprocessor, an LSRDP and a memory. An LSRDP consists of a lot of, e. g., a few thousand, floating-point units (FPUs) and operand routing networks (ORNs) which connect the FPUs. We reconfigure the LSRDP to fit a computation, i. e., a group of floating-point operations, which appears in a ‘for’ loop of numerical programs by setting the route in ORNs before the execution of the loop. We propose to implement the LSRDPs by RSFQ circuits. The processors and the memories can be implemented by semiconductor technology. We expect that a 10 TFLOPS supercomputer, as well as a refrigerating engine, will be housed in a desk-side rack, using a near-future RSFQ process technology, such as 0.35μm process.

Ultra fast switching speed of superconducting digital circuits enable realization of Digital Signal Processors with performance unattainable by any other technology. Based on rapid-single-flux technology (RSFQ) logic, these integrated circuits are capable of delivering high computation capacity up to 30 GOPS on a single processor and very short latency of 0.1 ns. There are two main applications of such hardware for practical telecommunication systems: filters for superconducting ADCs operating with digital RF data and recursive filters at baseband. The later of these allows functions such as multiuser detection for 3G WCDMA, equalization and channel precoding for 4G OFDM MIMO, and general blind detection. The performance gain is an increase in the cell capacity, quality of service, and transmitted data rate. The current status of the development of the RSFQ baseband DSP is discussed. Major components with operating speed of 30 GHz have been developed. Designs, test results, and future development of the complete systems including cryopackaging and CMOS interface are reviewed.

Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.

We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit., 9 pages, 4 figures

The main circuit components of RFSQ logic are based on overdamped Josephson junctions. They produce, store, transfer, and reproduce voltage pulses. These pulses are of picosecond duration. They have quantized area, which is correlated with the transmission of a single quantum of magnetic flux across a Josephson junction. According to superconductivity theory, the magnetic flux threading a superconducting loop or a hole in a bulk superconductor cannot acquire continuous values. It only assumes integral values which are multiples of a quantum of magnetic flux = h/(2q) where h stands for Plank’s constant and q is the elementary electronic charge. Its value is 2.0678 × 10−15 Wb = 2.07 mV ps. The RFSQ elements represent an ultrafast digital electronics technology working at 100–700 GHz, and beyond. Although it is consuming very low power, a disadvantage of this technology is the need of liquid helium environment, which is expensive even for military applications.

A wide variety of superconducting three-terminal devices is described. In order to control the superconducting current in Josephson junctions or source/drain channels, electric field, magnetic field, photo-irradiation, Joule heating, strain, or the injection of quasiparticles/Cooper pairs into the junction or the channel are utilized. These tree-terminal devices may find applications in microwave components and/or high-speed and low-power-consumption computings.

Improvement of integrated circuits and speed of computers concerned with their miniaturization demands considerable financial and mental power today. At the moment the innovation is limited by theoretical possibilities. It seems that new results can be reached by Josephson effects. The Josephson junctions consist of three layer instruments based on quantum tunnelling effect. The digital circuits based on the Josephson junction are developed in new ways. The first flip-flop led to ADC-DAC integrated circuits and further to microprocessors. Solving difficulties, the very high speed quantum computer based on Josephson junctions will be constructed in the first decade of this century.

This work describes the study of a superconducting quantum interference device (SQUID) with single-walled carbon nanotube (CNT) Josephson junctions. Quantum confinement in each junction induces a discrete quantum dot (QD) energy level structure, which can be controlled with two lateral electrostatic gates. The gates are also used to directly tune the quantum phase interference of the Cooper pairs circulating in the SQUID ring. Optimal modulation of the switching current with magnetic flux is achieved when both QD junctions are in the 'on' or 'off state. In particular, the SQUID design establishes that these CNT Josephson junctions can be used as gate-controlled π junctions. Besides, the CNT-SQUIDs are sensitive local magnetometers, which are very promising for the study of magnetization reversal of an individual magnetic particle or molecule placed on one of the two CNT Josephson junctions.

A vital precondition for the realization of rapid single-flux quantum (RSFQ) digital circuits with reduced critical currents of the Josephson junctions is the implementation of an efficient technique for superconductive phase dropping. In this paper, we present a novel phase shifting element consisting of a miniature superconductive ring located over a ground plane hole. Contrary to the solutions reported up to now, this topology can be simply integrated within complex digital RSFQ circuits realized with conventional fabrication technology.

A detailed design is given for a flux qubit readout using ballistic fluxons. In this scheme, fluxons propagate through an underdamped Josephson transmission line (JTL) coupled to the qubit, whose state affects the fluxon propagation time. For strong qubit–JTL coupling, and far from the symmetry point, a qubit can be measured with fidelity greater than 99% and measurement time of 4 ns. The readout circuit requires additional rapid single flux quantum (RSFQ) interface circuitry to launch and receive the delayed flux solitons. The parameters of this driver and receiver have been optimized to produce low fluxon speed at launch and impedance matching at the receiver. The delayed solitons are compared to a reference line using a detector with time resolution of better than 16 ps. Both the JTL and RSFQ interface were designed for the Nb 30 A cm^-2 process developed at VTT, Finland, with postdeposition of the Al qubit at IPHT, Germany

There is a great deal of interest in amplifiers with extremely high bandwidth, low noise and low power consumption which interface RSFQ circuits with commercial room temperature electronics or amplifying SFQ pulses. In this special application a hybrid amplifier should interface an RSFQ circuitry with a Josephson junction array quantizer chip (JA-Q) at 4.2 K. The input signal for the amplifier is generated by an RSFQ signal generator and the output signal fed-in to a Josephson array quantizer. A voltage gain of about 104 with a pattern frequency of 2 GHz for a good transfer of the SFQ pulses is required. Additionally, the JA-Q requires a high output current at low power consumption of the amplifier at the same time. Various hybrid amplifiers based on commercially available p-HEMT transistors in an embedded microwave design were designed and characterized. For the p-HEMT transistor characterization at cryogenic temperatures the biasing settings according to an optimum between voltage gain AV and low power consumption PV were determined. Thus a power consumption of PV = 2 mW and a voltage gain of about AV = 4 per stage were achieved. For a preamplifier and an amplifier concept a number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers and the combination of the amplifiers and the JA-Q at 4.2 K showed their good performance without any disturbances of the quantized voltage steps.

We measured the delay times of several components of the rapid single-flux-quantum (RSFQ) circuit using ring oscillators so as to improve the precision in the timing design. The delay time deviates from the designed value because of wafer-to-wafer and on-wafer parameter spreads. In addition, three-dimensional structures of the actual circuits generate unpredictable parasitic inductances, which occasionally lead to the large timing deviation from the design. The 1-σ local spread of the delay time originating from the fabrication was found to be 5.2% for a Josephson transmission line (JTL) composed of two junctions. This result provides a quantitative indication of timing margins required between SFQ pluses. However, the delay times tended to be smaller than those in numerical simulation by approximately 20%. We think that this is because the timing parameters were extracted without any considerations of the parasitic inductance of shunt resistors in the simulation. To examine the influence of the parasitic inductance, we designed four JTLs having additional inductances in series with shunt resistors, and measured each delay time. The decreasing ratio of delay time to the parasitic inductance was found to be 0.32 ps per 1 pH. We estimated that the parasitic inductance connected in series with a shunt resistor was 1.6 pH for the JTL. This timing consideration is applicable to all the cells because the junctions used in the actual circuits have roughly the same geometry as that of the JTL.