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The harmonic output of microwave lumped-element class-E load-coupling topologies is assessed. Measurement results on fabricated C-band class-E power amplifiers with either a modified lowpass and an optimised second-harmonic impedance network show that the latter provides better performance not only in terms of output power, gain and efficiency, but also in regard to harmonic suppression. Compared with the common modified lowpass network, harmonic content in the load of the optimised second-harmonic impedance topology at the second-, third- and fourth-harmonic frequencies are lower by more than 5.8, 10 and 5.8 dB, respectively.

This paper presents the analysis of effects and consequences of ESD on an operating integrated communication interface. We used a test structure for a differential bus module and observed its output signal behaviour under conducted ESD gun stress, to our knowledge for the first time. Measurements correlate to our simulations.

In this paper a V -band ultra-low-power currentreuse VCO is designed. The current-reuse topology can realize low-power consumption VCOs but the highest oscillation frequency is limited due to the use of PMOS transistor. The currentreuse negative transconductance (−gm) generator with boosting technique proposed in the paper is able to generate sufficient −gm. Hence, it reaches the oscillation condition and low power simultaneously. Due to the asymmetrical current-reuse topology, an amplitude compensation transistor is employed. A patternedgrounded- shield inductor is also adopted to improve the quality factor. The VCO is implemented in 65nm standard CMOS. The oscillation frequency is from 60.7GHz to 62.84 GHz and the phase noise at 61.8 GHz is −116.3 dBc/Hz at 10MHz offset. The DC power consumption is 0.98mW under a supply voltage of 1.2 V. A FOM of −188.9 is obtained.

This work presents the design and implementation of a fully integrated broadband medium power stacked amplifier in 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack to increase the output voltage swing along with the output impedance. The load impedance is further optimized with a resistive feedback which not only results in broadband operation but also avoids a lossy broadband output matching network which reduces area significantly. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier shows a measured peak saturated output power from 13 dBm to 8.5 dBm and a P1dB of 7 dBm to 4 dBm from 0.3 GHz to 10 GHz. The measured gain is 9 dB with a gain ripple of ±1.5 dB in the entire frequency range, yielding a fractional bandwidth of 188%. The measured load-pull −1 dB, −2 dB output power contours verify the optimum impedance around 50 Ω. The active chip area is only 0.44mm2.

This paper presents a design approach for frequency planning of a RF-DAC based transmitter, which combines digital-IF and RF-DAC architecture for the first time. With a proper frequency planning the achievable SFDR can be increased from 12 dB to 40 dB within a band of 800MHz at the center frequency of 2.4GHz without any additional circuitry effort. Spurs caused by harmonic mixing products of the IF and LO-signals are shifted out of the band of interest. The frequency planning is based on an optimization process, which delivers the IF and LO frequencies providing the highest SFDR at a certain transmit frequency. Therefore, a new FOM calculation is presented, which contains amplitude and frequency values of spurs with a Gaussian curve based weighting. The proposed structure introduced in this paper leads to a new class of SAW-less transmitters. Furthermore, the frequency planning and optimization method can be used for all kind of systems, which contains multiple frequency sources and lead to harmonic mixing products.

This paper presents a highly linear low-band 706MHz LTE compatible class-O RF power amplifier in 130nm CMOS technology for handheld wireless applications. Class-O topology uses a combination of common-source and common-drain amplifiers working in parallel with high linearity without the need for digital predistortion(DPD). With continuous wave measurements, 1-dB compression point (P1dB) of 30.6dBm and peak power added efficiency (PAE) of 45.2% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an ACPR less than −30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common-source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst VSWR conditions.

This paper presents the design and implementation of a compact wideband, lumped six-port receiver. The proposed six-port receiver operates at 2.4 GHz with a bandwidth of 600 MHz. The novel combination of the proposed architecture together with the lumped element implementation enables a wideband design with an EVM of 4.2%. It occupies significantly less area compared to a conventional hybrid implementation at these frequencies making it more suitable for integration. The design is demonstrated on a PCB and its capabilities are verified by demodulating 16-QAM signal across the 2.1 − 2.7 GHz band.

This paper presents the concept and measurements of a new microwave rectifier based on the time reversal duality of power amplifiers. It is shown that the proposed rectifier can simultaneously provide high efficiency at large input power range over much more improved bandwidth compared to the conventional rectifier from time reversal duality. It is also reported that the proposed rectifier allows reconfiguration of the efficiency at input power range without placing the tunable elements. A 10 W wideband power amplifier with 79%drain efficiency at 1.85 GHz is used to validate the concept. By making the gate bias network short-terminated and replacing the drain termination with the DC load resistor for power amplifier, the circuit can operate as microwave rectifier with taking part of bandwidth from power amplifier. Measurements show the efficiency bandwidth with larger than 70 % rectifying efficiency at 15 dB input power range over a 1.7–1.95 GHz frequency range. The measurements thereby validate the presented concept and demonstrate the potential of the proposed rectifier for use in future wireless energy harvesting applications.

A wideband, six-port, direct-conversion receiver operating between 0.9 GHz and 5 GHz is presented. It employs distributed power detectors that achieve good matching up to 4 GHz and more than twice the sensitivity as compared to a resistive-matching detector. Comparison of the proposed receiver to one employing resistive-matching detectors, is also presented. The proposed design is able to deliver comparably higher data-rates for a given EVM. Alternately, it provides better EVM for the same data-rate. Measurement results demonstrate the successful demodulation of a 200 Mbps, 16 QAM signal operating at a carrier-frequency of 2.4 GHz.

This work presents a loss compensated cascaded single-stage distributed amplifier (CSSDA) in commercial 65nm CMOS technology. The CSSDA is composed of three distributed stages connected in a cascade configuration to target high gain. The idle interstage drain terminations are omitted because of multiplicative gain mechanism. High gain is maintained over very large bandwidth through the inductive-peaking technique. Further, the CSSDA single cell is modified by a loss compensation technique to remove the high frequency losses of the artificial transmission lines which shows a significant enhancement in gain bandwidth (GBW) product. The simulation results show a GBW of 540GHz for the loss compensated CSSDA (LC-CSSDA) which is significantly higher than GBW of 350 GHz for a conventional CSSDA. The 2-stage (LC-CSSDA) shows a GBW of 835GHz which is almost twice the GBW (426 GHz) of a conventional 2-stage CSSDA.

This paper presents a 3-dB coupler providing 90° output phase-difference over wider bandwidth compared to other single-stage planar couplers. The proposed design is suited for the applications where high power RF signals need to be combined with quadrature phase. It uses a symmetric rat-race coupler to achieve wider bandwidth as compared to its asymmetric counterparts. The proposed coupler has a measured peak-to-peak phase-deviation of 16° and a magnitude-imbalance of lower than 0.5 dB over the entire bandwidth spanning 2 GHz to 3 GHz. The measurement results comparing the proposed coupler with a) a branch-line coupler, b) a rat-race coupler employing a Schiffman phase-shifter and c) a Wilkinson power-divider cascaded with the Schiffman phase-shifter, are also presented.

Current-handling capability of interconnection lines must be considered to avoid electromigration. In monolithic design, all design rules have to be rigorously followed which indicates that the maximum metal width is limited. In order to handle high current and simultaneously obey the design rules, stacked and mesh interconnections are employed. In this paper five coplanar waveguides (CPWs) for high current-handling are investigated using a commercial CMOS technology. The measurement shows that a mesh CPW reaches lower attenuation constant than stacking of metals under similar current carrying capability. The lowest measured attenuation is 0.81 dB/mm at 10 GHz and 1.46 dB/mm at 40 GHz in a mesh CPW, which can continuously flow a DC current of 145 mA without electromigration.

This paper describes an available graphene process with respect to material properties and also the work in progress to complete the graphene process back-end implementation to be MMIC-compatible. This process extension is critical to enable fully integrated circuits and systems based on graphene transistors. A stable process back-end is proposed, characterized and tested on both silicon and quartz substrates. Based on this, a process cross-section is now available for EM simulations. A prototype chip of RF passive devices including spiral inductors, MIM capacitors and thin film resistors, TFRs, is fabricated and measured on both substrates. On-wafer measurements of the fabricated passive devices up to 30 GHz show good agreement with EM simulation results.

In this paper, a digital up-sampling technique is presented for digital communication transmitters. This method allows to up-sample the I/Q baseband modulated signals to an intermediate frequency based on a 4∶1 multiplexing technique, before being again up-converted at the carrier frequency. The frequency conversion is made in two steps and permits to avoid the nonlinear behavior of direct up-converting architectures. Also, the mutual coupling between the output power amplifier (PA) and the phase-locked loop (PLL) can be reduced by choosing the local oscillator frequency (LO) far enough from the carrier output frequency. A fully integrated CMOS transmitter with an on chip PA is thus becoming feasible. A PLL at the frequency of 4.8 GHz has been designed in a 65 nm CMOS process along with a digital 4∶1 multiplexer in order to target the band-VII Long Term Evolution (LTE) applications in the 2.55 GHz frequency.

Integration of RF transceiver blocks along with the digital signal processing part in CMOS is becoming the trend in the semiconductor industry for lower cost and smaller form factor. Nowadays, the interest is even growing towards implementing the RF PA in CMOS technology. Cost reduction, diversifying means of fabrication and the addition of performance enhancement circuitry are the main reasons behind this growing interest. However, implementing RF PAs for 3G/4G standards in CMOS is quite challenging: The low breakdown voltage of nanoscale CMOS causes a ruggedness problem at typical average output power (P avg ) levels of 26dBm or more. In [1,2], power-combining techniques were used to reach PA output power (P out ) of 33dBm. However, amplification of signals with high peak-to-average-power-ratio (PAPR) requires also a high degree of linearity. Significant AM-PM distortions caused by the voltage-dependent parasitics are a fundamental problem in CMOS PAs. Thus far, predistortion is used to meet EVM requirements [2]. To overcome these challenges, this work presents a new class of operation, termed as Class-O, demonstrated by the design and the measurement of a single-stage PA implemented in 0.13μm CMOS and operating from a 3.3V supply.

This paper presents an analysis for the impedance transformation ratio of microwave rectifier, implemented as an energy recycling unit suitable for RF outphasing transmitters. The experimental demonstration is realised by two single-ended microwave rectifiers with different impedance transformation ratios to separately replace the power-wasting resistive load of an isolating combiner in a multilevel LINC system. The measurement results show that the implemented rectifier can improve the overall efficiency of the multilevel LINC system from original 39.5 % to 46.7 % and 44.9 % respectively, without affecting linearity.

A prototype of a wideband six-port receiver is presented. It consists of three multilayer elliptical microstrip-slot directional couplers (MSDCs), a power divider and reactive-matching power detectors. To compose the receiver using MSDCs, a controlled-impedance via is required. The via, taken advantage of the multilayer structure, reaches a bandwidth of more than 190% and low insertion loss. 64-QAM signals with different data rates are fed for testing. From 0.5 GHz to 5 GHz the measured EVM is less than 4% with 1 Mbps data rate. The operation frequency covers many commercial standards and thus, the concept is suitable for cognitive radio application. A sensitivity of −52dBm and −58dBm is achieved at 0.9 GHz and 2.4 GHz, respectively, without LNAs.

This paper presents a design-oriented analysis of two lumped-element load-coupling topologies, which can be used to approximate class-E switching conditions. The presented output circuits are compared theoretically and experimentally with respect to harmonic termination and component values. Using a commercial BiCMOS process, two monolithic integrated class-E power amplifiers (PAs) have been designed and fabricated for operation at 5-6 GHz based on these load-coupling circuits. The PAs show an output power of over 19.7 dBm and power-added efficiency greater than 43.6% when operated from a 3-V supply. The results obtained with these first prototypes, operating at C-band, show the feasibility of the proposed lumped-element class-E networks

This paper presents a low power and low phase noise if-band VCO using 180 nm CMOS and integrated passive device (IPD) technologies. The cross-coupling circuit in this design is composed of P-type MOSs instead of N-type. Employing PMOS results in lower flicker noise but reduces the negative transconductance (−g m ). Since the IPD inductor has low parasitic resistance, the −g m generated using PMOSs can fulfill the oscillation condition for the A>band VCO. Moreover, the high-Q IPD inductor is beneficial to phase noise. The flip-chip technique is applied to assemble the CMOS and IPD structures. The oscillation frequency is from 22.6 GHz to 24.5 GHz and the minimum phase noise is −111.4 dBc/Hz at 1 MHz offset. The DC power consumption is as low as 3.4 mW from a supply voltage of IV.

This paper studies the impact of bandwidth limita- tion on the linearity of multilevel LINC (ML-LINC) transmitter. By using the signals with discrete levels for characterisation, both amplitude and phase dispersions around levels can be observed, which result in the degradation of system linearity. It is also shown that improvement on both adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) can be obtained by either increasing the number of levels or system bandwidth in each amplification path. A measurement setup including two highly efficient power amplifiers (PAs) in GaN technology, which delivers 41 dBm output power with drain efficiency of 69% at 2.05 GHz, is built to verify the analysis. With the configuration of 16 levels and 80 MHz system bandwidth, the built ML- LINC transmitter gives 36 dBm average output power with 54% drain efficiency after calibration for the standard 5 MHz LTE downlink signal with a PAPR of 7. 5d B. The measured ACLR is −50.5 dBc and EVM is 1.6% for QPSK and 3.1% for 64-QAM with enough margin left according to the standard.

This paper presents the design and implementation of a broadband 3-way sequential-based Doherty power amplifier (DPA). This design approach can also be extended for a broadband N-way DPA architecture. A 12 - 23.5 W 3-way DPA has been designed, implemented and characterised to verify the proposed technique. The measured drain efficiency of 55 - 69 % over 500 MHz at 12 - 14 dB output power backoff (OBO) and 60 - 75 % over 600 MHz at saturation is achieved. Single-tone measurement at 2.1 GHz exhibits a drain efficiency of 63 %, 62.5 % and 75 % at 13.6 dB, 6 dB and 0 dB OBO, respectively. Also at this frequency, linearised measurement with a 10 MHz-LTE signal having a crest factor of 8.2 dB shows an average drain efficiency of 59 % and adjacent channel leakage ratio (ACLR) better than -45.5/ - 45.7 dBc at an average output power of 34.5 dBm. To the best knowledge of the authors, this is the first broadband 3-way sequential Doherty power amplifier with such high performance reported so far.

This paper proposes an iterative calibration technique to enhance the linearity for multilevel LINC transmitters. With this approach, the precision of characterising AM/AM and AM/PM behaviours for discrete levels can be improved, which results in better adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) performance. An ML-LINC transmitter is built with two PAs in GaN technology, which delivers 40.8 dBm output power with 68% drain efficiency at 2.05 GHz. Up to 5 dB ACLR improvement can be observed by iterative calibration using S1/S2 for a 5 MHz LTE signals. The configuration with 16 levels can give satisfying linearity performance to meet the standard specification, while keep the complexity reasonable. Measurement results show an ACLR of -46 dBc, EVM of 1.9% (QPSK) and 4.2% (64-QAM) at average output power of 35.7 dBm with 51.1% drain efficiency for a 10 MHz LTE signals with a PAPR of 7.9 dB. The performance of the built ML-LINC tranmitter is compared to the state-of-the-art. Both the linearity and drain efficiency are quite competitive.

This work presents a digital centric transmitter in a 65nm CMOS technology. The transmitter contains an RF-DAC frontend, a 3.2 Gbps interface, a fractional resampling pulse shape filter (PSF), LO feedthrough- and IQ-phase/gain-mismatch compensation. The PSF converts the XTAL based baseband clock to the independent LO clock domain. The 9 bit RF-DAC frontend occupies 0.18 mm 2 . The SSB sinusoid output power of the transmitter frontend reaches 11.9 dBm at 2.4 GHz. The transmitter system fulfills all WLAN requirements at 2.4 GHz ISM band with an output power of 0.5 dBm and a power dissipation of 92.6 mW. It also enables WCDMA and LTE transmission, resulting in 4.7 dBm/89mW in WCDMA mode and 2.5dBm/86.7mW in LTE mode respectively. In all cases the proposed design meets all ACLR requirements.

This paper proposes a novel implementation of a high frequency rectifier, which is realised using the simplified real frequency technique. The optimum impedances presented at the diode package plane are found from source-pull simulation over a broad frequency range. The implemented broadband rectifiers show good performance in terms of efficiency and bandwidth. Using a HSMS 2820 Schottky diode device, greater than 50 % efficiency has been measured from 1.25 GHz to 2.25 GHz. Furthermore, greater than 60 % efficiency with 14 dB (from 12 dBm to 26 dBm) input power dynamic range is achieved at 1.8 GHz. Peak efficiency of 77 % is obtained at the input power of 23 dBm. The high efficiency over such a large bandwidth is believed to be the best reported to data in open literature at these frequencies.

This paper proposes a filter realised using only lumped-element components, implemented as a highly selective bandpass filter suitable for lowpass delta-sigma (LPΔΣ) RF transmitters. The proposed filter is characterised by low insertion loss, high selectivity and a transfer function tailored for filtering the close-up out-of-band noise of LPΔΣ RF transmitters. The circuit design is based on a modified loaded-stub ring-resonator structure, however, implemented using 4 π-shape lumped-element resonators with LC tanks. The measurements show good agreement with simulation and the proposed filter provides a fractional 3-dB bandwidth of 14.3 %, insertion loss of less than 1.6 dB, suppression of more than 18 dB on both sides of the desired band, and a sharp cut-off frequency response. This filter is combined with the delta-sigma transmitter to show the effective reduction of the out-of-band quantisation noise signals.

This paper presents a stacked inverter-based amplifier in a commercial 65nm CMOS technology. The proposed amplifier, based on an inverter, uses stacking to achieve high output swing and distributed inductive peaking to obtain ultra-wide bandwidth. Furthermore, the proposed topology is generalized for more stacked transistors for high output swing requirement which then utilizes distributive peaking inductors to maintain that swing over a large bandwidth. The simulated output swing for a 2-, 4- and 6-stacked amplifier is 4.0 V, 6.5 V and 8.0 V with 3 dB-voltage bandwidth of 50 GHz, 43 GHz and 41.5 GHz, respectively. All transistors are regular RF MOSFETs with a 1.2 V supply voltage.

This paper presents the design and experimental results of a broadband sequential Doherty power amplifier (S-DPA). This new type of DPA allows large back-off (BO), highly efficient and broadband DPAs to be realised. A 10 W/10 dB BO S-DPA is designed to verify the design concept. Measurement results show obvious Doherty behaviour with 8 – 11 dB output power back-off over a 1.85 – 2.4 GHz frequency range. A drain efficiency of 65 % over 300 MHz at BO and ≥ 58 % over 500 MHz bandwidth at saturation is obtained. To show the state-of-the-art of the S-DPA, the drain efficiency at 2.0 GHz is selected with 74.5 % at saturation and 67.3 % at 10 dB BO. Linearised measurement with a 10 MHz LTE signal having a crest factor of 7.5 dB at 2.1 GHz exhibits an average drain efficiency of 53 % and an adjacent channel leakage ratio (ACLR) of −44.2/ − 48.7 dBc at an average output power of 32.7 dBm. To the best of the author's knowledge, this is the first wideband, 10 dB BO DPA with such high efficiency reported so far.

Power amplifiers (PAs) in CMOS technology have drawn considerable interest for meeting 4th generation (4 G) wireless standards due to their low cost and high level of integration. At increasing power levels, (around 1 W), it becomes challenging to meet the linearity constraints. In this paper, we investigate a differential common source class-AB RF PA employing floating body and compare it with a body-source shorted version. We use triple-well NMOS RF devices at 1.6 GHz in 130nm CMOS technology. Linearity is improved for the floating body based amplifier in terms of AM/PM and 3rd order intermodulation (IMD 3 ) suppression by 1.8° and 1.5 dBc at P 1dB as compared to a body-source shorted amplifier. The linearity is evident over all output power (P out ) levels. The linear gain is reduced by 0.42 dB due to increased coupling between drain and source terminals while the PAE is increased by 1.6% at P 1dB for floating body based amplifier.

This paper presents a new mismatch calibration technique for outphasing transmitters by means of instantaneous measurement characterisation. Results will show that by creating a model of the instantaneous measurements, the gain and phase imbalance between the outphasing paths can be fully compensated using only a single iteration. A multilevel-outphasing transmitter is implemented using 10 W GaN devices at 1.9 GHz. An ACPR performance of −51 dBc and −47 dBc are obtained for 1.4 MHz and 10 MHz LTE signals with a PAPR of 10 dB, respectively, while delivering 2 W average output power without requiring any form of predistortion.

In this paper, a dual-band wide-tuning-range quadrature VCO (QVCO) using a harmonic-injection coupling technique is proposed. The tuning range of a switched-capacitor and a switched-inductor LC-tank are investigated. Based on the investigation, a switched-inductor tank is employed since it provides a wide tuning range. A harmonic-injection coupling technique, which eliminates the noise sources of coupling transistors, is applied to generate the quadrature outputs. The QVCO is designed for 3.5GHz WiMAX and 2.4 GHz ISM applications. A tuning range of 24.9% and 20.7% are obtained. The measured phase noise is −123.5 dBc/Hz and −125.9 dBc/Hz at a 1MHz offset, respectively. Significant FOMT of −191.7 and −192.4 are achieved.

Six-port receivers have increasingly become popular due to their simple design, wide bandwidth and low power consumption. Large area and narrow dynamic range are the key factors in limiting the use of six-port topology in commercial mobile communication devices. In order to improve its dynamic range, we propose an L-type reactive matching network for the detector stage of the six-port receiver. The proposed six-port receiver covers the frequency band from 1 GHz to 3.3 GHz. Over the specified band, it has an EVM of less than 4 % with −20 dBm of RF input power and 15 dBm of LO power. At 2.2 GHz, it has 64 dB of dynamic range with EVM between 0.33 % and 10.5 %.

A novel large-signal gallium nitride (GaN) high electron mobility transistor (HEMT) model that focuses on and improves analysis and design of switching-mode power amplifiers (PAs) is presented in this letter. The proposed model can be constructed using standard DC and AC characterization measurements and easily implemented in any computer-aided design (CAD) software to simulate and design switching-mode amplifiers. The model can predict the behavior of a switching-mode PA accurately at saturation and, due to the proposed approach, also well in the weak compression region. Using the developed model, an inverse class-F PA is designed and fabricated for validation purposes. The prototype developed using the proposed model achieved power-added efficiency (PAE) of 67% for an output power of 36.7 dBm at 2.35 GHz. Comparison between simulation and measured results of the manufactured PA proves the validity and accuracy of the proposed model.

We propose a load network, consisting of an optimized impedance transformer, for a Doherty amplifier. This load network allows the carrier and peaking amplifiers to have different load impedance. This results in better IM3 cancellation. Using a four-carrier down-link WCDMA signal, we achieved 0.95 dB higher output power level and 2.21% higher power-added efficiency compared to a conventional Doherty amplifier at an ACLR level of −30 dBc. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2502–2504, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24657

A triple cascaded current-reuse CMOS low noise amplifier (LNA) for 3.5 GHz WiMAX application is presented. Three common-source amplifiers are stacked and reuse the same current. This triple cascaded topology is able to enhance power gain but needs two coupling networks which costs enormous chip size. In order to have reasonable chip size, two coupling methods are investigated. To achieve input and noise matching simultaneously, an additional capacitor is employed to adjust quality factor and reduce the gate induced current noise. The measurement results show a maximum power gain of 21.7 dB and minimum noise figure of 3.11 dB. The power consumption is 5.16 mW. The chip including pads occupies 1.05 mm × 0.93 mm. A figure-of-merit of 49.7 is reached.

This paper analyses the impact of the level locations in a multilevel LINC transmitter on the obtainable linearity performance. Results show that by placing levels in the upper dynamic region of outphased signals, a linearity performance suitable for LTE applications and beyond can be achieved. A multilevel LINC transmitter with 5 levels is implemented using 10 W GaN CREE devices at 1.9 GHz. A 10 dB PAPR 1.4 MHz LTE signal is decomposed for outphasing and recombined to achieve an ACPR performance of -50 dBc while delivering 2 W average output power.

In this work, a steady-state analysis and a fast optimisation approach based upon it are implemented to analyse the class-E PA. With this approach, the component values and performance of class-E PA with RFC and parallel-circuit load (PCL) are analysed and compared. One fast search approach is developed for various constrained/unconstrained optimisations. The analysis, fast optimisation approach and evaluation as well are implemented in Matlab©. The feasibility, flexibility and fast-simulation are shown by comparing the RFC and PCL for a 1 W class-E PA design. All the results show good match with ADS©harmonic balance.

This paper presents the design and measurement results of a quad-band Doherty power amplifier (DPA) for concurrent operation in the 900 MHz, 1.5 GHz, 2.1 GHz and 2.6 GHz frequency bands. In principle, a quad-band DPA requires that all passive structures involving the DPA, but especially the impedance inverter network (IIN), be either broad-or multiband to cover the desired number of frequency bands. In this work, a newly developed multiband IIN is introduced, enabling the realisation of multiband symmetric and asymmetric DPAs. The design concept can theoretically be applied for a large number of frequency bands. The approach has been validated in hybrid technology using a 10 W and 25 W GaN-HEMT as carrier and peaking devices, respectively. The measured results show peak drain efficiencies of 58.12 %, 60.52 %, 52.74 %, and 43.3 %, associated with output powers of greater than 41.75 dBm in all four bands. The corresponding drain efficiencies at 6 dB output power back-off are measured to be 48 %, 56 %, 47 % and 31.8 % for the first, second, third, and fourth band, respectively. To the best of our knowledge, this is the first time a quad-band concurrent DPA has been successfully designed and implemented.

This paper analyses an energy-efficient multilevel LINC transmitter with low complexity. Compared with a conventional multilevel LINC using a supply modulator, a new architecture to realise multiple levels is analysed. With this architecture, distortion caused by delay mismatch and memory effects caused by the limited bandwidth of PAs can be mitigated resulting in improved out-of-band emissions. A system analysis shows the improvement of performance regarding efficiency, spectrum and ACLR in presence of delay mismatch and system bandwidth limitations. The analysis at system level is verified by measurements complying with 3GPP LTE specification. An improvement of 17 dB in out-of-band emission is observed by increasing the number of levels from 1 to 40. Meanwhile, average efficiency is also increased from 12 % to 42 %.

This paper presents a low power high performance frequency synthesizer. Based on the current-reuse VCO architecture, the whole system power consumption is significantly saved with excellent phase noise performance. Imbalance amplitude problems caused by the unsymmetrical VCO are solved by the pre-tuning mechanism, which automatically chooses the correct frequency band for the certain frequency channel. Besides, the symmetric charge pump (CP) can minimize the current mismatches and phase offset. The frequency synthesizer is fully integrated in 130-nm CMOS technology consuming 5.8 mW. Measurement results show performance of -130 dBc/Hz at 1 MHz offset phase noise, 450 fs rms jitter. The reference spur is below -75dB, and it operates successfully with 1Mbps GFSK signals as the two-point modulated transmitter.

This paper presents a dual-band rectifying circuit for wireless power transmission working at 2.45 GHz and 5.8 GHz. A modified dual-band matching network is adopted to realize the highly efficient dual-band rectifier. Source-pull simulations are performed, to determine the proper impedances at the two different frequencies. The proposed dual-band rectifier has been implemented and the measurements show good agreement with simulation. With a dual-band input matching network, the measurement results for an input power level of 10 mW show peak RF-to-DC efficiencies of 66.8% and 51.5% at 2.45 GHz and 5.8 GHz, respectively.

This paper presents a digital centric transmitter architecture with clock domain transition from the baseband clock to a clock derived from the local oscillator of the proposed transmitter. Both clock domains are asynchronous and variable in general, hence this transistion block represents the key building block of the digital signal processing chain. It consists of a synchronizing stage, a timing control unit, and a modified Generalized Farrow upsample filter which allows to implement further upsample stages using simple integer-ratio CIC filters. The architecture is well appropriate for low energy digital-centric hardware designs. Highly reconfigurable, it is applied in a state-of-the-art multimode multistandard transmitter with radio frequency DAC frontend, suitable for WLAN, UMTS, LTE and other recent standards.

This paper proposes a highly selective bandpass filter suitable for lowpass delta-sigma RF transmitters. The proposed filter is characterized by a low insertion loss, high selectivity and a transfer function tailored for filtering the close-up out-of-band noise of lowpass delta-sigma transmitters. The circuit design is based on a modified stub-loaded ring resonator structure. The proposed filter has been implemented and the measurements show good agreement with simulation. The proposed filter provides a fractional 3-dB bandwidth of 14.6 %, an insertion loss of less than 1.3 dB, a suppression of more than 15 dB on both sides of desired band, and a sharp cut-off frequency response.

The behavior of a 5.2-GHz transmit antenna array in time division multiple acess operation is investigated, where the power amplifiers are only switched on during the data bursts. Using monolithically integrated power amplifiers, two thermal time-constants are found, associated with gain and phase changes that alter the antenna pattern. In this letter, the correlation of these changes between multiple channels is experimentally studied to derive guidelines for the calibration of such an array. It is found that changes within the typical burst duration are well correlated and no time-dependent calibration is needed. Thermal changes linked to a second time-constant lead to a calibration error.

In this paper, a novel design approach of a concurrent tri-band Doherty power amplifier (DPA) for the frequency bands at 1.49 GHz, 2.14 GHz and 2.64 GHz is presented. To the best of our knowledge, this is the first time that a concurrent tri-band DPA has been successfully designed and implemented. The design concept can be extended to cover a large number of frequency bands. In order to make a tri-band DPA feasible, all passive structures involving the DPA, especially the tri-band Impedance Inverter Network (IIN), must be designed such that they fulfil the tri-band operation requirements. A tri-band approach is validated in hybrid technology using a 10 W and a 25 W GaN-HEMTs for the carrier and peaking PA, respectively. The measured results show peak drain efficiencies of 61 %, 58.1 % and 46.1 % and the corresponding 6 dB output power back-off (OBO) efficiencies of 50.3 %, 39.45 % and 28.3% and the output power of 45.2 dBm, 43 dBm and 41.5 dBm for the first, second and third band, respectively.

This paper presents the RF characterization and modeling of a back-gated graphene field effect transistor (GFET) embedded in a coplanar waveguide (CPW). The electromagnetic model (EM) of the graphene structure includes both channel and metal/graphene contact resistances as well as all involved parasitic capacitances. The S-parameters of the resulting structures have been measured at room temperature in the frequency range from 10 MHz to 67 GHz for back-gate voltages up to 37 V. Measurements show a roughly back-gate independent contact resistance (∼ 900 Ωμm) and a highly rise in channel resistance from 20 Ω to 2.34 kΩ when increasing the back-gate voltage from 0 V to 37 V (Dirac point). Moreover, the associated capacitance decreases from 4.1 fF to 0.7 fF for the same voltage range. The simulation results of the electromagnetic model from the CPW together with the graphene structure are in reasonable well agreement with our measurements.

The paper presents an implementation of a linear supply modulator with high dynamic range and bandwidth in polar transmitter for LTE applications. The design starts with the analysis of specification requirements for LTE standard signals. Based upon this, a linear supply modulator with power amplifier is designed and implemented in 130 nm technology, achieving a dynamic range of 23 dB and an average efficiency of 18.0 % at 6 dB back-off power. The performance is also verified by using 5 MHz LTE modulated signals without any predistortion techniques. Simulation results show an average EVM of 3.0 % and more than 10 dB margin to spectrum emission mask.

This paper presents a novel energy-efficient multi-standard multilevel LINC transmitter architecture. The proposed system is able to provide a large number of reconfigurable multiple levels by arbitrarily controlling the output power of the two efficient power amplifiers. The novelty of the architecture relies in the efficient generation of the arbitrary multilevels. In fact, the system uses only one fixed supply voltage. An algorithm is developed to optimise the different symmetrical levels depending on the actual signal statistics in order to boost average system efficiency. A multilevel LINC transmitter system demonstrator was build to validate the proposed concept. Besides The system employs two identical hybrid power amplifiers designed using GaN HEMTs for a centre frequency of 2.28 GHz and output power of 40 dBm, the system employs only off-the-shelf components or measurement equipment. Measurement results on the demonstrator show that compared with a conventional LINC transmitter, average power efficiency of the proposed system can be improved from 28 % to 41 % for a WCDMA signal with a measured adjacent-channel-power ratio (ACPR) below −45 dBc. For a 10 MHz LTE signal efficiency is improved by nearly 24 percentage-points compared with a regular LINC system.

In this paper, a new technique for designing concurrent multiband biasing networks for multiband RF power amplifiers is presented. The proposed design technique can theoretically be applied for a large number of frequency bands. The biasing network (BN) is composed of a transmission line and high impedance quaterwave open stubs (QWOS) that are located at appropriate positions along the transmission line. Two tri-band BNs for 1.49 GHz, 2.15 GHz and 2.65 GHz frequencies were designed, fabricated and display very good performance with regard to the input impedance seen looking toward the BNs from the active devices, such as FETs, are approximately open for all three bands. For demonstration, a 10 W Class-AB tri-band power amplifier (PA) using the proposed technique was implemented, characterized and exhibits high output power of more than 40 dBm and maximum power added efficiency (PAE) of over 50 % in all the three bands.