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The development of intrinsically stretchable polymer semiconductor holds substantial promise in the field of wearable electronics. However, charge transport mobility is typically compromised in existing stretchable semiconductors to achieve the desired stretchability. Herein, a novel "regional conjugation" strategy is proposed to design an intrinsically stretchable polymer semiconductor oligo‐diketopyrrolopyrrole‐thieno[3,2‐b]thiophene (DPPTT)–urethane, in which oligo‐DPPTT conjugated units and alkyl urethane nonconjugated units are introduced. The regional conjugation of oligo‐DPPTT in the polymer backbone endows DPPTT–urethane with good molecular packing, leading to a high mobility of up to 1.7 cm2 V−1 s−1. Additionally, incorporating alkyl urethane nonconjugated units in the backbone can reduce film crystallinity and chain aggregation, which contribute to the stretchability of the polymer thin film. Consequently, fully stretchable transistors retain carrier mobility even at 100% biaxial tensile strain. Furthermore, the fully stretchable organic field‐effect transistor arrays show remarkable charge transport reversibility and durability after 1000 stretch–release cycles at 25% strain. Additionally, the device exhibits extraordinary electrical stability in air atmosphere. Overall, these results indicate that the "regional conjugation" strategy provides an effective and promising methodology to design intrinsically stretchable and high‐performance polymer semiconductor that can advance the development of soft and wearable electronics. [ABSTRACT FROM AUTHOR]

This paper presents a sub-1-V CMOS bandgap reference circuit with ultra-low power consumption, utilizing only 9 MOS transistors. The proposed circuit achieves nano-watt power consumption by biasing all transistors in the sub-threshold region. A three-branched configuration is utilized to create the bandgap voltage reference in the circuit. The proposed architecture generates CTAT and PTAT voltages without using any op-amp and BJT. In this circuit, the cascode structure are used to improve the line sensitivity (LS). In the proposed bandgap circuit, self-biased configuration is used without using an external bias circuitry. The first branch generates PTAT current and the second and third branches generate PTAT and CTAT voltages. The bandgap circuit is designed and simulated using Cadence in TSMC 0.18 μm CMOS technology. The results of post-layout simulation indicate that the bandgap voltage reference circuit generates a voltage reference of 644 mV, with a temperature coefficient (TC) of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The proposed circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. Furthermore, the circuit exhibits a line sensitivity of 0.31%/V for power supply voltages ranging from 0.9 to 1.8 V. The Power Supply Ripple Rejection (PSRR) of the proposed circuit is about − 40 dB within the frequency range of 1–100 Hz. [ABSTRACT FROM AUTHOR]

The conventional planar Metal-Oxide-Semiconductor FETs (MOSFETs) are being replaced with Fin Field-Effect Transistors (FinFETs) due to their improved ability to manage power dissipation, propagation delay, leakage current, and short channel effects. Process variability is an issue for planar MOSFETs, however the amount of dopant ions in FinFETs reduces device performance variability. In this study, a Static-Random Access Memory (SRAM) cell employing FinFET technology is designed using three MOS transistors. It is composed of two NMOS plus a single PMOS transistor. One NMOS acts as access transistor while the pull-up and pull-down functions are performed by remaining NMOS and PMOS transistors, respectively. The proposed SRAM cell is simulated using H-SPICE simulator and is compared with existing SRAM cell designs in terms delay, power consumption and transistor count. Performance analysis shows that the proposed SRAM Cell overcomes the constraint and achieves full swing storage of logic values between 0 and 1. This justifies the definition of static. Implementing a single-ended SRAM cell also has the benefit of simplifying the SRAM cell architecture, which also results in a reduction in area. [ABSTRACT FROM AUTHOR]

To elucidate the internal chemical physics of measured CMOS-compatible electrochemical random-access memory (ECRAM) devices, we constructed a 2D semiconductor device simulation, including ions and electrochemical reactions, and used it to fit measured devices. We present the results of a device simulation model that includes Cu+ ions' diffusion and the charge transfer reaction between the WOx conduction band electron and Cu+ (i.e., "Cu plating"). Reproducing the linear response of ECRAM devices, the effect of charging HfOx by the Cu+ ions is sufficient, and WOx is not being doped by the Cu+ ions. While potentiation is supported by the formation of an electron channel, an efficient depression requires the formation of high positive charge density at the channel material. At higher Cu+ flux, Cu+ reaches and penetrates the WOx layer. While this effect enhances the potentiation response, it also initiates the "plating" reactions. Including this reaction is essential to reproducing the data of devices exhibiting sub-linear responses. We suggest that electron trapping by ions (i.e., plating) would constitute a long-term degradation process even for H+ based devices. [ABSTRACT FROM AUTHOR]

All-solid-state electric double-layer (EDL) thin-film transistors (TFTs) consisting of solution-processed LaZrO gate insulators and sputtered InO channels with thicknesses of 10–200 nm were prepared, and their microstructures and electrical properties were investigated. In addition, mobility, carrier concentration, and their gate-voltage dependence in the InO layer were analyzed during a transistor operation to clarify the electron transport properties. It was confirmed that LaZrO was amorphous and that InO crystallized and had an In2O3 bixbyite structure. The transfer conductance increased with the InO thickness, and its normalized value was maximized (3.6 mS/V) at an InO thickness of 200 nm. The maximum capacitance of LaZrO was 31 μF/cm2, strongly suggesting the formation of an EDL. Solid EDL-TFTs operated stably without deterioration at gate voltages up to 5 V, which usually degrade liquid-electrolyte EDL transistors via electrolysis. Assuming the formation of a 1-nm-thick EDL, the concentration of carrier electrons induced during the transistor operation was estimated to be 1019–1021 cm−3. Moreover, the mobility increased with the InO thickness and reached a maximum value of 68 cm2/(V s) at an InO thickness of 120 nm. The conduction electrons were significantly affected by grain boundary scattering and surface scattering, in addition to scattering within the crystal grain. An increase in the InO thickness, which improved the crystallinity in the crystal grain, reduced the barrier height and the effect of grain boundary scattering. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide (MoS2) is a representative two-dimensional layered transition-metal dichalcogenide semiconductor. Layer-number-dependent electronic properties are attractive in the development of nanomaterial-based electronics for a wide range of applications including sensors, switches, and amplifiers. MoS2 field-effect transistors (FETs) have been studied as promising future nanoelectronic devices with desirable features of atomic-level thickness and high electrical properties. When a naturally n -doped MoS2 is contacted with metals, a strong Fermi-level pinning effect adjusts a Schottky barrier and influences its electronic characteristics significantly. In this study, we investigate multilayer MoS2 Schottky barrier FETs (SBFETs), emphasizing the metal-contact impact on device performance via computational device modeling. We find that p -type MoS2 SBFETs may be built with appropriate metals and gate voltage control. Furthermore, we propose ambipolar multilayer MoS2 SBFETs with asymmetric metal electrodes, which exhibit gate-voltage dependent ambipolar transport behavior through optimizing metal contacts in MoS2 device. Introducing a dual-split gate geometry, the MoS2 SBFETs can further operate in four distinct configurations: p − p, n − n, p − n, and n − p. Electrical characteristics are calculated, and improved performance of a high rectification ratio can be feasible as an attractive feature for efficient electrical and photonic devices. [ABSTRACT FROM AUTHOR]

The spin field effect transistor (sFET), proposed by Datta and Das (1990 Appl. Phys. Lett. 56 665–7), has long been regarded as a model semiconductor spintronic device, offering potential for new, more energy-efficient functionalities in electronic devices. Here, the overview is given how the pursuit of meeting the requirements for implementing the sFET concept has influenced spintronic research, leading to a greater understanding of spin phenomena in solids and resulting in numerous exciting effects. After looking back, based on the recent developments, the possible future directions of the sFET-related research are described. [ABSTRACT FROM AUTHOR]

Heart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage, the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low-power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The least mean square (LMS) filter with Co-ordinate Rotation Digital Computer (CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly, the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies, leakage power has started to occupy 30–50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, integrated coarse-grained power and clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch-, AND- and OR-based clock gating with forced transistor stacking and sleep transistor whose width and length are doubled from the rest of the complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques are found to be 36.95% from the non-gated CORDIC LMS filter design. [ABSTRACT FROM AUTHOR]

This work contributes an area-effective low-noise amplifier design with a vast voltage gain range for a wide frequency range. The novel low-noise amplifier has an input stage, a common-gate stage, and another stage of the common-source technique. It is designed using the current mirror, the current bleeding network, and a new active inductor circuit. The noise-canceling network leads to a reduction of noise and power. The current-bleeding network improves the trans-conductance and provides a reduction in overall noise. Active inductors are crucial for achieving maximal gain, extensive bandwidth values, and low power consumption. Body-biasing technique has improved overall performance of the design. The novel low-noise amplifier is simulated and designed at a 0.5 V input voltage cadence virtuoso GPDK 90 nm and GPDK 45 nm complementary metal-oxide semiconductors (CMOS). The power dissipation of the novel active inductor (AI) is 416 µW with an optimized gain value, a small area requirement, and inductance values that varies with different W/L ratios of AI transistors. Power consumption of this low-noise amplifier is 4.85 mW, with optimized S-parameters values. Additionally, a small area and an optimized gain value also adds to the immense potential offered by proposed designs compared to the state-of-the-art low-noise amplifiers. [ABSTRACT FROM AUTHOR]

Thermotronics has attracted much attention driven by the promising potentials offered by devices such as thermal diodes, thermal transistors, and thermal memristors. Heat shuttling (or heat ratcheting, or heat pumping) is a phenomenon exhibited by nonlinear materials presenting temperature-dependent thermal conductivity which, when sandwiched between two thermal baths with one bath subjected to a time-varying temperature, show nonvanishing net heat flow, although the baths share the same average temperature. Phase-change materials (PCMs) like VO 2 were recently taken for illustration due to a strong change in conductivity over a small temperature range; energy extraction from the thermal variations of the environment was envisioned thereupon. However, up to now, the impact of PCM hysteresis has been either overlooked or roughly approximated. On the basis of a thermal model simulating partial hysteresis loops and nonhysteretic branches, we demonstrate that the presence of hysteresis profoundly modifies the appearance of the heat-shuttling effect and can constitute a hindrance to its manifestation. Operating configurations to improve its observation have been proposed. [ABSTRACT FROM AUTHOR]

Thermotronics has attracted much attention driven by the promising potentials offered by devices such as thermal diodes, thermal transistors, and thermal memristors. Heat shuttling (or heat ratcheting, or heat pumping) is a phenomenon exhibited by nonlinear materials presenting temperature-dependent thermal conductivity which, when sandwiched between two thermal baths with one bath subjected to a time-varying temperature, show nonvanishing net heat flow, although the baths share the same average temperature. Phase-change materials (PCMs) like VO 2 were recently taken for illustration due to a strong change in conductivity over a small temperature range; energy extraction from the thermal variations of the environment was envisioned thereupon. However, up to now, the impact of PCM hysteresis has been either overlooked or roughly approximated. On the basis of a thermal model simulating partial hysteresis loops and nonhysteretic branches, we demonstrate that the presence of hysteresis profoundly modifies the appearance of the heat-shuttling effect and can constitute a hindrance to its manifestation. Operating configurations to improve its observation have been proposed. [ABSTRACT FROM AUTHOR]

Epitaxial graphene (EG) on cubic silicon carbide (3C-SiC) on silicon holds the promise of tunable nanoelectronic and nanophotonic devices, some uniquely unlocked by the graphene/cubic silicon carbide combination, directly integrated with the current well-established silicon technologies. Yet, the development of graphene field-effect devices based on the 3C-SiC/Si substrate system has been historically hindered by poor graphene quality and coverage, as well as substantial leakage issues of the heteroepitaxial system. We address these issues by growing EG on 3C-SiC on highly resistive silicon substrates using an alloy-mediated approach. In this work, we demonstrate a field-effect transistor based on EG/3C-SiC/Si with gate leakage current 6 orders of magnitude lower than the drain current at room temperature, which is a vast improvement on the current literature, opening the possibility for dynamically tunable nanoelectronic and nanophotonic devices on silicon at the wafer level. [ABSTRACT FROM AUTHOR]

A coupling model is established on piezoelectric semiconductor bipolar junction transistors (PS-BJT) subjected to mechanical loadings by abandoning depletion layer approximation and low injection assumption. Effect of base region on device performance and interaction between emitter/base junction (E/B) and base/collector junction (B/C) are investigated. It is found that too small a base width will cause B/C to extract electrons directly from emitter region, implying that an electron passageway will be excited to link from collector- to emitter-region by striding over base-region (abbreviated as "EP-CE" hereafter). We particularly clarify that the current produced by electrons flowing across EP-CE is independent of electron-hole recombination in E/B, which means that this current has not yet been bestowed on the information of base current. "Information of base current" refers to dispatching information of base current on the electrons in emitter region. Thus, a current from EP-EC cannot be reckoned in the amplification effect of base current. Our investigations show that base width should not be designed too small to avoid EP-CE, which has not been revealed before. As regards to tuning PS-BJT performance by mechanical loadings, we revealed the mechanism as follows: 1) raising electron-hole recombination rate inside E/B to reduce resistivity such that more electrons can be driven from emitter- to base-region; 2) elevating electron conductivity in base-region for easier pass of electrons; 3) promoting attractive ability of B/C on electrons such that more electrons cross the interface. Numerical results show that transmission characteristics can be greatly increased as expected by mechanical tuning. [ABSTRACT FROM AUTHOR]

This work explores the atomic-scale nature of defects within hafnium dioxide/silicon dioxide/silicon (HfO2/SiO2/Si) transistors generated by hot-carrier stressing. The defects are studied via electrically detected magnetic resonance (EDMR) through both spin-dependent charge pumping and spin-dependent tunneling. When combined, these techniques probe defects both at the Si-side interface and within the oxide-based gate stack. The defects at the Si-side interface are found to strongly resemble Pb-like defects common in the Si/SiO2 system. The defect within the gate stack has not been positively identified in the literature thus far; this work argues that it is a Si-dangling bond coupled to one or more hafnium atoms. The use of EDMR techniques indicates that the defects detected here are relevant to electronic transport and, thus, device reliability. This work also highlights the impressive analytical power of combined EDMR techniques when studying complex, modern materials systems. [ABSTRACT FROM AUTHOR]

Understanding thermal transport at the submicron scale is crucial for engineering applications, especially in the thermal management of electronics and tailoring the thermal conductivity of thermoelectric materials. At the submicron scale, the macroscopic heat diffusion equation is no longer valid and the phonon Boltzmann transport equation (BTE) becomes the governing equation for thermal transport. However, previous thermal simulations based on the phonon BTE have two main limitations: relying on empirical parameters and prohibitive computational costs. Therefore, the phonon BTE is commonly used for qualitatively studying the non-Fourier thermal transport phenomena of toy problems. In this work, we demonstrate an ultra-efficient and parameter-free computational method of the phonon BTE to achieve quantitatively accurate thermal simulation for realistic materials and devices. By properly integrating the phonon properties from first-principles calculations, our method does not rely on empirical material properties input. It can be generally applicable for different materials and the predicted results can match well with experimental results. Moreover, by developing a suitable ensemble of advanced numerical algorithms, our method exhibits superior numerical efficiency. The full-scale (from ballistic to diffusive) thermal simulation of a 3-dimensional fin field-effect transistor with 13 million degrees of freedom, which is prohibitive for existing phonon BTE solvers even on supercomputers, can now be completed within two hours on a single personal computer. Our method makes it possible to achieve the predictive design of realistic nanostructures for the desired thermal conductivity. It also enables accurately resolving the temperature profiles at the transistor level, which helps in better understanding the self-heating effect of electronics.

Organic electrochemical transistors (OECTs) possess low operating voltage and excellent amplification capability and show promising applications in biosensors and flexible electronics. However, the active layers of OECTs are usually dense films, which show limited ion penetration/transport, resulting in limited performances of OECTs. Here, unprecedented high‐performance flexible multifunctional OECTs based on nanoporous (mainly 2–60 nm), high‐specific‐surface‐area (255–281 m2 g−1), and flexible conjugated polymer aerogel films are developed. The nanoporous structures effectively facilitate ion penetration/transport, leading to significantly enhanced transconductance (48.5–53.5 mS) and on/off ratio (6.4 × 104) of the OECTs compared with those of dense devices. The resulting OECT‐based glucose sensors exhibit an ultralow detection limit of 1 pm, approximately two to three orders of magnitude lower than those of the previously reported OECT glucose sensors, and an ultrabroad detection range of 1 pm–5 m. They can detect trace amounts of glucose in sweat, serum, saliva, and urine in real time. Moreover, the OECTs can be used for high‐performance flexible artificial synapses and electrocardiogram monitoring. This work provides a powerful strategy toward highly sensitive biosensors, artificial synapses, and electrophysiological signal monitoring. [ABSTRACT FROM AUTHOR]

Faradaic‐mode organic electrochemical transistors (OECT) are promising but usually need hundreds of millivolts to sustain redox reactions. Decrease or even removal of the voltage penalty is highly desirable. Herein, the Faradic regime of the OECT is broadened toward zero bias by integrating a p‐n heterojunction of Cu2S‐diethylenetriamine (DETA)‐CdS for efficient photogating of poly(3,4‐ethylenedioxythiophene): poly(styrene sulfonate) channel. Upon light illumination, it is found that an obvious Faradaic process is evolved at the gate/electrolyte interface under zero gate bias, suggesting the potential of sensitive amperometric biodetection with enhanced signal resolution. At the Cu2S‐DETA‐CdS/liquid interface, a biosensing process is introduced, combining with a DNA walker and enzymatic biocatalytic precipitation to produce a target‐dependent diffusion barrier, modulating the amperometric output with enhanced signal variations under light irradiation compared to that in the dark. The proposed system achieves the desired analytical performance for representative target miRNA‐10b with a low detection limit of 0.21 fM. This work features a light‐mediated OECT device with enhanced signal resolution and provides new operational paradigms and insights for novel optoelectronics interfacing with biological systems. [ABSTRACT FROM AUTHOR]

Quasi‐2D perovskites have attracted significant attention because of their environmental robustness and superior long‐term stability compared with their 3D counterparts. However, they typically consist of a mixture of multiple quantum wells with different optoelectrical properties, which degrades the electronic properties and hinders further electronic applications. Here, to challenge this issue, a surface p‐doping strategy involving the introduction of a thiophene‐containing polymer onto the surface of quasi‐2D tin perovskites is reported. The tin ions in the perovskites effectively interact with the sulfur atoms in the thiophene moieties, thereby generating hole carriers and inducing p‐doping. The resulting doped quasi‐2D perovskites exhibit excellent surface crystallinity, lower trap density, and enhanced charge carrier transport capability along the perovskite semiconductor channels. Consequently, the doped quasi‐2D tin perovskite‐based transistors exhibit a high field‐effect mobility of 53 cm2V−1s−1 (7 cm2V−1s−1 for the control device) and an outstanding on/off ratio (>107), together with superior operational stability. [ABSTRACT FROM AUTHOR]

The key roles of electrode/semiconductor and semiconductor/dielectric interfaces play in the ideality of organic field‐effect transistors (OFETs) by traditional device preparation technologies are not yet fully understood, which severely limits progress in the design of molecules, the understanding of transport mechanisms, and the circuit applications of OFETs. Herein, at a quantitative level, the origin of nonideal current–voltage (I–V) curves and possibly overestimated mobility in single‐crystal OFETs is revealed, including contact resistance (Rc), charge trapping, and scattering at interfaces of devices. Impressively, an efficient interface collaborative strategy, which consists of transferred “doped” electrodes with tunable contact “doping” localized regions at the source‐drain contacts and polymer‐modified SiO2 with suitable surface polarity (γsp) is further demonstrated that have great advantages in the construction of ideal high mobility devices. Also, an interesting double‐edged sword effect of γsp of dielectric on the ideality of OFETs is observed. The dielectric with a lower γsp can result in higher mobility, while too low γsp would degrade the device ideality due to significant effect of charge scattering. The findings not only provide new perspectives and strategies to construct ideal OFETs but also offer useful guidance to correctly evaluate organic semiconductor materials. [ABSTRACT FROM AUTHOR]

We have proposed leaky integrate-and-fire (LIF) neuron having low-energy consumption and tunable functionality without external circuit components. Our LIF neuron has a simple configuration consisting of only three components: one bandgap-engineered resistive switching transistor (BE-RST), one capacitor, and one resistor. Here, the crucial point is that BE-RST with a silicon–germanium heterojunction possesses an amplified hysteric current switching with a low latch-up voltage due to improved hole storage capability and impact ionization coefficient. Therefore, the proposed neuron utilizing BE-RST requires an energy consumption of 0.36 pJ/spike, which is approximately six times lower than 2.08 pJ/spike of pure silicon-RST based neuron. In addition, the spiking properties can be tuned by modulating the leakage rate and threshold through gate bias, which contributes to energy-efficient sparse-activity and high learning accuracy. As a result, our proposed neuron can be a promising candidate for executing various spiking neural network applications. [ABSTRACT FROM AUTHOR]

The quadratic buck converter is renowned for its steep step‐down capability. It encounters increased losses due to its high component count. In scenarios with light loads, switching losses become the dominant factor. Additionally, the presence of two right‐half plane zeros impairs transient response, even at high‐frequency switching operations. Incorporating this converter into the digital domain introduces an undesired phenomenon known as subharmonic oscillation, rendering the system unstable, albeit potentially mitigated over time—a drawback particularly undesirable for converters tasked with rapid load dynamics. This paper introduces an adaptive pulse skipping modulation scheme to control metal–oxide–semiconductor field‐effect transistor (MOSFET) switching actions, enhancing overall efficiency in discontinuous conduction mode. Furthermore, the effects of right half‐plane (RHP) zeros on stability are analyzed within these switching schemes. The proposed scheme is integrated with voltage‐mode control. Simulation and theoretical analyses are conducted to validate this converter. A flat efficiency of 89% to 86% for the load range of 25 to 700 mA is obtained, outperforming other existing schemes. The results demonstrate that the adaptive pulse modulation scheme effectively improves efficiency and stability in discontinuous conduction mode converters. This research provides valuable insights for optimizing power electronics systems with varying load dynamics. [ABSTRACT FROM AUTHOR]

Stretchable conjugated polymers with conjugation break spacers (CBSs) synthesized via random terpolymerization have gained considerable attention because of their efficacy in modulating mobility and stretchability. This study incorporates a series of dianhydrohexitol diastereomers of isosorbide (ISB) and isomannide (IMN) units into the diketopyrrolopyrrole‐based backbone as CBSs. It is found that the distorted CBS (IMN) improves the mobility–stretchability properties of the polymer with a highly coplanar backbone, whereas the extended CBS (ISB) enhances those of the polymer with a noncoplanar backbone. Additionally, the different configurations of ISB and IMN sufficiently affect the solid‐state packing, aggregation capabilities, crystallographic parameters, and mobility–stretchability properties of the polymer. The IMN‐based polymers exhibit the highest mobility of 1.69 cm2 V−1 s−1 and crystallinity retentions of (85.7, 78.6)% under 20% and 60% strains, outperforming their ISB‐based or unmodified counterparts. The improvement is correlated with a robust aggregation capability. Furthermore, the CBS content affects aggregation behavior, notably affecting mobility. This result indicates that incorporating CBSs into the polymer can enhance backbone flexibility via movement and rotation of the CBS without affecting the crystalline regions. [ABSTRACT FROM AUTHOR]

We present robust pixel design methodologies for a vertical avalanche photodiode-based CMOS image sensor, taking account of three critical practical factors: (i) "guard-ring-free" pixel isolation layout, (ii) device characteristics "insensitive" to applied voltage and temperature, and (iii) stable operation subject to intense light exposure. The "guard-ring-free" pixel design is established by resolving the tradeoff relationship between electric field concentration and pixel isolation. The effectiveness of the optimization strategy is validated both by simulation and experiment. To realize insensitivity to voltage and temperature variations, a global feedback resistor is shown to effectively suppress variations in device characteristics such as photon detection efficiency and dark count rate. An in-pixel overflow transistor is also introduced to enhance the resistance to strong illumination. The robustness of the fabricated VAPD-CIS is verified by characterization of 122 different chips and through a high-temperature and intense-light-illumination operation test with 5 chips, conducted at 125 °C for 1000 h subject to 940 nm light exposure equivalent to 10 kLux. [ABSTRACT FROM AUTHOR]

The innovation of 3D FinFETs using top‐down silicon nanofins represents a significant advancement toward scaling down microchip process nodes to the cutting‐edge 3‐nm level. While bottom‐up semiconductor nanofins also hold promise as building blocks for FinFETs, their controlled growth remains challenging. Drawing inspiration from the guided roots along brick gaps, this study shows that the aligned atomic terraces on an annealed miscut LaAlO3 surface can trigger an exceptional graphoepitaxial effect, encouraging the bottom‐up vapor‐phase growth of self‐aligned nanostructures such as CdS, CdSe, ZnSe, and ZnTe. Subsequently, the resultant CdS nanofins, characterized by narrow widths of ≈20 nm and large height‐to‐width ratios exceeding 16, can be seamlessly assembled into arrayed FinFETs on the insulating LaAlO3 substrate, obviating the need for post‐growth alignment steps. Unlike most nanostructure‐based planar transistors, which often operate in depletion mode characterized by negative thresholds, these FinFETs operate in enhancement mode with positive thresholds (≈5 V), ≈10−14‐A standby currents, and ≈108 on/off current ratios. The achieved ratio surpasses the record for planar enhancement‐mode CdS transistors by 4 orders of magnitude, primarily due to the enhanced electrostatic control over the nanofins. Overall, the graphoepitaxially side‐by‐side nanofins show tremendous potential to expand the repertoire of FinFETs based on non‐silicon semiconductors. [ABSTRACT FROM AUTHOR]

Sensory adaptation is a very important function of the biological nervous system to maintain survival. It helps us to better perceive, understand, and adapt to the environment. Therefore, building artificial sensory adaptation systems through neuromorphic devices is a goal that humans have been continuously pursuing. Unfortunately, current research has either based on individual adaptive devices or employed complex processes. At present, a facile fabrication of adaptive device arrays is still a great challenge. Herein, a maskless ionotronic double‐gate oxide transistor array with pattern adaptation function is demonstrated using femtosecond laser process. Such process is a maskless patterning technology and free of chemical contamination, enabling a facile integration of device arrays. The as‐fabricated transistor exhibits a low subthreshold swing of 265 mV dec−1 and a reasonable current switching ratio of ≈103 under a low operating voltage of 1 V. Interestingly, it can achieve a transition from nonadaptive to adaptive behavior by the other gate terminal. Moreover, the desensitization behavior after adaptation can be realized for mimicking the self‐protection capability of biological sensory systems. Finally, a 2 × 2 transistor array is demonstrated for emulating the experience‐dependent pattern adaptation ability in the human brain. Therefore, this adaptive device array using femtosecond laser process may provide a good opportunity for the artificial sensory adaptation systems and the next‐generation bionic robots. [ABSTRACT FROM AUTHOR]

Highly stretchable aerogel films are attractive for advanced next‐generation stretchable electronics. However, it is a great challenge to achieve high stretchability for aerogel films. Here, several types of unprecedented ultra‐stretchable semiconducting polymer‐based aerogel films with crimpled porous structures are developed via crosslinking and template methods combined with uniaxial and biaxial pre‐stretching strategies. The semiconducting aerogel films obtained by uniaxial pre‐stretching exhibit ultrahigh stretchability up to 100–200%, while those obtained by biaxial pre‐stretching show high biaxial stretchability up to 50%. The resulting aerogel films show strain‐insensitive electrical and joule heating properties. A prototype of the aerogel film‐based stretchable organic electrochemical transistor (OECT) is developed for the first time. Benefiting from their unique porous structures, the aerogel film‐based OECTs exhibit enhanced on/off ratio and transconductance compared with corresponding dense film‐based OECTs, high stretchability up to 100%, and high stretching stability with 10 000 stretching cycles under 30% strain. It is demonstrated that the aerogel film‐based OECTs can be applied as high‐performance stretchable artificial synapses and biosensors. This work gives a versatile strategy toward highly stretchable aerogel films promising for flexible electronics. [ABSTRACT FROM AUTHOR]

Urine analysis stands as a critical diagnostic tool, offering insights into health and disease. However, current techniques demand sophisticated equipment or significant sample processing for urine examination, reducing their suitability for regular point‐of‐care assessments. This study introduces a novel multi‐component sensing platform to address these constraints. The proposed sensor array can detect sodium (Na+), potassium (K+), ammonium (NH4+), calcium (Ca++), chloride (Cl−), and pH levels, thus, enabling real‐time urine analysis. This sensing platform utilizes an extended gate (EG)‐field effect transistor (FET) design employing EG electrodes made of LASER engraved graphene on flexible Kapton substrates. These experimental findings from individual sensors demonstrate consistent linear responses to ion levels, discrimination of specific ions among interferences, and operational stability over time. Additionally, the six‐channel sensor array exhibits notable sensitivity and selectivity in a urine environment, effectively discerning various ions and pH, illustrating its efficacy for urine analysis and validating its potential for reliable point‐of‐care diagnostics. [ABSTRACT FROM AUTHOR]

This paper presents basic properties and laboratory tests of a commercial integrated high-frequency MOSFET gate driver IXRFD631 operating in the frequency range up to 30 MHz. The MOSFET driver has been tested for two operating states: in the idle state (no load) and at the gate load of a DE275-501N16A series MOSFET transistors. The obtained laboratory results were compared with three other commercial integrated drivers: DEIC420, DEIC515 and IXRFD630 (which are the base structures), and two previous solutions from the author (4xUCC27516 and 8xUCC27526). Additionally, this paper presents the characteristics of power losses and efficiency, measurements of switching and propagation times of the tested gate drivers. Also, this paper presents the output voltage waveforms of the integrated driver IXRFD631 for two operating states. The integrated circuit IXRFD631 of the gate driver is characterized by an efficiency of up to 70% for the tested frequency range, the power losses for two operating states (at idle state—15 W, at gate MOSFET load—43 W) and switching times of 2 ns for an operating frequency of 30 MHz. [ABSTRACT FROM AUTHOR]

In this paper, the operational verification of the stacked transistor configuration is provided, focusing on the use of GaN transistors. The methodology is based on simulated and laboratory experiments. The stacked transistor configuration appears to be a promising solution to increase the voltage-blocking capability of GaN technology for high-voltage operations. Currently available GaN transistors are manufactured for 650 V of blocking voltage. Devices with a higher voltage-blocking capability are not currently available. Therefore, the stacked module was verified, while the main focus was on the driving circuit design, verification, and testing. For this purpose, two alternatives of GaN transistor technology have been compared. The main goal was to reach 800 V of blocking voltage with acceptable voltage deviation for nominal power of a power semiconductor converter. [ABSTRACT FROM AUTHOR]

Effective Ohmic contact between metals and their conductive channels is a crucial step in developing high-performance Ga2O3-based transistors. Distinct from bulk materials, excess thermal energy of the annealing process can destroy the low-dimensional material itself. Given the thermal budget concern, a feasible and moderate solution (i.e., Ar-containing plasma treatment) is proposed to achieve effective Ohmic junctions with (100) β-Ga2O3 nanosheets. The impact of four kinds of plasma treatments (i.e., gas mixtures SF6/Ar, SF6/O2/Ar, SF6/O2, and Ar) on (100) β-Ga2O3 crystals is comparatively studied by X-ray photoemission spectroscopy for the first time. With the optimal plasma pre-treatment (i.e., Ar plasma, 100 W, 60 s), the resulting β-Ga2O3 nanosheet field-effect transistors (FETs) show effective Ohmic contact (i.e., contact resistance RC of 104 Ω·mm) without any post-annealing, which leads to competitive device performance such as a high current on/off ratio (>107), a low subthreshold swing (SS, 249 mV/dec), and acceptable field-effect mobility ( μ e f f , ~21.73 cm2 V−1 s−1). By using heavily doped β-Ga2O3 crystals (Ne, ~1020 cm−3) for Ar plasma treatments, the contact resistance RC can be further decreased to 5.2 Ω·mm. This work opens up new opportunities to enhance the Ohmic contact performance of low-dimensional Ga2O3-based transistors and can further benefit other oxide-based nanodevices. [ABSTRACT FROM AUTHOR]

A new approach to control the n‐doping reaction of organic semiconductors is reported using surface‐functionalized gold nanoparticles (f‐AuNPs) with alkylthiols acting as the catalyst only upon mild thermal activation. To demonstrate the versatility of this methodology, the reaction of the n‐type dopant precursor N‐DMBI‐H with several molecular and polymeric semiconductors at different temperatures with/without f‐AuNPs, vis‐à‐vis the unfunctionalized catalyst AuNPs, was investigated by spectroscopic, morphological, charge transport, and kinetic measurements as well as, computationally, the thermodynamic of catalyst activation. The combined experimental and theoretical data demonstrate that while f‐AuNPs is inactive at room temperature both in solution and in the solid state, catalyst activation occurs rapidly at mild temperatures (~70 °C) and the doping reaction completes in few seconds affording large electrical conductivities (~10–140 S cm−1). The implementation of this methodology enables the use of semiconductor+dopant+catalyst solutions and will broaden the use of the corresponding n‐doped films in opto‐electronic devices such as thin‐film transistors, electrochemical transistors, solar cells, and thermoelectrics well as guide the design of new catalysts. [ABSTRACT FROM AUTHOR]

We demonstrate that electroactive thin films incorporating semiconducting polymers and deterministic functionalized gold nanoclusters (ncAu25) lead to the integration of the functions of resistive memory device and field-effect transistor within a single component ("mem-transistor") in a neuromorphic system. Memristor functions originate from ferrocenyl-modified gold nanoclusters (ncAu25-Fc) embedded in polymethyl-methacrylate (PMMA) and devices optimized for maximum 1/0 "flash" memory effect are found to contain 15 wt. % ncAu25-Fc. Integrated memristor and neuromorphic functions are obtained by replacing PMMA with poly(3-hexylthiophene) (P3HT) in the active layer, from which transistor effects are derived. Based on the energy band diagrams of ncAu25, PMMA, and P3HT, percolation theory is used to explain the memristor 1/0 on/off ratio as a function of ncAu25-Fc concentration. The use of ncAu25-Fc with charge-tunable, ferrocene-modified ligands is critical to achieve better cluster–polymer interfaces. Our work shows that nanostructures of polymers and metalorganic frameworks bear strong potential in the field of neuromorphic devices and circuital simplification of data storage technology. [ABSTRACT FROM AUTHOR]

Field-effect transistors (FETs) based on two-dimensional materials (2DMs) with atomically thin channels have emerged as a promising platform for beyond-silicon electronics. However, low carrier mobility in 2DM transistors driven by phonon scattering remains a critical challenge. To address this issue, we propose the controlled introduction of localized tensile strain as an effective means to inhibit electron-phonon scattering in 2DM. Strain is achieved by conformally adhering the 2DM via van der Waals forces to a dielectric layer previously nanoengineered with a gray-tone topography. Our results show that monolayer MoS2 FETs under tensile strain achieve an 8-fold increase in on-state current, reaching mobilities of 185 cm²/Vs at room temperature, in good agreement with theoretical calculations. The present work on nanotopographic grayscale surface engineering and the use of high-quality dielectric materials has the potential to find application in the nanofabrication of photonic and nanoelectronic devices. Improving the performance of 2D transistors is essential to enable their future application for beyond-silicon electronics. Here, the authors report a method to induce localized tensile strain in monolayer MoS2 transistors, leading to enhanced electron mobilities up to 185 cm2/Vs and an 8-fold increase of the on-state current densities. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) are of great interest in low‐power bioelectronics and neuromorphic computing, as they utilize organic mixed ionic‐electronic conductors (OMIECs) to transduce ionic signals into electrical signals. However, the poor environmental stability of OMIEC materials significantly restricts the practical application of OECTs. Therefore, the non‐fused planar naphthalenediimide (NDI)‐dialkoxybithiazole (2Tz) copolymers are fine‐tuned through varying ethylene glycol (EG) side chain lengths from tri(ethylene glycol) to hexa(ethylene glycol) (namely P‐XO, X = 3–6) to achieve OECTs with high‐stability and low threshold voltage. As a result, the NDI‐2Tz copolymers exhibit ambipolarity, rapid response (<10 ms), and ultra‐high n‐type stability. Notably, the P‐6O copolymers display a threshold voltage as low as 0.27 V. They can operate in n‐type mode in an aqueous solution for over 60 h, maintaining an on‐off ratio of over 105. This work sheds light on the design of exceptional n‐type/ambipolar materials for OECTs. It demonstrates the potential of incorporating these ambipolar polymers into water‐operational integrated circuits for long‐term biosensing systems and energy‐efficient brain‐inspired computing. [ABSTRACT FROM AUTHOR]

In this paper, a successful electric field modulation in Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) transistors to enhance the electrical characteristics is presented. A β-Ga2O3 film in the drift region is incorporated. The β-Ga2O3 film leads to a more efficient electric field modulation and enhances the DC and RF capabilities. Also, a Silicon layer is embedded in the buried oxide of the proposed structure to improve self-heating effects. Overall, the proposed β-Ga2O3 film in SOI LDMOS (βF-LDMOS) structure offers improved performances in terms of electric field distribution, maximum available power gain, unilateral power gain, gate-drain capacitance, breakdown voltage, and maximum lattice temperature. This makes it a promising candidate for RF power applications requiring high voltage and high power handling capabilities. [ABSTRACT FROM AUTHOR]

In the pursuit of low‐dose flat‐panel X‐ray detection and imaging, controlling dark current is pivotal. Modulating the bandgap and resistivity of photosensitive materials is one of the methods to reduce dark current. The study introduces a novel approach by first demonstrating a non‐perovskite orthorhombic phase δ‐CsPbI2Br thick film, fabricated using an innovative elastic molecular‐assisted coating strategy. This technique results in a material with an optimized bandgap of 2.30 eV and a significantly elevated resistivity of 2.42 × 10¹⁰ Ω cm. Consequently, this leads to an ultralow dark current of 1.34 nA cm⁻2. Leveraging this advancement, the developed X‐ray detectors showcase a groundbreaking low detection limit of 53 nGyair s⁻¹, surpassing the performance of their cubic‐phase counterparts. Remarkably, the material exhibits excellent phase stability, maintaining its properties for up to 80 days. By integrating with a thin‐film transistor array, a flat‐panel X‐ray detector that delivers high‐quality 8‐bit imaging across a 64 × 64 matrix is successfully engineered. This work not only presents a transformative approach to substantially reduce dark current in low‐dose X‐ray detection but also sets a new benchmark in the field by combining enhanced imaging capability with robust long‐term stability. [ABSTRACT FROM AUTHOR]

Low energy consumption per synaptic event is important for artificial synapses in applications of highly integrated and large-scale neuromorphic computing systems. Reducing the channel length of a synaptic transistor is an effective method to achieve this goal because such devices can work under low operating voltage and current. In this Letter, we use femtosecond laser ablation to fabricate a microscale slit in an Ag film as the channel of an organic synaptic transistor to obtain low energy consumption. The length of the shortest channel is only 1.6 μm. As a result, the device could be driven by a 50 μV drain bias voltage while output 855 pA excitatory postsynaptic current under a gate spike of 50 mV and 30 ms. The calculated energy consumption per synaptic event is 1.28 fJ, which is comparable to that of a biological synapse (1–10 fJ per synaptic event). Femtosecond laser ablation has been demonstrated a rapid and effective process for the fabrication of microscale channel with high resolution for synaptic transistor, showing large potential for the development of neuromorphic electronics. [ABSTRACT FROM AUTHOR]

This work presents a normally off high-voltage indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) featuring a drain offset region modulated by the IZO layer (IMO, IMO-IGZO TFT). In addition to decreasing the specific on-resistance (Ron,sp) by more than three orders of magnitude, the IMO structure further elevates the breakdown voltage by optimizing the thickness of the IZO layer (tIZO) compared to the Offset TFT. Through TCAD simulation, the underlying mechanism responsible for the improved performance of the IMO-IGZO TFT is elucidated. The introduced IZO modulating layer effectively increases carrier concentration and rebuilds the electric field within the offset region. Consequently, the IMO-IGZO TFT with a 6 nm thick IZO modulating layer and 3.5 μm length offset region attains a breakdown voltage of 410 V and demonstrates favorable Ron,sp of 5.3 × 103 mΩ × cm2. This results in a Baliga's figure of merit of 31.72 kW/cm2, surpassing conventional and Offset TFTs by factors of 186 and 3048, respectively. [ABSTRACT FROM AUTHOR]

A new structure of distributed Doherty low-noise amplifier is implemented on a GaAs pHEMT substrate, using the ED02AH process design kit tailored for 5G applications. This circuit exhibits high linear gain and a consistent noise factor across the frequency range of 22 to 42 GHz. The LNA comprises 10 cells distributed across two stages, with a performance adjustment circuit added to the source electrode of each transistor. Operating with a VGS = –0.15 V and VDS = 1.8 V bias, the LNA delivers an S21 gain of 22.5 ± 2.5 dB and noise figure of 3 ± 0.55 dB, consuming 980 mW of power. The linear performance of the LNA is affirmed by an input 1 dB compression point (IP1dB) of 11 dBm and a third-order input intercept point (IIP3) of 13 dBm. With a surface area of 2.9 × 1.2 mm2, the LNA has a figure of merit of 73.14, demonstrating the high efficiency of the proposed Doherty distributed structure. [ABSTRACT FROM AUTHOR]

The magnetoresistance and the Hall effect in transistor structures fabricated on films of the three-dimensional topological insulator (Bi,Sb)2(Te,Se)3 are studied. It is shown that the negative magnetoresistance at low magnetic field is described in terms of quantum corrections to the conductivity. The magnitude of these corrections depends on the gate voltage and increases when approaching the charge neutrality point. The Hall coefficient RH is nonlinear at low magnetic fields for any gate voltage, and the RH nonlinearity is the most pronounced at high negative gate voltages. At high fields, the slope of the magnetic field dependence of the Hall coefficient changes its sign at some gate voltage. [ABSTRACT FROM AUTHOR]

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets. [ABSTRACT FROM AUTHOR]

In this study, the impact of varying the thickness of the Al2O3 interlayer dielectric on the electrical characteristics of BaTiO3/III‐nitride transistors is investigated. In the findings, it is revealed that a minimum thickness of 8 nm for the Al2O3 layer is crucial to maintain high device performance and protect against sputtering‐induced damage during BaTiO3 deposition. The fabricated BaTiO3/Al2O3/AlGaN/GaN high electron mobility transistors exhibit exceptional electrical properties, including a maximum current density of 700 mA mm−1, an on‐resistance of 5 Ω mm, an ION/IOFF ratio of 107, a subthreshold slope of 119 mV dec−1, and significantly reduced gate leakage current. The devices with the optimal 8 nm Al2O3 thickness demonstrates excellent agreement between theoretical and experimental values for effective mobility, achieving a value of 1188 cm2 V−1·s at a 2D electron gas density of 1013 cm−2. Furthermore, in the study, it is confirmed that increasing the Al2O3 thickness also improves the quality of interface charge density, as evidenced by the results obtained from capacitance–voltage measurements. In these findings, the critical role of controlling the Al2O3 thickness in optimizing the electrical characteristics and overall performance of BaTiO3/III‐nitride transistors are highlighted. [ABSTRACT FROM AUTHOR]

Transistors find application within various integrated circuits (ICs) alongside a multitude of electronic devices. These ICs have become integral components in contemporary systems. When organic semiconducting materials constitute the active layer, transistors are termed "organic transistors." The enhancement of diverse device characteristics is achievable through the modeling and simulation of these organic transistors. This study focuses on the simulation of different configurations of pentacene-based organic transistors. To augment device performance, an active layer comprising pentacene is coupled with 5 and 15 nm graphene. Notably, the top gate configuration yields an increase in ON/OFF ratio from 102 to 107, accompanied by an enhancement in sub-threshold swing from 276 to 59 mV/decade. Similarly, the bottom gate configuration exhibits an ON/OFF ratio improvement from 105 to 109, alongside a sub-threshold swing enhancement from 108 to 59 mV/decade. Leveraging graphene as the active layer material results in substantial benefits. These encompass a heightened on-current of 210 mA, a reduced sub-threshold swing of 58 mV/decade, and a significantly enhanced ON/OFF ratio of 1017. [ABSTRACT FROM AUTHOR]

A solution-gate controlled thin-film transistor with SnO2 epitaxial thin films (SnO2-SGTFT) is successfully utilized for highly sensitive detection of nitrite. The SnO2 films are deposited as channel materials on a c-plane sapphire (c-Al2O3) substrate through pulsed laser deposition (PLD), with superior crystal quality and out-of-plane atomic ordering. PtAu NPs/rGO nanocomposites are electrodeposited on a gold electrode to function as a transistor gate to further enhance the nitrite catalytic performance of the device. The change in effective gate voltage due to the electrooxidation of nitrite on the gate electrode is the primary sensing mechanism of the device. Based on the inherent amplification effect of transistors, the superior electrical properties of SnO2, and the high electrocatalytic activity of PtAu NPs/rGO, the SnO2-SGTFT sensor has a low detection limit of 0.1 nM and a wide linear detection range of 0.1 nM ~ 50 mM at VGS = 1.0 V. Furthermore, the sensor has excellent characteristics such as rapid response time, selectivity, and stability. The practicability of the device has been confirmed by the quantitative detection of nitrite in natural lake water. SnO2 epitaxial films grown by PLD provide a simple and efficient way to fabricate nitrite SnO2-SGTFT sensors in environmental monitoring and food safety, among others. It also provides a reference for the construction of other high-performance thin-film transistor sensors. [ABSTRACT FROM AUTHOR]

Boltzmann carrier statistics restrict the sub‐threshold swing (SS ≥ 60 mVdec–1) and, consequently, the supply voltage (≈ 1 V) of the thermionic transistor. This primary bottleneck results in rapidly increasing power consumption, heating, and associated reliability/scalability challenges as more devices are packed into a small footprint. Despite significant efforts from the device community, a suitable sub‐thermionic alternative is yet to emerge. In this work, an attempt is made to understand the physics of Schottky barrier FETs demonstrating SS < 60 mVdec–1, as evident in some experimental results. Employing the in‐house TCAD tool, the electrostatic potential in the device is accurately modeled with the sweeping gate bias. Next, the Tsu–Esaki model is used to compute the tunneling current. The analysis shows that the steep SS results from an abrupt change in the tunneling barrier profile, from a step‐like to a triangular‐like. However, in the ON regime, the drift component begins to dominate the transfer characteristics. Thus, the subtle interplay between the drift and tunneling components of transport leads to SS < 60 mVdec–1 in OFF‐state with improved Ion${\rm I}_{on}$ in ON‐state. Finally, using the calibrated model, the performance metrics of an all‐2D material‐based CMOS inverter operating at a low VDD ≈ 0.6 V are projected. [ABSTRACT FROM AUTHOR]

Capacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks. [ABSTRACT FROM AUTHOR]