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Opinion. Presents the author's wish list related to verifying complex application specific integrated circuits. Language for writing simulation-based verification; Faster simulators; Model checking and theorem-proving tools; Seamless verification environment.

Opinion. Presents the author's view on who has the application expertise to build single-chip systems. Importance of elements to consider in building single-chip systems like application specific integrated circuits (ASIC) architecture; Difficulties faced by Texas Instrument and Lucent Technologies in integrating cores; Information about the agreement of the Mentor Graphics with David Sarnoff Research Center.

Announces the availability of Chartered Semiconductor Manufacturing's 0.35-micron process technologies. Comments of Ben Lee, company's vice president of marketing, on the process technology; Information about the agreement of Chartered with library vendors.

Presents the computer industry consortium, Virtual Socket Interface (VSI) Alliance. VSI's goal; Founding members; Standards Proposal coverage; Policy for membership; Aim of the inauguration of the Reusable Application-Specific Internet protocol (IP) Developers (RAPID).

Introduces memBIST-XT for external static random access memory (SRAM) and dynamic random access memory (DRAM) on personal computer (PC) boards from Logic Vision. Design and functions of the system.

Introduces Aisys's Driveway Device Driver Design Environment (3DE) which takes the job of automating the programming of peripherals in an embedded system. Product features; API Library Selector; Peripheral Configuration Manager.

Discusses the release of a system-programmable gate array (SPGA), a combination of cell-based array gate-array technology of Silicon Architects and the field programmable gate array (FPGA) technology of Actel. Need to make FPGAs viable for intellectual property (IP); Misgivings on FPGA as effective platforms for IPs.

Reports on Avant! Corp.'s merger with both Anagram Inc. and Meta-Software Inc. Anagram's addition of a circuit level tool that analyzes the timing and power of logic circuits to Avant!'s product line; Avant!'s acquisition of the HSPICE analog/mixed-signal simulator from Meta-Software.

Addresses several intellectual property (IP) issues of interest to developers of application specific integrated circuits. IP ownership issue; legal protection/liability; Licensing and compensation models; Meeting of the Reusable Application-Specific IP Developers.

Focuses on the use of equivalence checkers in integrated circuit design. Practicality in design verification; Issues of readiness for model checking; Obstacles to model checking.

Focuses on the prospects for the development of synthesizable cores in application specific integrated circuits. Issue on the development of both hard and soft cores; Issues facing core integration.

Reports that at the ASIC Forum in Paris, France, application specific integrated circuit (ASIC) and electronic design automation (EDA) vendors agreed to cooperate to close the gap between silicon and tools. Participating companies.

Introduces interHDL's Verilint version 4.0, a semantics, synthesis and coding-style checker for designs written in Verilog hardware description language (HDL). Features.

Introduces Exemplar Logic's Leonardo synthesis tool software. Features; Modes of operation.

Reports on Speed Electronic's introduction of its speedExplorer, an option to its speedChart environment at the 1996 Design Automation Conference. Features.

Reports on Quickturn Design Systems' introduction of its Quest II toolset, an enhanced software suite for its System Realizer Emulation systems. Features.

Reports that UniCAD is expected to introduce UniRule which generates printed-circuit board (PCB) design in the pre-layout stage. Features.

Reports on the efforts to accelerate simulation of application specific integrated circuit (ASIC) design. Approaches to speed simulation; Effects of the growth of silicon complexity to ASIC design; Improvements in simulators.

Reports that Analog Devices has opened its AD21xx digital-signal-processor (DSP) architecture to other companies. Features and functions of AD2xx; Analog's licensing agreement with Mentro Graphics.

Reports on Model Technology Inc.'s redesign of the graphical user interface (GUI) of V-System/VHDL and Verilog computer hardware description language simulator. Model's creation of an interface on tool command language (Tcl); Functions of Tcl.

Focuses on the usefulness of behavioral synthesis in computer design and engineering. Use in digital signal processing (DSP); Behavioral Compiler's new behavioral retiming (BRT) capability; Learning the behavioral code; Computer vendors offering higher levels of abstraction.

Reports on developments related to the electronics firm Synopsys. Automation of gate-level transformations; Behavioral retiming capability; Partnership with International Business Machines.

Reports on Virtual Chips's core products that offer PCI bus-interface support. Implementation in VHDL hardware-description language; Comment from top executives.

Discusses various issues concerning application specific integrated circuit (ASIC) and electronic design automation (EDA). Intellectual property (IP) and design-reuse issues; Challenges facing IP providers; Types of IP; Purpose of the industry leaders' forum in Paris, France in March 1996.

Reports on an agreement that gave Quickturn Design Systems the right to sell the design-verification solution technology to all International Business Machines Corp. (IBM) divisions. Stages of the IBM-Quickturn deal; Preparations needed for Quickturn's introduction of the technology for the mass market.

Reports on the agreement entered into by Synopsys's Silicon Architech Business Unit with Taiwan Semiconductor Manufacturing Co. (TSMC). Terms of the agreement; Formalization of a working relationship between the two firms; Production of Silicon Architects' cell-based array libraries and design tools which are based on TSMC foundry process; Library-related developments.

Focuses on application specific integrated circuit (ASIC) design activity based on digital signal processing (DSP) cores. Texas Instruments' (TI) cDSP program; SGS-Thomson Microelectronics' proprietary DSP core; Designers' use of ASICs and field programmable gate arrays (FPGA) for their DSP applications.

Reports on the introduction of power optimization tools for use in the early phases of chip architecture design. Use of Sente's Watt Watcher/Architect to estimate the power characteristics of integrated circuits; Acceptance of designs in Verilog hardware description language (VHDL); EPIC Design Technology's AMPS for automatic minimization of power through sizing; AMPS' upsizing and/or downsizing of transistors.

Reports on IBM Microelectronics' acceptance of netlists for its 0.35-micrometer-drawn complementary metal oxide semiconductors (CMOS) 5X application specific integrated circuit (ASIC) product line. CMOS 5X ASIC's effective channel length; Typical two-way NAND gate delay; Dual 2.5-V/3.3-V power-supply option; Free intermix of input-output (I/O); Enhanced macro functions.

Reports on the availability of Cascade Design Automation's MasterPort tool, which allows users to automatically migrate existing cell libraries from one process technology to another. Development of technology file; GDSII and Spice data as input; Training course offered on MasterPort.

Focuses on shrinkwrapped software for EDA. How Mentor Graphics launched Antares as an independent entity.

Recommends the cycle-based simulators of FrontLine Design Automation and Pendulum Design for users of Cadence Design Systems' Verilog-Xl and Verifault. Integration of CycleDrive simulation engine into FrontLine's multi-engine PureSpeed event-driven Verilog simulator; Compilation and interpretation features; Use of no timing cycle-based mode on appropriate circuits to further accelerate simulation.

Features Virtual Machine Works' (VMW) VirtuaLogic Emulation System, a low-cost and easy-to-use emulator based on the Xilinx XC5000 field programmable gate arrays (FPGA). Increase in the number of emulators competing against market leader Quickturn Design Systems; VMW's VirtualWires multi-FPGA compilation technology.

Reports on the trend towards the use of third-party libraries as an alternative to application specific integrated circuit (ASIC) vendor libraries for ASIC design. Role of deep submicron in the trend; Movement towards customer-owned-tooling (COT)/foundry business; Move of ASIC vendors to extend welcome to library providers.

Reports that Precedence will retain its independence despite its merger with Model Technology. Success of Precedence's SimMatrix simulation back-plane technology and co-simulation solutions; Background on Precedence's operations; Background on the SimMatrix technology.

Reports on the development of Xionics Document Technologies' PowerPC-based 0.6-micrometer 250k-gate XipChip Image Processing central processing unit (CPU), as part of its XipPower family of multifunction-peripheral controllers (MFP). Description of the XipPower board controller.

Reports on the debut of IBM Microelectronics' library of System Building Blocks, application specific integrated circuits (ASIC) cores that include PowerPC processors and peripherals. Features; Co-design environment; Core testability. INSET: More on the cores..

Focuses on static-timing sign-off in application specific integrated circuit (ASIC)-based systems design. LSI Logic; Quad Design Technology's Motive tool; Product development plans of Oki Semiconductor; Expectations.

Reports on application specific integrated circuits (ASIC) from Toshiba America Electronic Components and LSI Logic. Specifications; Support; Compatibility; Availability; Contact information.

Reports on technological developments in formal-verification tools for application specific integrated circuit (ASIC) design. Includes Abstract Hardware's CheckOff-E and CheckOff-M; AT&T Design Automation's Formal Check model checker; Chrysalis Symbolic Design's Design Verifier 2.

Reports on verification and testing tools for application specific integrated circuit (ASIC)-based systems. Synopsys' VHDL System Simulator; VEDA Design Automation's VerdictFault VHDL fault simulator; Development plans.

Reports on the planned merger of ArcSys and Integrated Silicon Systems (ISS). Products; Company background information; Implications; Expectations.

Looks at cell-based array (CBA) architecture in application specific integrated circuits. Use of CBA in building chips with strong data-path content and several random access memory blocks; Examples of applications.

Comments on the move towards RT-level signoff in computer engineering. Reasons behind this trend; Statis timing analysis as a key technology; Formal verification.

Reports on the availability of an OVI-compliant RC-simulator option to interHDL's Viper Verilog HDL simulator. RCsim as the name of the RC-simulator; Tight coupling of the simulator to Viper; Accuracy of RCsim.

Reports on Synopsys' acquisition of Arkos Design. Use of Arkos' high-capacity emulation system with Synopsys' high-level design-automation tool; Use of custom processor chips in the emulator system; Applications of the emulation system.

Features Voyager FS software-only VHDL mixed-level fault simulator from Ikos. Performance of the software; Ikos' success as a vendor of hardware and software products for VHDL and Verilog HDL-based design.

Focuses on the complexity of the methodology for building core-based application specific integrated circuits. Need for systems-applications expertise in the implementation of a system on a chip; Accessibility of system-on-a-chip design for mainstream designers; Motorola's customizable standard products.

Reports on the launching of field programmable gate arrays (FPGA) at 3.3 volts from QuickLogic and Cypress. Use of QuickLogic's metal-to-metal antifuse technology in the FPGAs; Other features of the FPGAs.

Reports on the release of Crosspoint Solutions' re-engineered antifuse-based field programmable gate array (FPGA). Problems regarding the original version of the FPGA; Characteristics of Crosspoint Solutions FPGAs.