252 results on '"Tuck, Barbara"'
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202. Who has the application expertise to build systems?
203. Chartered 0.35-...m process available.
204. Toward standards for mixing and matching IP blocks on...
205. Extending BIST to boards and MCMs.
206. Startup offers embedded solution.
207. A common fabric for IP portability.
208. Avant! Acquires Anagram and Meta-Software.
209. Have we created a monster?
210. Are we ready or not for model checkers?
211. Jury still out on synthesizable cores.
212. Now we need a methodology.
213. Analyzing Verilog for coding errors.
214. Explore area, speed tradeoffs.
215. Optimizing area and speed in ASICS.
216. Quickturn enhances software.
217. EDA tool bridges electrical and physical design.
218. Simulation and the verification bottleneck.
219. Analog licenses its DSP cores...
220. Making V-System kernel more accessible.
221. Taking baby steps to behavioral synthesis.
222. Synopsys strengthens submicron strategy.
223. Virtual Chips supports PCI cores.
224. Of Paris, intellectual property, and design reuse.
225. David, Goliath emulation partnership.
226. Library providers gain respect.
227. Where perception and reality don't meet.
228. Optimizing power at every level of design.
229. IBM offers 2.5-V, 0.35-micrometer ASICs.
230. Port libraries to new process.
231. Is shrinkwrapped EDA software an oxymoron?
232. Cycle-based speed without the headaches?
233. List of emulators to select is growing.
234. Third-party libraries are an attractive alternative.
235. Precedence to retain autonomy despite merger.
236. IBM cores provide the punch for powerful image processing.
237. IBM introduces PowerPC-based core methodology.
238. Static-timing sign-off is on the way.
239. Toshiba and LSI Logic up the ante on deep-submicron ASICs.
240. Formal verification tools increase in number, improve in quality.
241. Tools verify, test VHDL designs.
242. ArcSys, ISS join forces.
243. Making intellectual property accessible to you.
244. Back to the future.
245. Verilog HDL gets RC simulator.
246. Synopsys buys Arkos Design.
247. VHDL simulator claims speed edge.
248. How will Everyman design system-on-a-chip ASICs?
249. Antifuse-based FPGAs ship at 3.3 V.
250. Crosspoint Solutions back with FPGAs.
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