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Graphical abstract Abstract Alignment of densely packed single-walled carbon nanotubes (SWNTs) largely preserves the extraordinary electronic properties of individual SWNTs in the alignment direction, while in transverse direction the films are very resistive due to large energy barriers for tunneling between adjacent SWNTs. We demonstrate that chromium atoms inserted between the sidewalls of parallel SWNTs effectively coordinate to the benzene rings of the nanotubes via hexahapto bonds that preserve the nanotube-conjugated electronic structure and serve as a conduit for electron transfer. The atomically interconnected aligned SWNTs exhibit enhanced transverse conductivity, which increases by ∼2100% as a result of the photoactivated organometallic functionalization with Cr. The hexahapto mode of bonding the graphitic surfaces of carbon nanotubes with transition metal atoms offers an attractive route to the reversible chemical engineering of the transport properties of aligned carbon nanotube thin films. We demonstrate that a device fabricated with aligned SWNTs can be reversibly switched between a state of high electrical conductivity (ON) by light and low electrical conductivity (OFF) by applied potential. This study provides a route to the design of novel nanomaterials for applications in electrical atomic switches, optoelectronic and spintronic devices. [ABSTRACT FROM AUTHOR]

In this paper, we report a hierarchical simulation study of the electromigration (EM) problem in Cu-carbon nanotube (CNT) composite interconnects. This paper is based on the investigation of the activation energy and self-heating temperature using a multiscale electrothermal simulation framework. We first investigate the electrical and thermal properties of Cu-CNT composites, including contact resistances, using the density functional theory and reactive force field approaches, respectively. The corresponding results are employed in macroscopic electrothermal simulations taking into account the self-heating phenomenon. Our simulations show that although Cu atoms have similar activation energies in both bulk Cu and Cu-CNT composites, Cu-CNT composite interconnects are more resistant to EM thanks to the large Lorenz number of the CNTs. Moreover, we found that a large and homogenous conductivity along the transport direction in interconnects is one of the most important design rules to minimize the EM. [ABSTRACT FROM AUTHOR]

Direct-write processes offer several advantages over traditional lithographic techniques, including high processing speeds, high resolution, and the ability to fabricate complex 2D and 3D structures. Specifically, laser-induced forward transfer (LIFT) is a non-lithographic process that can be utilized to efficiently print numerous materials on various substrates with high precision. By using high viscosity nanopastes, structures can be printed with high positional accuracy that maintain the shape of the spatially structured laser beam. This capability lends itself to applications such as sensors and microelectronic components requiring features with narrow pitch. Because of the versatility of the LIFT process, interconnects can be printed directly onto the bond pads of both flip-chip devices in addition to directly onto substrates. In this work, we demonstrate the use of LIFT for printing highaspect ratio vertical micro-pillars combined with freestanding voxels to fabricate low profile interconnects on a bare die LED. [ABSTRACT FROM AUTHOR]

Control of grooved structured profiles can be achieved by a femtosecond laser ablation process in different materials - dielectrics, semi-conductors and metals. In addition, high accuracy additive manufacturing techniques, e.g. laser induced forward transfer (LIFT), provide flexibility in 3D printed structures deposited on a variety of substrates. The combination of those two laser technologies allows the integration of embedded circuitry and other components, such as microfluidic and micromechanical systems, paving the way to a wide range of applications where conventional subtractive patterning is a problem. Embedding is advantageous in terms of mechanical stability and adherence of the printed metal allowing a favorable aspect ratio and thereby providing improved electrical properties of the conducting lines as well as planar and debris-free surfaces. In this work we report on a combination of laser grooving and laser printing processes and demonstrate the manufacturing of buried copper structures in a grooved borosilicate glass substrate. [ABSTRACT FROM AUTHOR]

This article outlines the design, processing, and implementation of inkjet and 3D printing technologies for the development of fully printed, highly integrated millimeter-wave (mm-wave) wireless packages. The materials, tools, and processes of each technology are outlined and justified for their respective purposes. Inkjet-printed 3D interconnects directly interfacing a packaging substrate with an integrated circuit (IC) die are presented using printed dielectric ramps and coplanar waveguide transmission lines exhibiting low loss (.6-.8 dB/mm at 40 GHz). Stereolithography 3D printing is presented for the encapsulation of IC dice, enabling the application-specific integration of on-package structures, including dielectric lenses and frequency selective surface-based wireless filters. Finally, inkjet and 3D printing technology are combined to present sloped mm-wave interconnects through an encapsulant, or through mold vias, achieving a slope of up to 65° and low loss (.5-.6 dB/mm at 60 GHz). The combination of these additive techniques is highlighted for the development of scalable, application-specific wireless packages. [ABSTRACT FROM AUTHOR]

Ruthenium (Ru) and cobalt (Co) are new candidates for the replacement of physical vapor deposition tantalum (Ta) in liner materials because Ru and Co have excellent Cu-filling properties when deposited using chemical vapor deposition (CVD). Under accelerated current stressing conditions, Cu interconnects on a TaN/Co barrier showed an abrupt increase in resistance. The Cu resistance on a TaN/Ru barrier increased gradually and saturated with low deviation because voids generated randomly, and the Cu that remained on the Ru in the voids acted as shunt layers, preventing a sudden increase in resistance. Cu evolution tests on a Ru liner indicated that Cu had a strong bond with CVD Ru liner, even at high temperatures. These results suggest that Cu deposited on a TaN/Ru barrier can endure electromigration failure. [ABSTRACT FROM AUTHOR]

To solve electrical contact problem of horizontal multilayer graphene nanoribbon (GNR), a vertical GNR (VGNR) interconnect scheme is proposed. Performance of the VGNR interconnect is theoretically evaluated and compared with those of conventional interconnect technologies. It is shown that the performance of VGNR is comparable (and even superior) to that of the horizontal GNR (HGNR). Moreover, VGNRs may provide a promising solution to the thermal challenges faced by HGNRs in nanoscale ICs. [ABSTRACT FROM AUTHOR]

Abstract: Although high‐quality graphene can be produced on catalyst metals, their practical applications, especially Si technologies, are limited by the high‐temperature growth and the posttransfer process. A high‐performance system composed of W/nanocrystalline graphene (nc‐G)/TiN is realized for the long‐term downscaling of interconnect technology. The nc‐G is directly grown on noncatalytic TiN, up to 300 mm in diameter, at a low temperature of ≈560 °C, which is below the complementary metal‐oxide semiconductor integration temperature. The versatile roles of nc‐G in the interconnect are demonstrated: as a promoter of the preferential grain growth of the W layer, as a diffusion barrier to metal‐silicide formation, and as a proper adhesion layer with adjacent layers. Overall, a significant reduction (27%) in the resistance of the interconnect is achieved by the insertion of nc‐G between W and TiN. This work points to the possibility of practical graphene applications via direct nc‐G growth that is compatible with current Si technology. [ABSTRACT FROM AUTHOR]

Co has elicited a strong interest to replace Cu for future interconnect applications in microelectronic circuits due to its potentially lower resistivity and better reliability at scaled dimensions. Here, we demonstrate Co wires with electrical cross-sectional areas as small as 34 nm2 using a simple subtractive patterning technique. Semiclassical resistivity modeling of the wire resistivity indicates that grain boundary scattering is the dominant contribution for cross-sectional areas of the order of 100 nm2, while the contribution of surface scattering increases drastically below 50 nm2. Furthermore, wafer-level reliability tests of the Co wires show the high fusing current densities and a strong resistance to thermoelectric stress demonstrating the potential for robust reliability. The resistivity and the reliability of the Co wires are comparable with those of Ru wires. [ABSTRACT FROM AUTHOR]

Quasi-1D van der Waals materials, such as transition metal trichalcogenides, have strong covalent bonds in one direction and weaker bonds in cross-plane directions. They can be prepared as crystalline nanowires or nanoribbons consisting of 1D atomic threads, i.e., chains. We have examined the current carrying capacity of ZrTe3 nanoribbons using a set of structures fabricated by the shadow mask method. The bulk crystals were synthesized by the chemical vapor transport method and exfoliated onto Si/SiO2 substrates. It was found that ZrTe3 nanoribbons reveal an exceptionally high current density, on the order of ~100 MA/cm2, at the peak of the stressing DC current. The low-frequency noise was of 1/ ${f}$ type near room temperature ( ${f}$ is the frequency). The noise amplitude scaled with the resistance, following the trend established for other low-dimensional materials. The high current density in ZrTe3 can be attributed to the single-crystal nature of quasi-1D van der Waals materials. [ABSTRACT FROM AUTHOR]

In electronic assemblies, interconnects provide connections between electrical components both mechanically and electrically. During their use conditions, interconnects encounter multiple stress conditions such as temperature extremes, corrosion, and vibration. When these stress conditions are applied repeatedly, interconnects may lose their functionality, and the assemblies may eventually fail during the operation. As the consequence of electronics failure becomes critical, the need for reliable interconnects will grow. This paper demonstrates a prognostic approach for predicting remaining lifetime of solder joints in real-time. During stress testing, impedance has been reported to respond to early stages of solder joint degradation in the form of non-linear increases. These early responses were trended using support vector machine and compared with real-time impedance measurements for solder joint remaining life prediction. To evaluate the prediction performance, the impedance of a degrading solder joint was collected during mechanical fatigue testing, and the proposed approach was applied in real-time. During fatigue testing, the proposed approach successfully predicted solder joint failures over multiple trials. These results imply this prognostic approach can be an effective means for real-time health management of electronics and can be applied to systems whose performance variable demonstrates gradual changes prior to their end of life. [ABSTRACT FROM AUTHOR]

A novel partial element equivalent circuit (PEEC) formulation for solving full-Maxwell’s equations, with piecewise homogeneous and linear conductive, dielectric, and magnetic media, is presented. It is based on the cell method which by using integral variables as problem unknowns is naturally suited for developing circuit-like approaches such as PEEC. Volume meshing allows complex 3-D geometries, with electric and magnetic materials, to be discretized. Electromagnetic couplings in the air domain are modeled by integral equations. [ABSTRACT FROM AUTHOR]

Chromium poisoning is one of the major reasons for cathode performance degradation in solid oxide fuel cells (SOFCs). To mitigate the effect of Cr-poisoning, a protective coating on the surface of interconnect for suppressing Cr vaporization is necessary. Among the various coating materials, Cu-Mn spinel coating is considered to be a potential candidate due to their good thermal compatibility, high stability and good electronic conductivity at high temperature. In this study, Crofer 22 H meshes with no protective coating, those with commercial CuMn 2 O 4 spinel coating and the ones with lab-developed CuMn 1.8 O 4 spinel coating were investigated. The lab-developed CuMn 1.8 O 4 spinel coating were deposited on Crofer 22 H mesh by electrophoretic deposition and densified by a reduction and re-oxidation process. With these different Crofer 22 H meshes (bare, CuMn 2 O 4 -coated, and CuMn 1.8 O 4 -coated), anode-supported SOFCs with Sr-doped LaMnO 3 -based cathode were electrochemically tested at 800 °C for total durations of up to 288 h. Comparing the mitigating effects of the two types of Cu-Mn spinel coatings on Cr-poisoning, it was found that the performance of the denser lab-developed CuMn 1.8 O 4 spinel coating was distinctly better, showing no degradation in the cell electrochemical performance and significantly less Cr deposition near the cathode/electrolyte interface after the test. [ABSTRACT FROM AUTHOR]

Crossing strip junctions form an important discontinuity problem in differential signaling an pose a major challenge for signal integrity modeling throughout an analysis in high-speed designs. An analytical framework is proposed to characterize differential transmission lines including the effect of crossing strip junctions for broadband circuit analysis. A new analytical model is proposed to include the finite thickness in the existing models for characterization of asymmetric striplines. The proposed modular representation of the differential line segments with discontinuity effects allows for an entire high-speed transmission channel with crossing lines to be modeled in a cascaded fashion for efficient signal integrity analysis. [ABSTRACT FROM AUTHOR]

The effect of different substrates, inks and sintering methods on the breakdown of a printed conducting trace subjected to a single millisecond-range pulsed current was investigated. The breakdown current density ( J b ) of a trace was found to be strongly dependent on substrate thermal diffusivity, which dictates the peak temperature and the cooling rate of the trace. As an example, a 102% increase in average J b was observed in switching substrate from glass slide to sapphire. Different inks resulted in significant J b deviation due to their distinct microstructure difference. Traces with dense microstructure exhibited an average J b that is 42% higher than their porous counterpart. Different sintering methods also resulted in varying J b . Traces thermally sintered on a hot plate demonstrated an average J b that is 74% higher than their laser sintered counterpart. Finally, a simple concept that effectively dissipates heat from the trace was explored. It prevented breakdown when the traces were subjected to a single firing pulse used in detonation. Results from this work offer important considerations in printing conductive traces for high pulsed power applications. [ABSTRACT FROM AUTHOR]

In this work x-ray photoelectron spectroscopy is used to investigate in-vacuo, the interaction of metallic manganese with a (3-trimethoxysilylpropyl)diethylenetriamine (DETA) self-assembled monolayer (SAM) on SiO 2 and non-porous low-k dielectric materials. Subsequent deposition of a ∼0.5 nm thick Mn, followed by a 200 °C anneal results in the Mn diffusing through the SAM to interact with the underlying SiO 2 layer to form a Mn-silicate layer. Furthermore, there is evidence that the Mn interacts with the carbon and nitrogen within the SAM to form Mn-carbide and Mn-nitride, respectively. When deposited on low-k materials the Mn is found to diffuse through to the SAM on deposition and interact both with the SAM and the underlying substrate in a similar fashion. [ABSTRACT FROM AUTHOR]

Fitting of sampled frequency response data to a rational function is often required for macromodeling of advanced microelectronic packages. The pole residue equivalent system solver (PRESS) method was recently proposed, as a novel fitting method that builds the global fit from local fits, computed from at most three data points at an error peak. To increase the fitting accuracy of PRESS, the error-maxima agnostic PRESS (EMPRESS) was proposed, but it is computationally intensive as the central processing unit needs to sequentially perform the local fits at all the frequency sample points before choosing the best among them. In this paper, we propose the parallel optimized EMPRESS (POEMPRESS) to reduce the computational complexity of EMPRESS while improving the fitting performance. POEMPRESS optimizes both the EMPRESS algorithm and its implementation through: 1) simplified local fit types, enabling the algorithm to rely on at most two data points only, and 2) an algorithm that can be implemented on graphics processing units for rapid parallel computation and evaluation of local fits at all the frequency points. The proposed algorithm is demonstrated on the interconnects of a microelectronic package. The results show that POEMPRESS is effective in fast macromodeling of complex interconnects for signal and power integrity simulations. [ABSTRACT FROM AUTHOR]

The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16nm ITRS technology node. A standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10m interconnect length at temperatures (233K, 300K and 378K). Our analysis shows that MLGNR exhibits (-) less SSN and (-) less IR-Drop as compared with traditional Cu-based power interconnects. Our analysis also shows that the average percentage of reduction in peak SSN is 52-32% (at 233K), 53-32% (at 300K) and 52-30% (at 378K) less in MLGNR compared with traditional Cu-based power interconnect and the average percentage of reduction in peak IR-Drop in MLGNR is 54-31% (at 233K), 57-29% (at 300K) and 57-26% (at 378K) less than that of Cu-based power interconnects. [ABSTRACT FROM AUTHOR]

Rapidly increasing demand for higher data bandwidths has motivated exploration of new communication channels based on spatially multiplexed in-fibre and on-chip coupled light guides. However, the conventionally used periodically arranged coupled waveguides display complicated light propagation patterns, ranging from quasiperiodic to nearly chaotic. Taking a different approach, we spectrally engineer interwaveguide coupling to instigate self-imaging of the input light state at the array output and thus enable construction of novel high-fidelity interconnects. Simple implementation via modulation of the interwaveguide separations makes these interconnects realizable in all fabrication platforms. Their competitive advantages are negligible crosstalk-induced information loss, high density that exceeds the current standards by an order of magnitude, and compatibility with both classical and quantum information encoding schemes. Moreover, the wavelength-dependent self-imaging opens up new possibilities for wavelength and spatial division demultiplexing. The proposed analytical designs are supported by extensive numerical simulations of silicon-on-insulator, silicon nitride and silica glass waveguide arrays, and a statistical feasibility study. • Novel interconnects based on linearly coupled waveguide arrays. • High-fidelity information transfer without the crosstalk-induced loss. • An order of magnitude higher channel density than in conventional interconnects. • Inverse design applicable to the long-haul, short-range and on-chip interconnects. • Compatible with the standard modulation formats, classical and quantum encoding. [ABSTRACT FROM AUTHOR]

As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic interconnects face several serious challenges in aspects of performance and reliability. To address these issues, nanocarbon materials, including carbon nanotube (CNT) and graphene, have been proposed as promising candidates for interconnect applications. Considering the rapid development of nanocarbon interconnects, this paper is dedicated to providing a mini-review on our previous work and on related research in this field.

Constant evolution of technology is leading to the improvement of electronical devices. Smaller, lighter, faster, are but a few of the properties that have been constantly improved, but these developments come hand in hand with negative downsides. In the case of miniaturization, this shortcoming is found in the inherent property of conducting materials—the limit of current density they can withstand before failure. This property, known as ampacity, is close to reaching its limits at the current scales of use, and the performances of some conductors such as gold or copper suffer severely from it. The need to find alternative conductors with higher ampacity is, therefore, an urgent need, but at the same time, one which requires simultaneous search for decreased density if it is to succeed in an ever-growing electronical world. The uses of these carbon nanotube-based materials, from airplane lightning strike protection systems to the microchip industry, will be evaluated, failure mechanisms at maximum current densities explained, limitations and difficulties in ampacity measurements with different size ranges evaluated, and future lines of research suggested. This review will therefore provide an in-depth view of the rare properties that make carbon nanotubes and their hybrids unique.

Drying of stencil-, screen-, or dispense-printed paste is a crucial, yet taken-for-granted, presintering step for sinterable-silver (SS) interconnect processing and ultimately its reliability. If the paste’s solvent is not sufficiently removed during drying, then entrapped gas can result, and that leads to the formation of thermal-, strength-, and reliability-limiting defects in the later-sintered interconnect layer. Presently advocated drying strategies for wet silver paste cause either a limit of associated size or area or require pressure assistance during subsequent sintering. Alternatively, open-face contact drying (OContDry) from contact heating or conductive heating (a method used in industrial processes) offers the potential to overcome those limitations with SS paste. However, satisfactory strength of its final sintered structure must be proven prior to any potential adoption. In this paper, the achievement of a combination of relatively large shear failure stress with low scatter for OContDry SS was demonstrated. This is significant because OContDry enables greater processing versatility with SS interconnects and several other advantages too. [ABSTRACT FROM PUBLISHER]

A new integral-equation-based formulation is presented enabling the modeling of lossy dielectrics, such as silicon, in the framework of the partial element equivalent circuit (PEEC) method, in the time domain. Due to the reduced value of conductivity of the lossy dielectric, charge is not restricted to its surface, e.g., the relaxation time is not as small as in standard conductors. This requires the PEEC method to be reformulated in order to consider both the conductivity of the dielectric material and the reduced value of the electrical conductivity, which prevents the charge to be located only on the surfaces. The proposed new PEEC model is validated through comparison with results available from the theory and commercial software. Then, the proposed method is used to analyze two silicon interconnects showing how the finite even small electrical conductivity of silicon may have a significant impact on the results compared with the ideal behavior of the dielectric. [ABSTRACT FROM AUTHOR]

This work details efforts to estimate the direct manufacturing cost of solid oxide fuel cell (SOFC) stack components for combined heat and power applications. The main research goals are to identify the major contributors to fuel cell stack manufacturing costs, examine the influence of both production volume and stack size on cost, and compare the results of the cost trajectories with the U.S. Department of Energy SOFC stack manufacturing cost target of $238 kWe−1 (in 2015) and industry reported cost projections and to identify critical areas for manufacturing research and development. Stack component direct manufacturing costs are modeled for net electricity capacity of 1, 10, 50, 100 and 250 kWe across annual production volumes of 10, 1,000, 10,000 and 50,000 systems per year. Overall stack manufacturing costs range from $5,387 kWe−1 to a minimum of about $166 kWe−1 for a 250 kWe system at 50,000 systems per year. To meet the manufacturing cost target of $238 kWe−1, a minimum annual production of 100-250 MWe per year would be required. Reduction opportunities for stack cost are expected to be available, mainly with the adoption of thinner cells and stack components, higher levels of factory automation, and more sensitive in-line defect diagnostics. [ABSTRACT FROM AUTHOR]

High-current carrying capacity and superior thermal conductivity have made multiwall carbon nanotubes (MWCNTs) a material for next-generation interconnects. Its distinct electrical and thermal properties result in various physical phenomenon, interaction among which give rise to unique electro-thermal transport. The interaction aggravates in presence of high-electric fields, which generally occur under ESD conditions. In this paper, we present detailed investigation of electro-thermal transport through MWCNTs under ESD conditions. The role of the substrate, MWCNT shells, and sub-bands in ESD current conduction is highlighted, while considering two device architectures—suspended and dielectric-supported MWCNTs. The quantum electron–phonon transport under non-equilibrium (ESD) conditions is explained using CNT band structure and interplay between electrical and thermal transport along the nanotube. The investigation highlights the role of the dielectric substrate in mitigating the detrimental effects of ESD stress. A strong dependence of failure current on metal-MWCNT contact resistance is revealed. The overall breakdown mechanism is found to follow Wunsch–Bell model, indicating a direct scaling between the rate of oxidation of MWCNT shells and injected power. [ABSTRACT FROM PUBLISHER]

Multiwall carbon nanotube (MWCNT)-based interconnects have been shown to outperform conventional metal interconnects. For reliable operation of such interconnects, it is imperative to evaluate their reliability at possible fatal events. Here, we report the ESD reliability of MWCNT-based interconnects. High failure current of ~10 mA and unique failure behavior involving discrete and gradual breakdown of individual shells is reported. It was found that MWCNT interconnects change resistance in steps of fundamental quantum resistance ( h/2e^2 ) after individual shell burning. The role of individual shells, diameter, and resistance of the tube in deciding the ESD behavior is investigated, while monitoring the response on a shell-by-shell basis. Contrary to widespread notion of immunity of MWCNT interconnects to electromigration, the ESD-induced melting of contacts is also observed. [ABSTRACT FROM PUBLISHER]

Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase ( α -W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step. The W liner with thicknesses ranging from 3 to 4 nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances. [ABSTRACT FROM AUTHOR]

The main aim of the presented study was to investigate the possibility of application of one of the newest group of materials – black glasses, in the form of protective-conducting coatings on metallic interconnects in Solid Oxide Fuel Cells (SOFC). Materials, obtained using the sol-gel method, with use of novel silsesquioxanes precursors, were deposited on ferritic stainless steel Crofer 22APU substrate via dip-coating and then heat-treated in protective atmosphere of argon at 800 °C. Structural studies of the resulting coatings i.e. XRD and MIR confirm formation of black glass structure while microstructural studies i.e SEM with EDS allowed to assess their compactness and homogeneity. The effectiveness of black glass coatings in the protective role was evaluated by the oxidation kinetics tests performed for 100 h in a laboratory air atmosphere at 800 °C in isothermal conditions. Additional microstructural studies (SEM with EDS and XRD) of both surfaces and cross-sections of the tested samples, after treatment in the simulated aggressive working environment of SOFC, proved protective properties of the investigated materials. The electrical properties of coatings were studied with the use of direct current (DC) two-probe four-point technique at temperatures ranging from 500 to 800 °C, showing an acceptable level of the area-specific resistance of the oxidized coatings around 0.1 [Ω·cm 2 ]. The presented results show that the black glass-based protective-conductive coatings have a significant potential in the proposed application. [ABSTRACT FROM AUTHOR]

We present an investigation into the effects of photon lifetime and the associated damping of the modulation response on 50 Gbps 4-pulse-amplitude modulation (4-PAM) signal generation with directly modulated 25G class vertical-cavity surface-emitting lasers (VCSELs). While 4-PAM benefits from higher slope efficiency and output power, it is shown that the greater impact of intensity noise and dynamic nonlinearities implies that a VCSEL with a longer photon lifetime and more damped response is needed when transitioning from existing 25 Gbps OOK to 50 Gbps 4-PAM using the 25G VCSEL technology. [ABSTRACT FROM PUBLISHER]

The continuous scaling of copper (Cu) interconnects produced two major shortcomings-a severe resistivity size effect and material reliability issues. Tungsten (W), with the expected reduction in resistivity size effect due to its shorter electron mean free path and improved reliability due to its high activation energy for diffusion, is a worthwhile candidate to replace Cu. In this article, the potential of W for future interconnects is critically discussed by reviewing the current status of W technology, including various W processing methods and the resulting phases, resistivity and microstructure. The compatibility of W with the back-end-of-line processes in CMOS devices is also discussed. The resistivity of W and Cu wires at similar nanoscale is compared based on the Fuchs-Sondheimer surface scattering model and Mayadas-Shatzkes grain boundary scattering model using the reported scattering parameters ( p = 0.11 and R = 0.42 for W, and p = 0.52 and R = 0.43 for Cu), which shows that the resistivity of W wires is predicted to exhibit lower resistivity than that of Cu wires at line-widths below ~15 nm. Finally, anisotropy in the resistivity size effect in W wires is discussed, with a suggested method to reduce wire resistivity. [ABSTRACT FROM AUTHOR]