Search

Character segmentation is an important stage in Automatic Number Plate Recognition systems as good character separation leads to a high recognition rate. This paper presents an improved character segmentation algorithm based on pixel projection and morphological operations. An efficient architecture based on the proposed algorithm is also presented. The architecture has been successfully implemented and verified using the Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-Gate Xilinx Virtex-4 LX40. A database of 1,000 UK binary NPs with varying resolution has been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can process a number plate image in 0.2---1.4 ms with 97.7 % successful segmentation rate and consumes only 11 % of the available area in the used FPGA.

The Internet of Things (IoT) holds great promises to provide an edge cutting technology that enables numerous innovative services related to healthcare, manufacturing, smart cities and various human daily activities. In a typical IoT scenario, a large number of self-powered smart devices collect real-world data and communicate with each other and with the cloud through a wireless link in order to exchange information and to provide specific services. However, the high energy consumption associated with the wireless transmission limits the performance of these IoT self-powered devices in terms of computation abilities and battery lifetime. Thus, to optimize data transmission, different approaches have to be explored such as cooperative transmission, multi-hop network architectures and sophisticated compression techniques. For the latter, compressive sensing (CS) is a very attractive paradigm to be incorporated in the design of IoT platforms. CS is a novel signal acquisition and compression theory that exploits the sparsity behavior of most natural signals and IoT architectures to achieve power-efficient, real-time platforms that can grant efficient IoT applications. This paper assesses the extant literature that has aimed to incorporate CS in IoT applications. Moreover, the paper highlights emerging trends and identifies several avenues for future CS-based IoT research.

This paper presents a gas identification system which is part of an ongoing research project aiming to develop a low power reconfigurable self-calibrated multi-sensing platform for gas applications where real time parameters such as temperatures and gas concentrations are monitored. The gas identification system is based on decision tree classifier; training is performed in MATLAB environment. It is first carried out using the steady states extracted from the raw data obtained from the sensors, and then using transformed data by applying principal component analysis. The data used for training is collected from a 16-Array SnO2 gas sensor. The sensor array is exposed to three types of gases (CO, C2H6O and H2) at ten different concentrations (20, 40, 60, 80, 100, 120, 140, 160, 180 and 200ppm). The resulting models are implemented in C and synthesized using Vivado High Level Synthesis tool for rapid prototyping on the heterogeneous Zynq platform.

This paper describes an image processing algorithm and its efficient architecture. The proposed architecture is used to process images of microelectrode arrays (MEAs) and micro-wells captured by a microscope camera in a dielectrophoresis (DEP)-based system which consists as well of digital switches for turning the DEP force 'on' or 'off'. The images are processed in order to determine if a neuron has entered any of the micro-wells in which case the corresponding switch turns 'off' the DEP force. This process must be in real-time to avoid more than one cell to be loaded in a micro-well. The proposed architecture has been successfully implemented and tested on a Zynq SoC. Results achieved have shown that the system can process one image in 9 ms which meets the minimum real-time requirements of this DEP system. 2015, UK Simulation Society. All rights reserved. Scopus

Gas detection is one of the major processes that has to be taken into consideration as an important part of a monitoring system for production and distribution of gases. Gas is a critical resource. Therefore, for safety reason, it is imperative to keep monitoring in real time all parameters such as temperature, concentration and mixture. The presented research in this abstract on gas identification is part of an ongoing research project aiming at the development of a low power reconfigurable self-calibrated multi-sensing platform for gas applications. Gas identification system can be described as a pattern recognition problem. Decision tree classifier is a widely used classification technique in data mining due to its low implementation complexity. It is a supervised learning that consists in a succession of splits that leads to the identification of the predefined classes. The decision tree algorithm has been applied and evaluated for the hardware implementation of a gas identification system. The data used for training is collected from a 16-Array SnO2 gas sensor, the sensor array is exposed to three types of gases (CO, Ethanol and H2) at ten different concentrations (20, 40, 60, 80, 100, 120, 140, 160, 180 and 200ppm), the experiment is repeated twice to generate 30 patterns for training and another 30 patterns for testing. Training is performed in MATLAB. It is first done using the raw data, which is the steady states, and then using transformed data by applying principal component analysis. Table 1 shows the decision tree training results. These include the trees obtained from the learning on the original data and on different combinations of principal components. The resulted models are implemented in C and synthesised using Vivado High Level Synthesis (HLS) tool for a quick prototyping on the heterogeneous Zynq platform. Table 2 illustrates the on-chip resources usage, maximum running frequency and latency for the implementation of the trained decision tree models. The use of Vivado HLS helped to optimise the hardware design by applying different directives such as the one that allow loop unrolling for a better parallelism. The best performance is obtained when the first three principal components were used for the training which resulted in an accuracy of 90%. The hardware implementation illustrated that a trade-off is to be found between the accuracy of the identification and the performance in terms of processing time. It is planned to use drift compensation techniques to get more accurate steady states and increase the performance of the system. The system can be easily adapted to other types of gases by exposing the new gas to the sensor array, collecting the data, performing the training and finally implementing the model.

Clipping is a potential treatment for ruptured/unruptured brain aneurysm patients. In order to determine the profitable treatment and also clip's location, surgeons need to have the measurements such as velocity and blood pressure in and around the aneurysm.Typically, simulating the blood fluid and finding the corresponding measurements require heavy computation resources. The Lattice Boltzmann (LB) method is the conventional way to simulate the fluid dynamics and HemeLB is an open-source computational suite for 3D fluid dynamics simulations of blood flow in the vasculature of the human body. In this work, we aim to evaluate the hardware acceleration of LB and HemeLB on reconfigurable system on chip (SoC) and high performance computing (HPC) machine using RAAD platform.

The production of hazardous gases due to different physicochemical reactions in gas industries have raised the need of autonomous sensor tag. However the adaptation of remotely controlled sensor tag is still suffering with many challenges, among which power consumption, selectivity and durability are the most prominent problems in gas application. Therefore in this paper, a reconfigurable multi-sensing platform is presented for gas applications. A low power ring-oscillator based temperature and tin-oxide based gas sensors are utilized to indicate the temperature and type of the gas with a total power of few μW's. The processing unit is designed on a heterogeneous ZynQ platform and a passive radio frequency identification (RFID) tag is designed to provide communication between the sensors and the processing unit. Qatar National Research Fund (QNRF) under the National Priority Research Program (NPRP) No. 5-080-2-028. Scopus

Principal component analysis (PCA) is a commonly used technique for data reduction in general as well as for dimensionality reduction in gas identification systems when a sensor array is being used. This paper presents the design and implementation of a complete PCA IP core for gas application on the Zynq programmable system on chip (SoC). All steps of PCA starting from the mean computation to the projection of data onto the new space, passing by the normalization process, covariance matrix and the eigenvectors computation are developed in C and synthesized using the new Xilinx VIVADO high level synthesis (HLS). The Jacobi method is used to find the eigenvectors and different approaches for the implementation of the PCA core on the heterogeneous Zynq platform are proposed. The hardware implementation of the presented PCA algorithm for a 16 x 30 matrix is faster than the software one with a speed up of 1.41 times when executed on a desktop running a 64-bit Intel i7-3770 processor at 3.40GHz. It was achieved using an average of 23% of all resources. 2013 IEEE. Scopus

Automatic Number Plate Recognition (ANPR) system becomes an important research topic in Intelligent Transportation systems (ITS). More recently, high-definition (HD) cameras are used for providing better performance in ANPR system. However, most known approaches for standard definition (SD) number plate localisation (NPL) are not suitable for real-time HD image processing as the real-time requirement cannot be met due to the computationally intensive cost of localising the number plate. In this paper, a solution to link previously designed architectures for NPL, character segmentation and character recognition in a SD ANPR system is first described. The system is to be implemented on a single stand-alone FPGA-based processing unit. An approach to extend the SD ANPR system to HD ANPR system without significantly increasing the computational cost is then introduced. 2013 IEEE. Scopus

The ARM-DSP based ANPR system described is designed for commercial applications where the need for low power, low prices and real time systems is vital. A single FPGA can also be added as a plug-in to the ARM-DSP based hardware SoC, depending on the extra resources needed for the application. The overall results have shown that it is possible to use cheaper off-the-shelf ARM-DSPs and FPGAs multicore processors for standalone ANPR systems through device and algorithm optimisation to achieve real-time performance at higher recognition rate using efficient algorithms. 2013 IEEE. Scopus

Automatic Number Plate Recognition (ANPR) systems have become one of the most important components in the current Intelligent Transportation Systems (ITS). In this paper, a FPGA implementation of a complete ANPR system which consists of Number Plate Localisation (NPL), Character Segmentation (CS), and Optical Character Recognition (OCR) is presented. The Mentor Graphics RC240 FPGA development board was used for the implementation, where only 80% of the available on-chip slices of a Virtex-4 LX60 FPGA have been used. The whole system runs with a maximum frequency of 57.6 MHz and is capable of processing one image in 11ms with a successful recognition rate of 93%. 2013 IEEE. Scopus

This paper presents an overview of a PhD research project, completed tasks and future work. The aim of the research is to contribute to the improvement of gas identification systems at different levels by designing and implementing dedicated IP cores for data analysis, pre-processing, dimensionality reduction and pattern recognition algorithms. This PhD dissertation research is part of an ongoing funded research project by NPRP-Qatar Foundation which consists of the development of a low power reconfigurable self-calibrated multi-sensing platform for gas applications. 2013 IEEE. Scopus

Optical Character Recognition (OCR) is the last stage in an Automatic Number Plate Recognition System (ANPRs). In this stage the number plate characters on the number plate image are converted into encoded texts. In this paper, an Artificial Neural Network (ANN) based OCR algorithm for ANPR application is presented. A database of 3700 UK binary character images have been used for testing the performance of the proposed algorithm. Results achieved have shown that the proposed algorithm can meet the real-time requirement of an ANPR system and can averagely process a character image in 8.4ms with 97.3% successful recognition rate.

This paper proposes an upgrade scenario for xDSL networks to provide broadband access for extended link lengths while demonstrating network grooming by means of more than one subscriber using a single network connection concurrently. This is achieved by applying direct spread code division multiple access (DS-CDMA) in a fiber-to-the-cabinet (FTTC) topology by means of a field programmable gate array (FPGA), used to demonstrate simultaneous user transmission and system-on-chip (SoC) network element generation. Experimental results have displayed efficiency in ADSL link rates of 66% and 41% for back-to-back and 12 km-reach fiber links respectively.

The nature of some scientific computing applications involves performing complex tasks repeatedly on floating-point data, often under real-time requirements. Therefore, high performance systems are required by the developers for fast computations. Many researchers have begun to recognize the potential of reconfigurable hardware such as field-programable gate arrays in implementing floating-point arithmetic. In this paper a floating-point adder and multiplier are presented. The proposed cores are used as basic components for the implementation of a parallel floating-point matrix multiplier designed for 3D afflne transformations. The cores have been implemented on recent FPGA devices. The performance in terms of area/speed of the proposed architectures has been assessed and has shown that they require less area and can be run with a higher frequency when compared with existing systems.

In this paper we present a design for an efficient FPGA implementation of a color space converter in video compression. The proposed architecture is based on distributed arithmetic principles has been implemented on the Xilinx Virtex-2000E FPGA using a hybrid design approach combining Handel-C and VHDL. Maximum optimization of performance metrics including frequency and power has been achieved by careful manual floor planning of the design, with particular attention paid to the critical paths and pin assignment. Additionally, a novel functional level power analysis and modeling using non-linear regression analysis has been developed using power and energy data obtained for different combinations of system parameters.

3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine transformations. A proposed solution based on processing large matrix multiplication has been implemented, for large 3D models, on the RC1000-PP Celoxica board based development platform using Handel-C, a C-like language supporting parallelism, flexible data size and compilation of high-level programs directly into FPGA hardware.

Matrix multiplication is very important in many types of applications including image and signal processing. This paper presents an investigation into the design and implementation of matrix product algorithm using different design approaches such as Handel-C and VHDL, where the performance of both programming languages have been presented. Solutions for processing large matrix products based partitioning methodology have been described. The proposed system has been implemented and verified using the RC1000-PP Celoxica board based development platform.

Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power, plus the ability to experiment with algorithms. To try to meet the dual requirements of high performance and ease of development, in this work we present a High Level framework for the implementation of FFTs for real-time image processing applications. The frequency-domain (convolution-based) image filtering problem is targeted by developing an FPGA-based parametrisable environment based on the proposed parallel 2-D FFT architecture for real-time operation. Results show that the parallel implementation of 2-D FFT achieves virtually linear speed-up and real-time performance for large matrix sizes.

3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, Computer Aided Design (CAD) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA) devices as a low cost solution for implementing 3D affine trans formations. A proposed solution based on processing large matrix multiplication has been implemented, for large 3D models, on the RC1000-PP Celoxica board based development platform using Handel-C, a C-like language supporting parallelism, flexible data size and compilation of high-level programs directly into FPGA hardware.

Processing an image in the RGB color space, with a set of RGB values for each pixel is not the most efficient method. To speed up some processing steps many video compression and communication techniques use luminance/chrominance color spaces, such as YCrCb, making a mechanism for converting between formats necessary. Therefore, techniques which efficiently implement this conversion are desired. This paper presents a novel architecture for efficient implementation of two such color space converters (CSC) suitable for field programmable gate array (FPGA) and VLSI. The proposed architecture is based on distributed arithmetic (DA) ROM accumulator principles. The architecture has been implemented and verified using the Celoxica RC1000-PP FPGA development board. The implementation approach exhibits better performance when compared with existing implementations.

This paper presents two novel architectures for efficient implementation of a Color Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000-PP FPGA development board. In addition, they are platform independent and have a low latency (8 cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/seconds.

This paper presents novel architectures for efficient implementations of matrix product using an FPGA based parameterizable system. These operations are important in many signal and image processing applications including image and speech compression, filtering, coding and beamforming. Two novel architectures for matrix multiplication using both systolic architecture and distributed arithmetic design methodologies are presented. The first approach uses the Baugh-Wooley algorithm for a systolic architecture implementation. The second approach Is based on both distributed arithmetic ROM and accumulator structure. Implementations of the algorithms on a Xilinx FPGA board are described. Distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.

Matrix algorithms are important in many types of applications including image and signal processing. These areas require enormous computing power. A close examination of the algorithms used in these, and related, applications reveals that many of the fundamental actions involve matrix operations such as matrix multiplication which is of O (N3) on a sequential computer and O (N3/p) on a parallel system with p processors complexity. This paper presents an investigation into the design and implementation of different matrix algorithms such as matrix operations, matrix transforms and matrix decompositions using an FPGA based environment. Solutions for the problem of processing large matrices have been proposed. The proposed system architectures are scalable, modular and require less area and time complexity with reduced latency when compared with existing structures.© (2003) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

There have been a large number of fast Fourier transform (FFT) algorithms which have been developed over the years. Among these algorithms, the most promising are the Radix-2, Radix-4, Split-Radix and fast Hartley transform (FHT). In this paper we present an investigation into the design and implementation of the above mentioned FFT algorithms using Handel-C - a recently developed C-like programming language for compilation of high-level programs directly into FPGA hardware. The algorithms have been implemented and verified on the Celocixa RC1000 FPGA development board. A detailed evaluation has also been reported based on maximum system frequency, chip area and computation time.

Matrix algorithms are important in many types of applications including image and signal processing. A close examination of the algorithms used in these, and related, applications reveals that many of the fundamental actions involve matrix algorithms such as matrix multiplication. This paper presents an investigation into the design and implementation of different matrix algorithms such as matrix operations, matrix transforms and matrix decompositions using a novel custom coprocessor system for MATrix algorithms based on Reconfigurable Computing (RCMAT). The proposed RCMAT architectures are scalable, modular and require less area and time complexity with reduced latency when compared with existing structures.

3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, computer aided design or visualisation applications. This article investigates the suitability of field programmable gate array devices as an accelerator for implementing 3D affine transformations. Proposed solution based on processing large matrix multiplication have been implemented, for large 3D models, on the RC1000 Celoxica board based development platform using Handel-C. Outstanding results have been obtained for the acceleration of 3D transformations using fixed and floating-point arithmetic.

Matrix multiplication is very important in many types of applications including image and signal processing. The suitability of reconfigurable hardware devices, in the form of field programmable gate arrays (FPGAs), is investigated as a low-cost solution for implementing two matrix multipliers for 3-D affine transformations and colour space conversion. A first solution based on processing large matrix multiplication, for large 3-D models, and for the evaluation of the Celoxica fixed-point library and Xilinx CoreGen performance has been reported. A novel architecture for efficient implementation of a colour space converter (CSC) based on distributed arithmetic (DA) principles has been presented. The two multipliers have been developed and implemented on the RC1000-PP Celoxica board-based development platform. Results show that the FPGA-based first parallel multiplier can achieve the performance of a graphics card when performing 3-D affine transformations, while the second multiplier, which is fully pipelined and platform-independent, has a low latency (8 cycles) and is capable of a sustained data rate of over 234 mega-conversions per second.

Consciousness about power consumption at the appliance level can assist user in promoting energy efficiency in households. In this paper, a superior non-intrusive appliance recognition method that can provide particular consumption footprints of each appliance is proposed. Electrical devices are well recognized by the combination of different descriptors via the following steps: (a) investigating the applicability along with performance comparability of several time-domain (TD) feature extraction schemes; (b) exploring their complementary features; and (c) making use of a new design of the ensemble bagging tree (EBT) classifier. Consequently, a powerful feature extraction technique based on the fusion of TD features is proposed, namely fTDF, aimed at improving the feature discrimination ability and optimizing the recognition task. An extensive experimental performance assessment is performed on two different datasets called the GREEND and WITHED, where power consumption signatures were gathered at 1 Hz and 44000 Hz sampling frequencies, respectively. The obtained results revealed prime efficiency of the proposed fTDF based EBT system in comparison with other TD descriptors and machine learning classifiers., This article has been accepted in ISCAS 2020, Seville, Spain, 2020

The Zynq-7000 based platforms are increasingly being used in different applications including image and signal processing. The Zynq system on chip (SoC) architecture combines a processing system based on a dual core ARM Cortex processor with a programmable logic (PL) based on a Xilinx 7 series field programmable gate arrays (FPGAs). Using the Zynq platform, real-time hardware acceleration can be performed on the programmable logic and controlled by a software running on the ARM-based processing system (PS). In this paper, a design and implementation of a gas identification system on the Zynq platform which shows promising results is presented. The gas identification system is based on a 16- Array SnO2 gas sensor, principal component analysis (PCA) for dimensionality reduction and decision tree (DT) for classification. The main part of the system that will be executed on the PL for hardware acceleration takes the form of an IP developed in C and synthesized using Vivado High Level Synthesis for the conversion from C to register transfer level, a hardware design for the entire system that allows the execution of the IP on the PL and the remaining parts of the identification system on the PS is developed in Vivado using IP Integrator. The communication between the processing system and programmable logic is performed using advanced extensible interface protocol (AXI). A software application is developed and executed on the ARM processor to control the hardware acceleration on the programmable logic of the previously designed IP core and the board is programmed using Software Development Kit. The maximum accuracy achieved by the system to classify three types of gases CO, C2H6O and H2 is 96.66%. 2006-2015 Asian Research Publishing Network (ARPN). This paper was made possible by National Priorities Research Program (NPRP) grant No. 5 - 080 - 2 - 028 from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors. Scopus

The convergence of computers, the Internet and a wide variety of video devices, all using different color representations, is forcing the digital designers today to convert between them. The objective is to have a common color space that all inputs are converted to before algorithms and processes are executed. This paper presents a novel architecture for efficient implementation of a color space conversion suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architecture is based on Distributed Arithmetic (DA) ROM accumulator principles. In addition, it is fully pipelined, platform independent, has a low latency (8 cycles) and a high throughput rate.