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We have developed an automated, compile time approach to generating error-detecting parallel programs. The compiler is used to identify statements implementing affine transformations within the program and automatically insert code for computing, manipulating, and comparing checksums in order to check the correctness of the code implementing affine transformations. Statements which do not implement affine transformations are checked by duplication. Checksums are reused from one loop to the next if this is possible, rather than recomputing checksums for every statement. A global dataflow analysis is performed in order to determine points at which checksums need to be recomputed. We also use a novel method of specifying the data distributions of the check data using directives provided by the High Performance Fortran (HPF) standard so that the computations on the original data and the corresponding check computations are performed on different processors. Results are presented on an Intel Paragon distributed memory multicomputer.

The design and implementation of portable, efficient, and expressive mechanisms for I/O on complex distributed data structures—such as found in adaptive parallel applications—is a challenging problem that we address in this paper. We describe the design, programmer interface, implementation, and performance of pC++/streams , a library that provides an expressive mechanism for I/O on distributed arrays of variable-sized objects in pC++, an object-parallel language. pC++/streams is intended for developers of parallel programs requiring efficient high-level I/O abstractions for checkpointing, scientific visualization, and debugging. pC++/streams is an implementation of d/streams , a language-independent abstraction for buffered I/O on distributed data structures. We describe the d/streams abstraction and present performance results on the Intel Paragon and SGI Challenge showing that d/streams can be implemented efficiently and portably.

The upwind leapfrog scheme for electromagnetic scattering is briefly described. Its application to the 3D Maxwell`s time domain equations is shown in detail. The scheme`s use of upwind characteristic variables and a narrow stencil result in a smaller demand in communication overhead, making it ideal for implementation on distributed memory parallel computers. The algorithm`s implementation on two message passing computers, a 1024-processor nCUBE 2 and a 1840-processor Intel Paragon, is described. Performance evaluation demonstrates that the scheme performs well with both good scaling qualities and high efficiencies on these machines.

Simulating a supersonic wake flow field behind a conical body is a computing intensive task. It requires a large number of computational cells to capture the dominant flow physics and a robust numerical algorithm to obtain a reliable solution. High performance parallel computers with unique distributed processing and data storage capability can provide this need. They have larger computational memory and faster computing time than conventional vector computers. We apply the PINCA Navier-Stokes code to simulate a wind-tunnel supersonic wake experiment on Intel Gamma, Intel Paragon, and IBM SP2 parallel computers. These simulations are performed to study the mean flow in the near wake region of a sharp, 7-degree half-angle, adiabatic cone at Mach number 4.3 and freestream Reynolds number of 40,600. Overall the numerical solutions capture the general features of the hypersonic laminar wake flow and compare favorably with the wind tunnel data. With a refined and clustering grid distribution in the recirculation zone, the calculated location of the rear stagnation point is consistent with the 2D axisymmetric and 3D experiments. In this study, we also demonstrate the importance of having a large local memory capacity within a computer node and the effective utilization of the number of computermore » nodes to achieve good parallel performance when simulating a complex, large-scale wake flow problem.« less

This report summarizes the third phase of a Cooperative Research and Development Agreement between Oak Ridge National Laboratory and Intel in evaluating a 28-node Intel Paragon MP system. An MP node consists of three 50-MHz i860XP`s sharing a common bus to memory and to the mesh communications interface. The performance of the shared-memory MP node is measured and compared with other shared-memory multiprocessors. Bus contention is measured between processors and with message passing. Recent improvements in message passing and I/O are also reported.

In this paper we present an implementation of an MPEG1 encoder on the Intel Touchstone Delta and Intel Paragon parallel computers. We describe the unique aspects of mapping the algorithm onto the parallel machines and present several versions of the algorithms. We will show that I/O contention can be a bottleneck relative to performance. We will also describe how the Touchstone Delta and Paragon can be used to compress video sequences faster than real-time.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

This report describes EDONIO (Extended Distributed Object Network I/O), an enhanced version of DONIO (Distributed Object Network I/O Library) optimized for the Intel Paragon Systems using the new M-ASYNC access mode. DONIO provided fast file I/O capabilities in the Intel iPSC/860 and Paragon distributed memory parallel environments by caching a copy of the entire file in memory distributed across all processors. EDONIO is more memory efficient by caching only a subset of the disk file at a time. DONIO was restricted by the high memory requirements and use of 32-bit integer indexing to handle files no larger than 2 Gigabytes. EDONIO overcomes this barrier by using the extended integer library routines provided by Intel`s NX operating system. For certain applications, EDONIO may show a ten-fold improvement in performance over the native NX I/O routines.

Abstract Key to the development of an efficient parallel reservoir simulator is the implementation of an efficient parallel linear equation solver Although recent advances in distributed memory parallel computers have seen a significant improvement in communications overhead among the processors, increases in processor performance have kept the ratio of communications to node performance about the same. Previous published parallel linear equation solvers have emphasized the importance of reduced communications and increased granularity for the solver partitioning among the processors. This study investigates the implementation of asynchronous message-passing schemes to further reduce communications overhead for the parallel solver. The basic idea is for each processor to proceed with the linear solution without interruption from waiting to receive messages. If data is available in the buffer from other processors, however, it is utilized. This study implements an asynchronous parallel preconditioner for ORTHOMIN(k). The preconditioner has two parts: Z-line relaxation and a block incomplete LU factorization (ILU(O)). Also included in the solution is the use of a reduced three-dimensional subproblem which is solved on one of the processors. Because of the asynchronous implementation of the solver, each of the nodes may perform a different number of iterations and converge to different tolerances; however, the overall tolerance for convergence is checked periodically to determine when the linear solution can be halted. This technique has been implemented on the IBM SP2, Intel IPSC/860 and Intel Paragon with problem sizes varying from 4096 to 184,320 grid blocks. For the largest problem significant performance improvements were observed. For the range of problems investigated the linear solution technique showed excellent robustness and efficiencies. Number of iterations increased only slightly with increasing number of nodes. Moreover, speedups of up to 26 and 37 were observed for 32 and 64 nodes, respectively, for the largest problem investigated. P. 507

Analysis of modern aerospace vehicles requires the computation of flowfields about complex three dimensional geometries composed of regions with varying spatial resolution requirements. Overset grid methods allow the use of proven structured grid flow solvers to address the twin issues of geometrical complexity and the resolution variation by decomposing the complex physical domain into a collection of overlapping subdomains. This flexibility is accompanied by the need for irregular intergrid boundary communication among the overlapping component grids. This study investigates a strategy for implementing such a static overset grid implicit flow solver on distributed memory, MIMD computers; i.e., the 128 node Intel iPSC/860 and the 208 node Intel Paragon. Performance data for two composite grid configurations characteristic of those encountered in present day aerodynamic analysis are also presented.

Rapid increases in computing and communication performance are exacerbating the long-standing problem of performance-limited input/output. Indeed, for many otherwise scalable parallel applications. input/output is emerging as a major performance bottleneck. The design of scalable input/output systems depends critically on the input/output requirements and access patterns for this emerging class of large-scale parallel applications. However, hard data on the behavior of such applications is only now becoming available. In this paper, we describe the input-output requirements of three scalable parallel applications (electron scattering, terrain rendering, and quantum chemistry, on the Intel Paragon XP/S. As part of an ongoing parallel input/output characterization effort, we used instrumented versions of the application codes to capture and analyze input/output volume, request size distributions, and temporal request structure. Because complete traces of individual application input/output requests were captured, in-depth, off-line analyses were possible. In addition, we conducted informal interviews of the application developers to understand the relation between the codes' current and desired input/output structure. The results of our studies show a wide variety of temporal and spatial access patterns, including highly read-intensive and write-intensive phases, extremely large and extremely small request sizes, and both sequential and highly irregular access patterns. We conclude with a discussion of the broad spectrum of access patterns and their profound implications for parallel file caching and prefetching schemes.

The purpose of the molecular interaction program DOT (Daughter of Turnip) is rapid computation of the electrostatic potential energy between two proteins or other charged molecules. DOT exhaustively tests all six degrees of freedom, rotational and translational, and produces a grid of approximate interaction energies and orientations. It is able to do this because the problem is cast as the convolution of the potential field of the first molecule and any rotated charge distribution of the second. The algorithm lends itself to both parallelization and vectorization, permitting huge increases in computational speed over other methods for obtaining the same information. For example, a complete mapping of interactions between plastocyanin and cytochrome c was done in eight minutes using 256 nodes of an Intel Paragon. DOT is expected to be particularly useful as a rapid screen to find configurations for more detailed study using exact energy models.

Publisher Summary This chapter uses the block Jacobi method for the calculation of the supersonic flow over the proposed aircraft Alliance, which uses a 56 processor Intel Paragon. This computation is a typical industrial application where the mesh generation provides a multi block mesh where the number of blocks is much smaller than the number of available processors. It is found that the efficient parallel calculations can be carried out even for a large number of blocks using a block Jacobi procedure. The obtained MFLOP rate on a 56 processor Intel Paragon is about 2.3 times that of what is obtained on a single Cray Y/MP processor. The most important factor determining the total CPU time is, however, the convergence rate, which is strongly dependent on the block partitioning. The chapter presents examples where an increase in load balance is totally outweighed by an increase in the number of time steps to reach convergence due to undesirable block shapes. A decomposition algorithm is, therefore, required that takes into account the numerical efficiency as well as load balance and communication.

We introduce Remote Queues (RQ), a communication model that integrates polling with selective interrupts to support a wide range of applications and communication paradigms. We show that polling is desirable for a range of applications for both performance and atomicity. Polling enables optimizations that are essential for fine-grain applications such as sparse-matrix solution. Polling also improves flow control for high-level communication patterns such as transpose. We use RQ to implement active messages, bulk transfers, and fine-grain applications on the MIT Alewife, Intel Paragon and Cray T3D using extremely different implementations of RQ. RQ improves performance on all of the machines, and provides atomicity guarantees that greatly simplify programming for the user. RQ also separates handler invocation from draining the network, which simplifies deadlock avoidance and multiprogramming. We also introduce efficient atomicity mechanisms on Alewife to integrate polling with interrupts, and discuss how to exploit interrupts on Alewife and the Intel Paragon without forfeiting the atomicity and optimization advantages of RQ.

We present an overview of the locally self-consistent multiple scattering (LSMS) method. The method is based on real space multiple scattering theory, is naturally highly parallel, and has been implemented on Intel Paragon parallel platforms within the Center for Computational Sciences at Oak Ridge National Laboratory. O(N)-scaling is demonstrated for unit cells as large as 1000-atoms. We discuss in detail how the real space convergence properties of the method can be controlled by taking advantage of the stationary properties of a finite temperature Harris-Foulkes free energy functional. We show how the LSMS method can be combined with spin-dynamics to treat non-collinear magnetic states of materials. We show some preliminary results for the ground state magnetic structure of FCC Fe0.6 5Ni 0.35 alloys that indicate the possible existence of non-collinear arranges of magnetic moments in this system.

Processing element allocation is a fundamental service for the efficiency and performance of today's partitionable scalable high performance computing (SHPC) systems. In this paper we give an overview of different partitioning policies and introduce a Partition Management Tool (PMT) we developed. PMT could be integrated into the Intel Paragon's ParAide tool environment and is a major step towards an easy and efficient partition management.

The simulation of long range air pollution using regional scale models requires a substantial amount of CPU-time on traditional supercomputers and should be able to benefit substantially from effective parallel algorithms. In this paper we describe a continuous domain decomposition algorithm for advection-diffusion equations. The algorithm is applied to an air pollution model, involving advection in the horizontal directions and advection-diffusion and chemical reactions in the vertical direction. The parallel model has been implemented on the Intel Paragon. The numerical experiments shows that the parallel algorithm scales well and the results for the full parallel model are encouraging with respect to the possibilities for operational use.

Communication in a parallel system frequently involves moving data from the memory of one node to the memory of another; this is the standard communication model employed in message passing systems. Depending on the application, we observe a variety of patterns as part of communication steps, e.g., regular (i.e. blocks of data), strided, or irregular (indexed) memory accesses. The effective speed of these communication steps is determined by the network bandwidth and the memory bandwidth, and measurements on current parallel supercomputers indicate that the performance is limited by the memory bandwidth rather than the network bandwidth.Current systems provide a wealth of options to perform communication, and a compiler or user is faced with the difficulty of finding the communication operations that best use the available memory and network bandwidth. This paper provides a framework to evaluate different solutions for inter-node communication and presents the copy-transfer model; this model captures the contributions of the memory system to inter-node communication. We demonstrate the usefulness of this simple model by applying it to two commercial parallel systems, the Cray T3D and the Intel Paragon.In particular we identify two methods to transfer data between nodes in these two machines. In buffer-packing transfers, a contiguous block of data is transferred across the network. If the data are not stored contiguously, they are copied to (gathering) or from (scattering) buffers in local memory before and after the transfer. Chained transfers perform gathering, transfer and scattering in one step, reading the data elements with some non-sequential pattern and immediately transferring them on to the destination.Our model and measurements indicate that chaining of the gather, transfer, and scatter operations results in better performance than buffer packing for many important access patterns. Most standard message passing libraries (like MPI, PVM or NX) force the parallelizing compiler (or the programmer) to employ the buffer-packing communication operations. However, the addition of hardware support dedicated to communication (e.g., DMAs, line-transfer units) now gives the compiler a wider range of options.

Publisher Summary Recent advances in the architectures of scalable or massively parallel processors have provided a cost-effective way to achieve high-performance computational fluid dynamics computation. In the compressible viscous flow, both explicit and implicit schemes are widely used. The explicit codes, such as the FLO57, the MDNS3D, and the RAMPANT, based on the Runge–Kutta marching scheme with structured or unstructured grids are almost parallel. Near linear speed-up, efficiency of 96% performance has been achieved. Partitioning strategies of unstructured grids are still ongoing research topics. The implicit solvers, such as the ARC3D, based on the Beam–Warming scheme can be effectively parallelized. The parallelization strategies are discussed in this chapter. It also presents results on one of the NAS parallel benchmarks—block tridiagonal (BT). The NAS-BT represents the computations associated with the ARC3D code. In the incompressible flow, the chapter illustrates the pressure-correction SIMPLEC algorithm with a modified QUICK scheme. In the transient flow, time parallelism is introduced in the chapter into the fully implicit time-stepping algorithm using Womble's parallel time-stepping.

A serial code for 2D seismic depth migration has been ported to a parallel platform. Only small modifications of the serial code was necessary. The porting was done using portable parallel primitives, such that the same code can be run on a number of parallel and serial machines. The computing time scales well with the number of processors on an Intel Paragon. The result shows that 32 processors on the Paragon machine are about 10 times faster than an IBM RS6000/580 workstation, and 25 times faster than a SUN Sparc 10 workstation.

We propose a parallel object-oriented language, called OCore. OCore is designed to generate efficient code especially for multi-computers. As a research vehicle for massively parallel computation models, advanced communication models, and optimization techniques, OCore supports the notion of community, meta-level architecture, and a distributed garbage collection mechanism on top of a fundamental concurrent object-oriented layer. OCore supports both control- and data-parallel programming. A prototype language processing system for the Intel Paragon XP/S and Sun SPARC stations is currently available.

We discuss the results of a collaborative project on parallel processing of Synthetic Aperture Radar (SAR) data, carried out between the NASA/Jet Propulsion Laboratory (JPL), the California Institute of Technology (Caltech) and Intel Scalable Systems Division (SSD). Through this collaborative effort, we have successfully parallelized the most compute-intensive SAR correlator phase of the Spaceborne Shuttle Imaging Radar-C/X-Band SAR (SIR-C/X-SAR) code, for the Intel Paragon. We describe the data decomposition, the scalable high-performance I/O model, and the node-level optimizations which enable us to obtain efficient processing throughput. In particular, we point out an interesting double level of parallelization arising in the data decomposition which increases substantially our ability to support ''high volume'' SAR. Results are presented from this code running in parallel on the Intel Paragon. A representative set of SAR data, of size 800 Megabytes, which was collected by the SIR-C/X-SAR instrument aboard NASA's Space Shuttle in 15 seconds, is processed in 55 seconds on the Concurrent Supercomputing Consortium's Paragon XP/S 35+. This compares well with a time of 12 minutes for the current SIR-C/X-SAR processing system at JPL. For the first time, a commercial system can process SIR-C/X-SAR data at a rate which is approaching the rate at which the SIR-C/X-SAR instrument can collect the data. This work has successfully demonstrated the viability of the Intel Paragon supercomputer for processing ''high volume" Synthetic Aperture Radar data in near real-time.

Interconnection networks with nearly distance independent communication latency are a key feature of recent architectures. However, shared resources such as network channels can become bottlenecks that degrade performance and limit workload scalability.

Multicomputers can be effectively used for interactive graphics rendering only if there are mechanisms available to rapidly composite and transfer images to an external display device. One method for achieving the necessary bandwidth for this operation is to provide multiple high-bandwidth ports into a frame buffer. In this paper, we evaluate the design space of a multiport frame buffer design for the Intel Paragon mesh routing network. We use an instrumented rendering system to capture the graphics operations needed for rendering a number of three-dimensional scenes; we then use those workloads as input to test programs running on the Paragon to estimate the performance of our hardware. Our experiments consider three major design questions: how many network ports the frame buffer needs, whether Z-Buffering should be done in hardware on the frame buffer or in software on the computing nodes, and whether the design alternatives are scalable.

The locally self-consistent multiple scattering method is applied to ab initio spin-polarized local density approximation calculations for ferromagnetic CuNi alloys. The samples used to model the alloys are constructed with experimentally measured short range order parameters. These large cell calculations are performed using the Intel Paragon XP/S massively parallel processing supercomputer. The neutron magnetic diffuse scattering cross sections are calculated and compared with experiment. The dependence of magnetic moment formation on the local environment is discussed.

This report describes the use of shared memory emulation with DOLIB (Distributed Object Library) to simplify parallel programming on the Intel Paragon. A molecular dynamics application is used as an example to illustrate the use of the DOLIB shared memory library. SOTON PAR, a parallel molecular dynamics code with explicit message-passing using a Lennard-Jones 6-12 potential, is rewritten using DOLIB primitives. The resulting code has no explicit message primitives and resembles a serial code. The new code can perform dynamic load balancing and achieves better performance than the original parallel code with explicit message-passing.

Large-scale distributed systems are very attractive for the execution of parallel applications requiring a huge computing power. However, their high probability of site failure is unacceptable, especially for long time running applications. In this paper, we address this problem and propose a checkpointing mechanism relying on a recoverable distributed shared memory (DSM) in order to tolerate single node failures. Although most recoverable DSMs require specific hardware to store recovery data, our scheme uses standard memories to store both current and recovery data. Moreover, the management of recovery data is merged with the management of current data by extending the DSM's coherence protocol. This approach takes advantage of the data replication provided by a DSM in order to limit the amount of transferred pages during the checkpointing. The paper also presents an implementation and a preliminary performance evaluation of our recoverable DSM on a 56-node Intel Paragon. >

After the proposal for HPF had been finalized, it took only a very short time until the first compilers were visible at the surface; mainly those from APR and PGI. The parallel programming-model of HPF covers the partitioning of data-arrays at compile-time and data- and DO-loop-distribution onto PEs according to the owner sets rule. Non-distributed data-arrays and scalars are replicated. Efficiency can be achieved through a good work- and data-partitioning onto PEs.

Synthesizing architectural requirements from an application viewpoint can help in making important architectural design decisions towards building large scale parallel machines. In this paper, we quantify the link bandwidth requirement on a binary hypercube topology for a set of five parallel applications. We use an execution-driven simulator called SPASM to collect data points for system sizes that are feasible to be simulated. These data points are then used in a regression analysis for projecting the link bandwidth requirements for larger systems. The requirements are projected as a function of the following system parameters: number of processors, CPU clock speed, and problem size. These results are also used to project the link bandwidths for other network topologies. Our study quantifies the link bandwidth that has to be made available to limit the network overhead in an application to a specified tolerance level. The results show that typical link bandwidths (200-300 MBytes/sec) found in current commercial parallel architectures (such as Intel Paragon and Cray T3D) would have fairly low network overhead for the applications considered in this study. For two of the applications, this overhead is negligible. For the other applications, this overhead can be limited to about 30% of the execution time provided the problem sizes are increased commensurate with the processor clock speed. The technique presented can be useful to a system architect to synthesize the bandwidth requirements for realizing well-balanced parallel architectures.

This paper presents performance results for ZPL programs running on the Kendall Square Research KSR-2 and the Intel Paragon. Because ZPL is a data parallel language based on the Phase Abstractions programming model, these results complement earlier claims that the Phase Abstractions model can lead to portability across MIMD computers. The ZPL language and selected aspects of the compilation strategy are briefly described, and performance results are compared against hand-coded programs.

The study of plasma turbulence and transport is a complex problem of critical importance for fusion-relevant plasmas. To this day, the fluid treatment of plasma dynamics is the best approach to realistic physics at the high resolution required for certain experimentally relevant calculations. Core and edge turbulence in a magnetic fusion device have been modeled using state-of-the-art, nonlinear, three-dimensional, initial-value fluid and gyrofluid codes. Parallel implementation of these models on diverse platforms--vector parallel (National Energy Research Supercomputer Center`s CRAY Y-MP C90), massively parallel (Intel Paragon XP/S 35), and serial parallel (clusters of high-performance workstations using the Parallel Virtual Machine protocol)--offers a variety of paths to high resolution and significant improvements in real-time efficiency, each with its own advantages. The largest and most efficient calculations have been performed at the 200 Mword memory limit on the C90 in dedicated mode, where an overlap of 12 to 13 out of a maximum of 16 processors has been achieved with a gyrofluid model of core fluctuations. The richness of the physics captured by these calculations is commensurate with the increased resolution and efficiency and is limited only by the ingenuity brought to the analysis of the massive amounts of data generated.

This report describes the use of shared memory emulation with DOLIB (Distributed Object Library) to simplify parallel programming on the Intel Paragon. A molecular dynamics application is used as an example to illustrate the use of the DOLIB shared memory library. SOTON-PAR, a parallel molecular dynamics code with explicit message-passing using a Lennard-Jones 6-12 potential, is rewritten using DOLIB primitives. The resulting code has no explicit message primitives and resembles a serial code. The new code can perform dynamic load balancing and achieves better performance than the original parallel code with explicit message-passing.

Parallel computing offers an attractive means for high-performance computing to alleviate the current bottleneck in speedup potential of large application codes for practical problem solving. The challenge of actual implementation, however, can be significant The objective of this report is to address the issue of porting and parallelizing a Computational Fluid Dynamics (CFD) application code on several supercomputing platforms such as Cray C-90, Cray Y-MP, KSRl, CM-S and Intel PARAGON. This overall objective is achieved through first emulating the application code by conducting a model test code, in an effort to understand the influence of data structure on the code performance. The conclusions derived from this are then utilized to restructure the 2-D/3-D CFD code such that the final version is transportable to a wider class of platforms.

This paper describes the design and implementation in MPI of the parallel vector library CVL, which is used as the basis for implementing nested data-parallel languages such as NESL and Proteus. We compare the ease of writing and debugging the portable MPI implementation of CVL with our experiences writing previous versions in CM-2 Paris, CM-5 CMMD, and PVM, and give initial performance results for MPI CVL running on an IBM SP-1, Intel Paragon, and TMC CM-5.

This document describes the work on Message Passing Interface (MPI) standard implementation of the parallel version of the solver EARTH for the Computational Fluid Dynamics (CFD) program PHOENICS. The Intel Paragon NX and MPI versions of the program have been developed and tested on massively parallel (MP) supercomputers Intel Paragon XP/S 5, XP/S 35, and Kendall Square Research (KSR) supercomputers at Oak Ridge National Laboratory (ORNL). The preliminary testing results of the developed program have shown scalable performance for reasonably sized computational domains.

This paper focuses on a nonparametric regression technique known as locally-weighted regression or LOESS, LOESS is a computationally intensive technique which makes it naturally amenable to exploiting high performance computers. In this paper, we explore domain decomposition techniques for LOESS and study the performance of our algorithm on an Intel Paragon XP/S A4 machine. We study both speedup and efficiency as a function of the number of nodes. Certain segments of the LOESS computation are shown to be fruitfully parallelized while others are essentially sequential and cannot be parallelized effectively.

This report describes the use and implementation of DOLIB (Distributed Object Library), a library of routines that emulates global or virtual shared memory on Intel multiprocessor systems. Access to a distributed global array is through explicit calls to gather and scatter. Advantages of using DOLIB include: dynamic allocation and freeing of huge (gigabyte) distributed arrays, both C and FORTRAN callable interfaces, and the ability to mix shared-memory and message-passing programming models for ease of use and optimal performance. DOLIB is independent of language and compiler extensions and requires no special operating system support. DOLIB also supports automatic caching of read-only data for high performance. The virtual shared memory support provided in DOLIB is well suited for implementing Lagrangian particle tracking techniques. We have also used DOLIB to create DONIO (Distributed Object Network I/O Library), which obtains over a 10-fold improvement in disk I/O performance on the Intel Paragon.

Experiences and performance figures are reported from early tests of the 512-node Intel Paragon XPS35 at Oak Ridge National Laboratory. Computation performance of the 50 MHz i860XP processor as well as communication performance of the 200 megabyte/second mesh are reported and compared with other multiprocessors. Single and multiple hop communication bandwidths and latencies are measured. Concurrent communication speeds and speed under network load are also measured. File I/O performance of the mesh-attached Parallel File System is measured. Early experiences with OSF/Mach and SUNMOS operating systems are reported, as well results from porting various distributed-memory applications. This report also summarizes the second phase of a Cooperative Research and Development Agreement between Oak Ridge National Laboratory and Intel in evaluating a 66-node Intel Paragon XPS5.

SUNMOS is an acronym for Sandia/UNM Operating System. It was originally developed for the nCUBE-2 MIMD supercomputer between January and December of 1991. Between April and August of 1993, SUNMOS was ported to the Intel Paragon. This document provides a quick overview of how to compile and run jobs using the SUNMOS environment on the Paragon. The primary goal of SUNMOS is to provide high performance message passing and process support an example of its capabilities, SUNMOS Release 1.4 occupies approximately 240K of memory on a Paragon node, and is able to send messages at bandwidths of 165 megabytes per second with latencies as low as 42 microseconds using Intel NX calls. By contrast, Release 1.2 of OSF/1 for the Paragon occupies approximately 7 megabytes of memory on a node, has a peak bandwidth of 65 megabytes per second, and latencies as low as 42 microseconds (the communication numbers are reported elsewhere in these proceedings).

The impact of two different operating systems OSF, and SUNMOS available on the NAS Paragon, on the performance of applications has been studied and investigated. In OSF, paging of the unused part of the server and management of the virtual memory by the operating system degrades the performance of the applications by as much as by 40% in some of the cases studied. The influence of the data cache on the performance of the applications under both OSF and SUNMOS using one-dimensional (1-D) Fast Fourier transform (FFT) and three-dimensional (3-D) FFT has also been investigated. The performance of NAS Parallel Benchmarks is reported, and the scalability issues of the machine and the algorithms under both OSF and SUNMOS are considered.

A pseudo-random number generator is presented which makes optimal use of the architecture of the i860-microprocessor and which is expected to have a very long period. It is therefore a good candidate for use on the parallel supercomputer Paragon XP. In the assembler version, it needs 6.4 cycles for a real∗4 random number. There is a FORTRAN routine which yields identical numbers up to rare and minor rounding discrepancies, and it needs 28 cycles. The FORTRAN performance on other microprocessors is somewhat better. Arguments for the quality of the generator and some numerical tests are given.

We propose an efficient parallel implementation of the Swendsen-Wang algorithm for a 3D Ising system. A modified relaxation method was used for the parallelization. The simulations were performed on the Intel Paragon. We discuss the implementation in detail.

We established a fast Swendsen-Wang algorithm for the two-dimensional Ising model on parallel computers with a high efficiency. On an Intel paragon with 140 processors we reached spin update times of only 14 ns with an efficiency of 89%. This algorithm was used to examine the non-equilibrium relaxation of magnetization and energy in large Ising systems of a size up to 17920 × 17920 spins. Nevertheless we observed still a strong finite-size effect for the magnetization. We assume both magnetization and energy decay to behave like (t + Δ)-λe-bt in an infinitely large system. Thus, for long times magnetization and energy show an exponential, asymtotic time-dependence, implying a critical dynamic exponent z of zero.

We have developed a flexible hybrid decomposition parallel implementation of the first-principles molecular dynamics algorithm of Car and Parrinello. The code allows the problem to be decomposed either spatially, over the electronic orbitals, or any combination of the two. Performance statistics for 32, 64, 128 and 512 Si atom runs on the Touchstone Delta and Intel Paragon parallel supercomputers and comparison with the performance of an optimized code running the smaller systems on the Cray Y-MP and C90 are presented., Comment: Accepted by Computer Physics Communications, latex, 34 pages without figures, 15 figures available in PostScript form via WWW at http://www-theory.chem.washington.edu/~wiggs/hyb_figures.html

Parallel computer systems have reached a share of interest that is already far beyond the sacred halls of universities and research laboratories. The amount of performance delivered today theoretically allows for the tackling of so called grand challenge problems. But there is still the software-gap that keeps us from fully exploiting the performance of such systems.

This report describes the use and implementation of DONIO (Distributed Object Network I/O), a library of routines that provide fast file I/O capabilities in the Intel iPSC/860 and Paragon distributed memory parallel environments. DONIO caches a copy of the file in memory distributed across all processors. Disk I/O routines (such as read, write, and lseek) are replaced by calls to DONIO routines, which translate these operations into message communication to update the cached data. Experiments on the Intel Paragon show that the cost of concurrent disk I/O using DONIO for large files can be 15-30 times smaller than using standard disk I/O.

Much computational power on state-of-the-art multicomputers like the Paragon is wasted with porting applications. Using networks of workstations is an attempt to withdraw this workload from multicomputer systems. Therefore an environment is needed which provides the programming interface of multicomputers on coupled workstations. The paper describes the design and implementation of the NXLib environment which allows to use Ethernet coupled workstations as a development platform for applications targeted for Intel Paragon systems.

This report describes the use and implementation of DOLIB (Distributed Object Library), a library of routines that emulates global or virtual shared memory on Intel multiprocessor systems. Access to a distributed global array is through explicit calls to gather and scatter. Advantages of using DOLIB include: dynamic allocation and freeing of huge (gigabyte) distributed arrays, both C and FORTRAN callable interfaces, and the ability to mix shared-memory and message-passing programming models for ease of use and optimal performance. DOLIB is independent of language and compiler extensions and requires no special operating system support. DOLIB also supports automatic caching of read-only data for high performance. The virtual shared memory support provided in DOLIB is well suited for implementing Lagrangian particle tracking techniques. We have also used DOLIB to create DONIO (Distributed Object Network I/O Library), which obtains over a 10-fold improvement in disk I/O performance on the Intel Paragon.

The program outlined here is directed to research on methods, algorithms, and software for distributed parallel supercomputers. Of particular interest are finite element methods and finite difference methods together with sparse iterative solution schemes for scientific and engineering computations of very large-scale systems. Both linear and nonlinear problems will be investigated. In the nonlinear case, applications with bifurcation to multiple solutions will be considered using continuation strategies. The parallelizable numerical methods of particular interest are a family of partitioning schemes embracing domain decomposition, element-by-element strategies, and multi-level techniques. The methods will be further developed incorporating parallel iterative solution algorithms with associated preconditioners in parallel computer software. The schemes will be implemented on distributed memory parallel architectures such as the CRAY MPP, Intel Paragon, the NCUBE3, and the Connection Machine. We will also consider other new architectures such as the Kendall-Square (KSQ) and proposed machines such as the TERA. The applications will focus on large-scale three-dimensional nonlinear flow and reservoir problems with strong convective transport contributions. These are legitimate grand challenge class computational fluid dynamics (CFD) problems of significant practical interest to DOE. The methods developed and algorithms will, however, be of wider interest.

In this note the authors describe the results of some tests of the message-passing performance of the Intel Paragon. These tests have been carried out under both the Intel-supplied OSF/1 operating system with an NX library, and also under an operating system called SUNMOS (Sandia UNM Operating System). For comparison with the previous generation of Intel machines, they have also included the results on the Intel Touchstone Delta. The source code used for these tests is identical for all systems. As a result of these tests, the authors can conclude that SUNMOS demonstrates that the Intel Paragon hardware is capable of very high bandwidth communication, and that the message coprocessor on Paragon nodes can be used to give quite respectable latencies. Further tuning can be expected to yield even better performance.