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This paper shown that millisecond annealing effectively suppresses the B diffusion in Germanium after ion implantation, and provides much higher activation efficiency of acceptors compared to conventional annealing methods.

Hybrid quantum devices enable novel functionalities by combining the benefits of different subsystems. Particularly, point defects in nanomechanical resonators made of diamond or silicon carbide (SiC) have been proposed for precise magnetic field sensing and as versatile quantum transducers. However, the realization of a hybrid system may involve tradeoffs in the performance of the constituent subsystems. In a spin-mechanical system, the mechanical properties of the resonator may suffer from the presence of engineered defects in the crystal lattice. This may severely restrict the performance of the resulting device and needs to be carefully explored. Here, we focus on the impact of defects on high Q nanomechanical string resonators made of pre-stressed 3C-SiC grown on Si(111). We use helium ion implantation to create point defects and study their accumulated effect on the mechanical performance. Using Euler-Bernoulli beam theory, we present a method to determine Young’s modulus and the pre-stress of the strings. We find that Young’s modulus is not modified by implantation. Under implantation doses relevant for single defect or defect ensemble generation, both tensile stress and damping rate also remain unaltered. For higher implantation dose, both exhibit a characteristic change.

This study explores defect engineering in 2D materials using ion beam irradiation to modify the electrical and optical properties with potential in advancing quantum electronics and photonics. Helium and neon ions ranging from 5 to 7.5 keV are employed to manipulate charge transport in monolayer molybdenum disulfide (MoS2). In situ electrical characterization occurs without vacuum breakage post-irradiation. Raman and photoluminescence spectroscopy quantify ion irradiation’s impact on MoS2. Small doses of helium ion irradiation enhance monolayer MoS2 conductivity in field-effect transistor geometry by inducing doping and substrate charging. Findings reveal a strong correlation between the electrical properties of MoS2 and the primary ion used, as well as the substrate on which the irradiation occurred. Using hexagonal boron nitride (h-BN) as a buffer layer between MoS2 flake and SiO2 substrate yields distinct alterations in electrical behavior subsequent to ion irradiation compared to the MoS2 layer directly interfacing with SiO2. Molecular dynamics simulations and density functional theory provide insight into experimental results, emphasizing substrate influence on measured electrical properties post-ion irradiation.

Brownian dynamics simulations are utilized to study segregation phenomena far from thermodynamic equilibrium. In the present study, we expand upon the analysis of binary colloid mixtures and additionally introduce a third particle species to further our understanding of colloidal systems. Gravitationally driven, spherical colloids immersed in an implicit solvent are confined in two-dimensional linear microchannels. The interaction between the colloids is modeled by the Weeks-Chandler-Andersen potential, and the confinement of the colloids is realized by hard walls based on the solution of the Smoluchowski equation in half space. In binary and ternary colloidal systems, a difference in the driving force is achieved by differing colloid sizes, but fixed mass density. We observe for both the binary and ternary systems that a driving force difference induces a nonequilibrium phase transition to lanes. For ternary systems, we study the tendency of lane formation in dependence of the diameter of the medium-sized colloids. Here, we find a sweetspot for lane formation in ternary systems. Furthermore, we study the interaction of two differently sized colloids at the channel walls. Recently, we observed that driven large colloids push smaller colloids to the walls. This results in small particle lanes at the walls at early simulation times. In this work, we additionally find that thin lanes are unstable and dissolve over very long time frames. Furthermore, we observe a connection between lane formation and the nonuniform distribution of particles along the channel length. This nonuniform distribution occurs either alongside lane formation or in shared lanes (i.e. lanes consisting of two colloid types).

DNA and RNA offer fascinating possibilities for the self-organisation of complex patterns, which can be used in various combinations. Since this self-organisation occurs at the nanometer scale, it can possibly offer ways for the creation of nanooptical or nanoelectronic devices. Therefore, the quest for conductivity of DNA or RNA has inspired a vast amount of experiments which have led to a large number of diverse results. In the recent past, a coherent picture has emerged which describes charge transport along DNA or RNA in various environments. Based on this, electronic applications of these biomolecules have been developed.

Measured resistance as a function of nanowire (NW) width for different modulation doped Si NWs.

DNA origami is a powerful tool to fold 3-dimensional DNA structures with nanometer precision. Its usage, however, is limited as high ionic strength, temperatures below ~60 °C and pH values between 5 to 10 are required to ensure the structural integrity of DNA origami nanostructures. Here, we demonstrate a simple and effective method to stabilize DNA origami nanostructures against harsh buffer conditions using [PdCl4]2-. It provided the stabilization of different DNA origami nanostructures against mechanical compression, temperatures up to 100 °C, double-distilled water and pH values between 4 to 12. Additionally, DNA origami superstructures and bound cargos are stabilized with a yield of 98 %. To demonstrate the general applicability of our approach, we employed our protocol to a Pd metallization procedure at elevated temperatures. In the future, we think that our method opens up new possibilities for applications of DNA origami nanostructures beyond their usual reaction conditions.

Transistor measurements

The file "figures.hdf5" contains all numbers plotted in the figures of the main manuscript. Each entry in the first hierarchy level of the file, e.g. "Figure 2a", corresponds to one subfigure. Each entry in the second hierarchy level (if existent) corresponds to one of the curve/subset of the the respective figure, e.g. if curves for multiple fluences are plotted. The innermost hierarchy level contains the data arrays. The dataset name corresponds to the axis label and units. The file "analyzed.hdf5" contains frequencies, quality factors, stress and Young's modulus fit results for each measured nanostring device on each measured sample. The first hierarchy level represents the sample (A or B). The second hierarchy level represents the accumulated implantation fluence that the sample has seen before the respective measurements. The third hierarchy level represents the write field, i.e. string array index, on the chip (0-3) and the fourth hierarchy level represents the string length within the write field. Each length exists exactly once in each write field. The innermost hierarchy level contains arrays of mode number, frequency, quality factor and "raw data indices" (see next paragraph) representing each measured resonance. The fields Young's modulus and pre-stress are scalars containing the respective fit result and its uncertainty. The file "raw.hdf5" finally contains all raw spectra. The first hierarchy level corresponds to unique indices of the respective measurement. This is intended as a look up table for the "raw data indices" of the "analyzed.hdf5" file. Using the index found in the "analyzed.hdf5", one can obtain the raw frequency sweep data and metadata. The file "srim-VACANCY.txt" is the vacancy output file of the SRIM simulation discussed in the main manuscript.

This study explores defect engineering in 2D materials using ion beam irradiation to modify the electrical and optical properties with potential in advancing quantum electronics and photonics. Helium and neon ions ranging from 5 to 7.5 keV are employed to manipulate charge transport in monolayer molybdenum disulfide (MoS2). In situ electrical characterization occurs without vacuum breakage post-irradiation. Raman and photoluminescence spectroscopy quantify ion irradiation’s impact on MoS2. Small doses of helium ion irradiation enhance monolayer MoS2 conductivity in field-effect transistor geometry by inducing doping and substrate charging. Findings reveal a strong correlation between the electrical properties of MoS2 and the primary ion used, as well as the substrate on which the irradiation occurred. Using hexagonal boron nitride (h-BN) as a buffer layer between MoS2 flake and SiO2 substrate yields distinct alterations in electrical behavior subsequent to ion irradiation compared to the MoS2 layer directly interfacing with SiO2. Molecular dynamics simulations and density functional theory provide insight into experimental results, emphasizing substrate influence on measured electrical properties post-ion irradiation.

Vertical stacking of different two-dimensional (2D) materials into van der Waals heterostructures exploits the properties of individual materials as well as their interlayer coupling, thereby exhibiting unique electrical and optical properties. Here, we study and investigate a system consisting entirely of different 2D materials for the implementation of electronic devices that are based on quantum mechanical band-to-band tunneling transport such as tunnel diodes and tunnel field-effect transistors. We fabricated and characterized van der Waals heterojunctions based on semiconducting layers of WSe2 and MoS2 by employing different gate configurations to analyze the transport properties of the junction. We found that the device dielectric environment is crucial for achieving tunneling transport across the heterojunction by replacing thick oxide dielectrics with thin layers of hexagonal boronnitride. With the help of additional top gates implemented in different regions of our heterojunction device, it was seen that the tunneling properties as well as the Schottky barriers at the contact interfaces could be tuned efficiently by using layers of graphene as an intermediate contact material.

Germanium (Ge) is a promising candidate for designing near-infrared photodetectors because of its bandgap (0.66 eV), which induces a large absorption coefficient at near-infrared wavelengths. Also, Ge has excellent compatibility of parallel processing with silicon technology [1,2]. Photodetectors based on Ge material have been fabricated with different structures such as metal-semiconductor-metal (MSM) and p−n junctions. On the other hand, the observation of high responsivity in semiconductor nanowires with a high surface-to-volume ratio has attracted growing interest in using nanowires in photodetectors. So far, significant efforts have been made to fabricate single nanowire-based photodetectors with different materials such as Si, Ge, and GaN to achieve miniaturized devices with high responsivity and short response time [3-5]. Hence, Ge nanowires are an excellent candidate to fabricate single nanowire-based near-infrared photodetectors. In this work, we report on the fabrication and characterization of an axial p−n junction along Ge nanowires. First, through a resist mask created by electron beam lithography (EBL), the top Ge layers of germanium-on-insulator (GeOI) substrates were locally doped with phosphorus ions using ion beam implantation followed by rear-side flash lamp annealing. Then, the single Ge nanowire-based photodetectors containing an axial p−n junction were fabricated using EBL and inductively coupled plasma reactive ion etching. The fabricated single Ge nanowire devices demonstrate the rectifying current−voltage characteristic of a p−n diode in dark conditions. Moreover, the photoresponse of the axial p−n junction-based photodetectors was investigated under light illumination with three different wavelengths: 637 nm, 785 nm, and 1550 nm. The measurements indicated that the fabricated photodetectors can be operated at zero bias and room temperature under ambient conditions. A high responsivity of 3.7×102 AW-1 and a detectivity of 1.9×1013 cmHz1/2W-1

Innovative material and processing concepts are needed to further enhance the performance of complementary metal-oxide-semiconductor (CMOS) transistors-based circuits as the scaling limits are being reached. To achieve that, we report on the development of an atomic layer etching (ALE) [1] process to fabricate smooth and thin nanowires using a conventional dry etching tool. Firstly, a negative tone resist (hydrogen silsesquioxane) is spin-coated on SiGe-on-insulator (SiGeOI) samples and electron beam lithography performed to create nano-patterns. These patterns act as an etch mask and are transferred into the SiGeOI layer using an inductively-coupled plasma reactive ion etching (ICP-RIE) process. Subsequently, an SF6 and Ar+ based ALE process is employed to smoothen the nanowires and reduce their widths. SF6 modifies the surface of the samples, while in the next step Ar+ removes the modified surface. The ALE cycle sequence is surface modification with 60 sccm SF6 for 20 s, 60 sccm Ar purge for 15 s, removal of the layer with 60 sccm Ar for 10 s at 25 W platen power, and 40 sccm Ar purge for 10 s. To investigate the effect of ALE on the nanowire roughness and width, several ALE cycles are performed. The surface of the etched features is studied using scanning electron microscopy and atomic force microscopy. With the increasing number of ALE cycles, a reduction in the width of the nanowires, as well as surface roughness, is observed. The roughness reduced from ca. 6 nm to 1 nm (the resolution of the AFM tip) as the number of ALE cycles is increased from 78 to 102. An etch per cycle of 1.1 Å is obtained. Sub-12 nm nanowires with smooth sidewalls were achieved after performing 63 ALE cycles. This process, developed on a conventional ICP-RIE tool, can be used to further down-scale semiconductor nanowires. 1. Kanarik, Keren J., et al. "Overview of atomic layer etching in the semiconductor industry." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 33.

Single photon emitters (SPE) are the starting point and foundation for future photonic quantum technologies. We present the laterally controlled fabrication of single G and W centers in silicon that emit in the telecom O-band. We utilized home built gold-silicon liquid metal alloy ion sources (LMAIS) in a focused ion beam (FIB) system to perform mask-free implantation of 40 keV Si ions from 6 to 500 ions per spot. Analysis and confirmation of SPEs has been done in a home-build cryo-photoluminescence setup. We will demonstrate a success rate of more than 50% and upscaling to wafer-scale. We will also provide an insight and overview on the LMAIS technology and an outlook on other potential applications of FIB implantation.

Downscaling of complementary metal-oxide-semiconductor (CMOS) technology is fraught with difficulties. As a result, novel devices and circuits, sophisticated nanomaterials, and enhanced fabrication processes have become increasingly important in recent decades. Particularly, silicon nanowires have been employed effectively in innovative electronic devices, including sensors, solar cells and in logic circuitry. Due to their high surface to volume ratio, silicon nanowires have been demonstrated as energy efficient devices, which is the key for the next generation of information processing. Field-effect-transistors based on silicon nanowires have been extensively used for sensing applications since the compact nanoscale structures allow excellent regulation of electrostatic potential across the nanowire channel. One such nanowire concept is junctionless nanowire transistor (JNT). A JNT is a highly doped nanowire channel without p-n junctions, where the gate electrode regulates the flow of charge carriers. Silicon JNTs have shown excellent sensi tivity to record-low concentrations of the protein streptavidin in liquid phase. However, they have not yet been operated as gas sensors. In this work, we report the fabrication and characterization of silicon-based JNT devices and their initial tests as gas sensors. Intrinsic silicon-on-insulator (SOI) substrates are ion-implanted with phosphorus (n-type) dopant. Millisecond range flash lamp annealing (FLA) is used for dopant activation and implantation defect healing. Top-down approach is carried out for nanowire fabrication using electron beam lithography patterning of the negative resist HSQ followed by reactive ion etching. Successive processes of rapid thermal oxidation, nitrogen purge step and forming gas annealing are performed to create SiO2 shell around the silicon nanowires. SiO2 thickness is controlled by optimizating the time and temperature in these steps. UV lithography and metal evaporation are employed to create

Silicon nanowires (Si NWs) like structures in the form of nanosheets are the building blocks for future transistors in the most advanced complementary metal–oxide–semiconductor technologies. However, Si NWs with few nanometers in diameter suffer from severe difficulties with respect to efficient impurity doping. These difficulties can be overcome by a novel doping concept for Si NWs comparable to the modulation doping approach known from III–V semiconductors. Modulation doping means that the parent dopant atoms are spatially separated from the volume that is to be doped by embedding them into an adjacent material with a higher bandgap. Herein, Al-doped SiO2 shells around the Si NWs are used for the experimental realization of modulation doping. In two independent experiments, a significant reduction of the electrical resistance of Si NWs by several orders of magnitude is measured, when compared to the resistance of Si NWs with undoped SiO2 shells. The results are discussed in the context of modulation doping by the surface functionalization with SiO2:Al shells.

In recent years, more and more research was conducted to explore smaller and smaller systems that become similar to an actual micro/nano-robot. The major roadblock regarding their real world implementation is the highly restricted available volume. In this paper, we introduce folding – hence an origami technology using Al2O3 as building material, which is compatible with current Si technology. High quality 50 nm thin Al2O3 film is grown by atomic layer desposition, patterned, thinned and then released from the Si subtrate using SF6 plasma etching. The realized free standing Al2O3 structure would fold itself at predefined regions due to the stress in the as deposited films. We believe such technology could offer a new possibility to tackle the problem of efficiently using the volume. Al2O3 could act as both the structural origami material and the functional gate dielectric material for electronics. This approach enables the feasibility of patterning devices and circuits on every Al2O3 facet of a 3D object, while the inside volume of this object is still available for 3D bulk device components. We demonstrate the optimized etching process as well as an emperical improvement of the folding hinges and of the overall structural stability.

Quantum mechanical band-to-band tunneling (BTBT) is a type of carrier injection mechanism that is responsible for the electronic transport in devices like tunnel field effect transistors (TFETs), which hold great promise in reducing the subthreshold swing below the Boltzmann limit. This allows scaling down the operating voltage and the off-state leakage current at the same time, and thus reducing the power consumption of metal oxide semiconductor transistors. Conventional group IV or compound semiconductor materials suffer from interface and bulk traps, which hinders the device performance owing to the increased trap induced parasitics. Alternatives like two-dimensional materials (2DMs) are beneficial for realizing such devices due to their ultra-thin body and atomically sharp interfaces with van der Waals interactions, which significantly reduce the trap density, compared to their bulk counterparts, and hold the promise to finally achieve the desired low voltage operation. In this review, we summarize the recent progress on such devices, with a major focus on heterojunctions made of different 2DMs. We review different types of emerging device concepts, architectures and the tunneling mechanisms involved by analytically studying various simulations and experimental devices. We present our detailed perspective on the current developments, major roadblocks and key strategies for further improvements of the TFET technology based on 2D heterojunctions to match industry requirements. The main goal of this paper is to introduce the reader to the concept of tunneling especially in van der Waals devices and provide an overview of the recent progress and challenges in the field.

Photonic integrated circuits require photodetectors that operate at room temperature with sensitivity at telecom wavelengths and are suitable for integration with planar complementary-metal-oxide-semiconductor (CMOS) technology. Silicon hyperdoped with deep-level impurities is a promising material for silicon infrared detectors because of its strong room-temperature photoresponse in the short-wavelength infrared region caused by the creation of an impurity band within the silicon band gap. In this work, we present the first experimental demonstration of lateral Te-hyperdoped Si PIN photodetectors operating at room temperature in the optical telecom bands. We provide a detailed description of the fabrication process, working principle, and performance of the photodiodes, including their key figure of merits. Our results are promising for the integration of active and passive photonic elements on a single Si chip, leveraging the advantages of planar CMOS technology.

The properties of transition metal dichalcogenides (TMDCs) are highly sensitive to doping and surface-state defects, making it crucial to fabricate high-performance nanoelectronic devices from defect-free materials and gate dielectrics that have a low interface-state density. In this work, the optical and structural properties of mechanically exfoliated mono-, bi- and trilayer thick TMDCs with Al2O3, Si3N4 or SiO2 as a potential gate dielectric layer are investigated. The photoluminescence (PL) and micro-Raman results indicate that all the dielectrics investigated increase the doping of the TMDCs monolayers, quench the emission of neutral excitons and enhance the trion emission. Plasma enhanced chemical vapour deposition was found to generate more defects in the monolayer TMDCs than atomic layer deposition. We establish the relationship between the dielectric deposition process and the optical properties of TMDCs, which could be of interest for future nanoelectronics based on 2D materials.

This work demonstrates the novel concept of a mixed-dimensional reconfigurable field effect transistor (RFET) by combining a one-dimensional (1D) channel material such as a silicon (Si) nanowire with a two-dimensional (2D) material as a gate dielectric. An RFET is an innovative device that can be dynamically programmed to perform as either an n- or p-FET by applying appropriate gate potentials. In this work, an insulating 2D material, hexagonal boron nitride (hBN), is introduced as a gate dielectric and encapsulation layer around the nanowire in place of a thermally grown or atomic-layer-deposited oxide. hBN flake was mechanically exfoliated and transferred onto a silicon nanowire-based RFET device using the dry viscoelastic stamping transfer technique. The thickness of the hBN flakes was investigated by atomic force microscopy and transmission electron microscopy. The ambipolar transfer characteristics of the Si-hBN RFETs with different gating architectures showed a significant improvement in the device’s electrical parameters due to the encapsulation and passivation of the nanowire with the hBN flake. Both n- and p-type characteristics measured through the top gate exhibited a reduction of hysteresis by 10–20 V and an increase in the on–off ratio (ION/IOFF) by 1 order of magnitude (up to 108) compared to the values measured for unpassivated nanowire. Specifically, the hBN encapsulation provided improved electrostatic top gate coupling, which is reflected in the enhanced subthreshold swing values of the devices. For a single nanowire, an improvement up to 0.97 and 0.5 V/dec in the n- and p-conduction, respectively, is observed. Due to their dynamic switching and polarity control, RFETs boast great potential in reducing the device count, lowering power consumption, and playing a crucial role in advanced electronic circuitry. The concept of mixed-dimensional RFET could further strengthen its functionality, opening up new pathways for future electronics.

We investigate the lane formation in nonequilibrium systems of colloidal particles moving in parallel that are driven by the force of gravity. For this setup, an experimental implementation of a channel on a slope can be conceptualized. We employ the Brownian dynamics algorithm and confine the repulsive particles with hard walls based on the solution of the Smoluchowski equation in the half space. A difference of the driving force acting on the colloids could be achieved by using two spherical particle types with differing diameters but equal mass density. Firstly, we investigate how a difference in the channel slope affects the lane formation of the systems, after which we analyze the lanes that formed. We found that the large particles push the small particles to the walls, resulting in exclusively small particle lanes at the walls. This contrasts the equilibrium state, where depletion forces push the larger particles to the walls. Additionally, we have a closer look at the mechanisms by which the lanes form. Finally, we found system parameter values that foster lane formation to lay the foundation for an experimental realization of our proposed setup. To round this off, we give an exemplary calculation of the slope angle needed to get the experimental system into a state of lane order. With the examination of lane order in systems that are driven in parallel, we hope to deepen our understanding of nonequilibrium order phenomena.

The self-assembly of conducting nanostructures is currently investigated intensively in order to evaluate the feasibility of creating novel nanoelectronic devices and circuits using such pathways. In particular, methods based on so-called DNA Origami nanostructures have shown great potential in the formation of metallic nanowires. The main challenge in this method is the reproducible generation of very well-connected metallic nanostructures which may be used as interconntects in future devices. Here we use a novel design of nanowires with a quasi-circular cross-section as opposed to rectangular or uncontrolled cross-sections in earlier studies. We find indications that the reliability of the fabrication scheme is enhanced and the overall resistance of the wires is comparable to metallic nanostructures generated by electrochemistry or top-down methods. In addition, we observe that some of the nanowires are annealed when passing a current through them, which leads to a clear enhancement for the conductance. We envision that these nanowires are providing further steps towards the succesful generation of nanoelectronics using self-assembly.

Structural insight into nano-objects down to the atomic scale is one of the most important prerequisites in understanding functional materials properties and will ultimately permit to relate the size and shape of nanoparticles to their catalytic activity. We elucidate the potential of extracting structural information about a small ensemble of nanoparticles semi-regularly arranged on a periodic array from coherent X-ray Bragg diffraction. The observed superstructure in the Pt(111) Bragg peak obviously originates from the mutual interference of the Bragg scattered wave field from individual nanoparticles in the nano-array. Despite the absence of a symmetry center in the Bragg peak of the nano-array, we identify the most prominent in-plane spatial frequencies of the latter by applying a Patterson map analysis to the Bragg peak superstructure. Integration along the out-of-plane reciprocal space direction over the relevant in-plane regions of interest results in Laue oscillations that arise from nanoparticle sets of similar heights in real space. A one-to-one comparison with real-space microscopic information obtained from SEM and AFM suggests potential nanoparticle subsets as origin for the X-ray intensity in these regions of interest by the good agreement in their height and direction-dependent in-plane interparticle distances, as also further supported by simulations. Nanoparticle arrays with well-defined tunable sizes and lateral distances may serve in the future to track structural changes of smallest catalysis-relevant nanoparticles during operando heterogeneous catalysis experiments in the 10 nm size regime.

In this work, we demonstrate the usability of a fully-2D-material based device consisting of MoS2/WSe2 heterojunction encapsu-lated by hBN and contacted by graphene as temperature sensor for linear temperature measurement at cryogenic temperatures. More precisely, temperatures in the range of 10 K up to 300 K were applied to the device while recording the I-V characteris-tics. From this, we had a deeper look on the current transport mechanism by obtaining the activation energy of the saturation current in the Arrhenius diagram. It is 1.3 eV, which can be related to the bandgap of MoS2 or WSe2 (both nominal 1.3 eV) as for traditional pn-junction diodes in bulk materials. Further-more, we applied a constant forward current to the device while measuring the voltage drop at different temperatures to investi-gate the temperature-sensor performance. In the range of 40 K up to 300 K, the sensitivity of the sensor is ~2 mV/K, which is comparable to Si devices, while the linearity is still lower (R2 ~ 0.94). On the other hand, the demonstrated device consists only of 2D materials and is, thus, substrate independent, ultra-thin, and can be fabricated on a fully flexible substrate in a low-cost process.

Innovative material and processing concepts are needed to further enhance the performance of complementary metal-oxide-semiconductor (CMOS) transistors-based circuits as the scaling limits are being reached. To achieve that, we report on the development of an atomic layer etching (ALE) [1] process to fabricate smooth and thin nanowires using a conventional dry etching tool. Firstly, a negative tone resist (hydrogen silsesquioxane) is spin-coated on SiGe-on-insulator (SiGeOI) samples and electron beam lithography performed to create nano-patterns. These patterns act as an etch mask and are transferred into the SiGeOI layer using an inductively-coupled plasma reactive ion etching (ICP-RIE) process. Subsequently, an SF6 and Ar+ based ALE process is employed to smoothen the nanowires and reduce their widths. SF6 modifies the surface of the samples, while in the next step Ar+ removes the modified surface. The ALE cycle sequence is surface modification with 60 sccm SF6 for 20 s, 60 sccm Ar purge for 15 s, removal of the layer with 60 sccm Ar for 10 s at 25 W platen power, and 40 sccm Ar purge for 10 s. To investigate the effect of ALE on the nanowire roughness and width, several ALE cycles are performed. The surface of the etched features is studied using scanning electron microscopy and atomic force microscopy. With the increasing number of ALE cycles, a reduction in the width of the nanowires, as well as surface roughness, is observed. The roughness reduced from ca. 6 nm to 1 nm (the resolution of the AFM tip) as the number of ALE cycles is increased from 78 to 102. An etch per cycle of 1.1 Å is obtained. Sub-12 nm nanowires with smooth sidewalls were achieved after performing 63 ALE cycles. This process, developed on a conventional ICP-RIE tool, can be used to further down-scale semiconductor nanowires. 1. Kanarik, Keren J., et al. "Overview of atomic layer etching in the semiconductor industry." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 33.

A review of single photon emitters in silicon based on ion-induced defects is provided. Fabrication methods and current state of the art are discussed.

Single-photon emitters (SPEs) are one of the elementary building blocks for photonic quantum information and optical quantum computing. One of the upcoming challenges is the monolithic photonic integration and coupling of single-photon emission, reconfigurable photonic elements, and single-photon detection on a silicon chip in a controllable manner. Particularly, fully integrated SPEs on-demand are required for enabling a smart integration of advanced functionalities in on-chip quantum photonic circuits. The major challenge in realizing a fully monolithic, photonic integrated circuitry lies in the development of a quantum light source in silicon since the indirect nature of the small energy bandgap does not allow for efficient PL emission. Nevertheless, below-bandgap light emission can be used for good advantage by exploiting extrinsic and intrinsic point defects acting as SPEs. Indeed, the isolation of SPEs, such as G-, W-, and T-centers, in the optical telecommunication O-band has been recently realized in silicon.. In all these cases, however, SPEs were created uncontrollably in random locations, preventing their scalability. We present mask-free nanofabrication involving a quasi-deterministic creation of single G- and W-centers in silicon wafers using focused-ion beam (FIB) writing. We also implement a scalable, broad-beam implantation protocol compatible with the complementary-metal-oxide-semiconductor (CMOS) technology to fabricate telecom SPEs at desired positions on the nanoscale.

Single-photon emitters (SPEs) are one of the elementary building blocks for photonic quantum information and optical quantum computing. One of the upcoming challenges is the monolithic photonic integration and coupling of single-photon emission, reconfigurable photonic elements, and single-photon detection on a sili- con chip in a controllable manner. Particularly, fully integrated SPEs on-demand are required for enabling a smart integration of advanced functionalities in on-chip quantum photonic circuits. The major challenge in realizing a fully monolithic, photonic integrated circuitry lies in the development of a quantum light source in silicon since the indirect nature of the small energy bandgap does not allow for efficient PL emission. Nev- ertheless, below-bandgap light emission can be used for good advantage by exploiting extrinsic and intrinsic point defects acting as SPEs. Indeed, the isolation of SPEs, such as G-, W-, and T-centers, in the optical telecom- munication O-band has been recently realized in silicon [1-4]. In all these cases, however, SPEs were created uncontrollably in random locations, preventing their scalability. We present mask-free nanofabrication involving a quasi-deterministic creation of single G- and W-centers in silicon wafers using focused-ion beam (FIB) writing. We also implement a scalable, broad-beam implan- tation protocol compatible with the complementary-metal-oxide-semiconductor (CMOS) technology to fabri- cate telecom SPEs at desired positions on the nanoscale [5]. [1] M. Hollenbach et al., Optics Express 28, 26111 (2020) [2] W. Redjem et al., Nature Electronics 3, 738 (2020) [3] Y. Baron et al., ACS Photonics 9, 2337 (2022) [4] D. B. Higginbottom et al., Nature 607, 266 (2022) [5] M. Hollenbach et al., Nat. Commun. 13, 7683 (2022)

Germanium (Ge) is a promising candidate for designing near-infrared photodetectors because of its bandgap (0.66 eV), which induces a large absorption coefficient at near-infrared wavelengths. Also, Ge has excellent compatibility of parallel processing with silicon technology [1,2]. Photodetectors based on Ge material have been fabricated with different structures such as metal-semiconductor-metal (MSM) and p−n junctions. On the other hand, the observation of high responsivity in semiconductor nanowires with a high surface-to-volume ratio has attracted growing interest in using nanowires in photodetectors. So far, significant efforts have been made to fabricate single nanowire-based photodetectors with different materials such as Si, Ge, and GaN to achieve miniaturized devices with high responsivity and short response time [3-5]. Hence, Ge nanowires are an excellent candidate to fabricate single nanowire-based near-infrared photodetectors. In this work, we report on the fabrication and characterization of an axial p−n junction along Ge nanowires. First, through a resist mask created by electron beam lithography (EBL), the top Ge layers of germanium-on-insulator (GeOI) substrates were locally doped with phosphorus ions using ion beam implantation followed by rear-side flash lamp annealing. Then, the single Ge nanowire-based photodetectors containing an axial p−n junction were fabricated using EBL and inductively coupled plasma reactive ion etching. The fabricated single Ge nanowire devices demonstrate the rectifying current−voltage characteristic of a p−n diode in dark conditions. Moreover, the photoresponse of the axial p−n junction-based photodetectors was investigated under light illumination with three different wavelengths: 637 nm, 785 nm, and 1550 nm. The measurements indicated that the fabricated photodetectors can be operated at zero bias and room temperature under ambient conditions. A high responsivity of 3.7×102 AW-1 and a detectivity of 1.9×1013 cmHz1/2W-1

streak camera data, meta data

IV-measurements of nanowires discussed in the paper&nbsp

Single photon emitters (SPE) are fundamental building blocks for future quantum technology applications. However, many ap- proach lack the required spatial placement accuracy and Si tech- nology compatibility required for many of the envisioned applica- tions. Here, we present a method to fabricate at will placed single or few SPEs emitting in the telecom O-band in Silicon [1] . The successful integration of these telecom quantum emitters into photonic structures such as micro-resonators, nanopillars and photonic crystals with sub-micrometer precision paves the way to- ward a monolithic, all-silicon-based semiconductor-supercon- ductor quantum circuit for which this work lays the foundations. To achieve our goal we employ home built AuSi liquid metal alloy ion sources (LMAIS) and an Orsay Physics CANION M31Z+ focused ion beam (FIB). Silicon-on-insulator substrates from different fabri- cation methods have been irradiated with a spot pattern. 6 to 500 Si2+ ions have been implanted per spot using an energy of 40 keV. For the analysis and confirmation of the fabrication of true SPEs a home build photo luminescence setup has been used. G-centers formed by the combination of two carbon atoms and a silicon atom are confirmed by measurements of zero phonon lines (ZPL) at the expected wave length of 1278 nm for the case of carbon rich SOI wafers. In the case of ultra clean SOI wafers and high ion fluxes emission from tri-interstitial Si complexes is observed. The SPE nature of these so called W-centers has also been confirmed by ZPL measurements at 1218 nm. The achieved lateral SPE placement accuracy is below 100 nm in both cases and the success rate of SPE formation is more than 50%. After a discus- sion of the formation statistic we also present an approach how our FIB based approach can be upscaled to wafer-scale nanofabrication of telecom SPEs compatible with complementary metal oxide semiconductor (CMOS) technology for very large scale integration (VLSI).

Germanium (Ge) is considered as a promising candidate for designing near-infrared photodetectors. Ge has a bandgap of 0.67 eV, which induces a large absorption coefficient at near-infrared frequencies. Also, Ge has excellent compatibility of parallel processing with silicon technology [1,2]. Photodetectors based on Ge material have been fabricated with different structures such as metal-semiconductor-metal (MSM) and p−n junctions. On the other hand, the observation of high photoresponsivity in semiconductor nanowires with a high surface-to-volume ratio has attracted growing interest in using nanowires in photodetectors. So far, significant efforts have been made to fabricate single nanowire based photodetectors with different materials such as Si, Ge, and GaN to achieve miniaturized devices with high responsivity and short response time [3-5]. Hence, Ge nanowires are an excellent candidate to fabricated single nanowire based near-infrared photodetectors. In this work, we report on the fabrication and characterization of an axial p−n junction along Ge nanowires with different widths. First, through a resist mask created by electron beam lithography (EBL), the Ge layers were locally doped with phosphorus ions using ion beam implantation followed by rear-side flash lamp annealing. Then, the single Ge nanowire based photodetectors containing an axial p−n junction were fabricated using EBL and inductively coupled plasma reactive ion etching (ICP-RIE). The fabricated single Ge nanowire devices demonstrate the rectifying current-voltage characteristic of a p−n diode in dark conditions. Moreover, the photoresponse of the axial p−n junction based photodetectors was investigated under three different illumination lights of 637 nm, 785 nm, and 1550 nm wavelengths. It appears that fabricated photodetectors can be operated at zero bias and at room temperature under ambient conditions. A high responsivity of 3.7×102 AW-1, and detectivity of 1.9×1013 cmHz1/2W-1 were observed at ze

Down-scaling of complementary metal-oxide-semiconductor (CMOS) technology faces strong challenges. Therefore, new device and logic concepts, advanced nanomaterials, and advanced fabrication techniques have gained importance in the last few decades. Nanomaterials and nanostructures hold the key for next-generation information processing due to their reduced sizes and new properties [1]. Silicon nanowires, in particular, have been used successfully in new electronic devices, including thermoelectric energy harvesting, sensors, and solar cells. Silicon nanowires, due to their high surface-to-volume ratio, have demonstrated energy efficient devices. In the case of nanowire based field-effect transistors (FETs), excellent control of conductance across the nanowire is achieved through the electrostatic potential applied at the gate [2]. Moreover, nanowires have been used for fabrication of high sensitivity biochemical sensors, since small volumes allow effective control of the electrostatic potential across a nanowire. Such sensors have been used for various applications, including diagnosing cancer biomarkers and viruses [3], sensing gases such as ammonia (NH3), nitrogen dioxide (NO2) [4], and hydrogen (H2) [5]. One of the new, nanowire based, device concepts mentioned above is the junctionless nanowire transistor (JNT) [6]. A JNT consists of a highly doped nanowire channel without p-n junctions, where the flow of carriers is controlled by the gate potential. JNTs have already shown excellent performance as biosensors [7]. In this work, we report on the fabrication of such transistors for the detection of atmospheric free radicals. Intrinsic silicon-on-insulator (SOI) wafers are n-doped by ion implantation. Flash lamp annealing is performed for dopant activation and mitigation of implantation defects. Nanowires are fabricated following a top-down approach using electron beam lithography and reactive ion etching. Then, Nickel/Gold contacts are fabricated. Electrical chara

Free carriers in doped semiconductors absorb terahertz radiation when the frequency of the electromagnetic field is lower or comparable to the plasma frequency of the system. This phenomenon can be used to manipulate the optical response of the material. We present here the results of two different experiments performed at the infrared free-electron laser FELBE on atomically-thin van der Waals semiconductors. In MoSe2 monolayers, we observe a terahertz-induced redshift of the trion resonance. Terahertz absorption induces an average high momentum to the carriers and this momentum gets transferred during the trion formation, resulting in a net redshift in the absorption. In few-layer InSe, the terahertz pulses induce a transient quenching of the photoluminescence emission. In both cases, a microscopic study of the hot carrier distribution cooling is also presented.

The physical downscaling of CMOS technology has reached its limitations. Subsequently, the quest for alternative technological solutions based on new materials and device concepts augment the downscaling of integrated circuits. One such concept is the reconfigurable FET (RFET), which can be dynamically programmed to n- or p-polarity by applying an electrostatic potential [1]. In this work, we present the idea of a novel mixed dimensional RFET device, which explores the potential of both one-dimensional (1D) channel materials (like silicon (Si) or silicon-germanium (SiGe) based nanowires) and two-dimensional (2D) materials. In the most generic process, an RFET device is based on intrinsic Si or SiGe nanowire with Nickel (Ni) placed on both ends. Subsequent annealing results in the formation of silicide regions in the nanowire. The junction of the silicide to Si or SiGe is a typical Schottky junction. By controlling the Schottky junction with the help of gating architectures, the flow of charge carriers within the channel can be modulated. For ambipolarity, an electrostatic potential on the back-gate or a single top-gate enables the n- or p-transport depending on the polarity of the gate voltage. The main aim of this work is to optimize the RFET architecture based on 2D materials like hexagonal boron nitride (hBN) as a dielectric and encapsulating layer instead of thermally grown oxide around the nanowire. 2D hBN comprises a structure very similar to graphene with its sub lattice consisting of boron or nitrogen atoms. However, contrary to graphene, hBN acts as an insulator with dielectric constant between 3-4 (similar to SiO2). The properties of atomically thin hBN like the absence of dangling bonds, resistance to oxidation and chemical stability makes it an ideal gate dielectric material for flexible electronics. Top-down fabrication of RFETs is an essential requirement for large-scale device integration. The Si or SiGe nanowires are fabricated using electron beam li

Single photon emitters (SPE) are fundamental building blocks for future quantum technology applications. However, many ap- proach lack the required spatial placement accuracy and Si tech- nology compatibility required for many of the envisioned applica- tions. Here, we present a method to fabricate at will placed single or few SPEs emitting in the telecom O-band in Silicon [1] . The successful integration of these telecom quantum emitters into photonic structures such as micro-resonators, nanopillars and photonic crystals with sub-micrometer precision paves the way to- ward a monolithic, all-silicon-based semiconductor-supercon- ductor quantum circuit for which this work lays the foundations. To achieve our goal we employ home built AuSi liquid metal alloy ion sources (LMAIS) and an Orsay Physics CANION M31Z+ focused ion beam (FIB). Silicon-on-insulator substrates from different fabri- cation methods have been irradiated with a spot pattern. 6 to 500 Si2+ ions have been implanted per spot using an energy of 40 keV. For the analysis and confirmation of the fabrication of true SPEs a home build photo luminescence setup has been used. G-centers formed by the combination of two carbon atoms and a silicon atom are confirmed by measurements of zero phonon lines (ZPL) at the expected wave length of 1278 nm for the case of carbon rich SOI wafers. In the case of ultra clean SOI wafers and high ion fluxes emission from tri-interstitial Si complexes is observed. The SPE nature of these so called W-centers has also been confirmed by ZPL measurements at 1218 nm. The achieved lateral SPE placement accuracy is below 100 nm in both cases and the success rate of SPE formation is more than 50%. After a discus- sion of the formation statistic we also present an approach how our FIB based approach can be upscaled to wafer-scale nanofabrication of telecom SPEs compatible with complementary metal oxide semiconductor (CMOS) technology for very large scale integration (VLSI).

Silicon junctionless nanowire transistors (JNTs) have shown excellent sensitivity to record-low concentrations of the protein streptavidin in liquid phase. However, JNTs have not yet been tested for sensing in gas phase. Here we present the fabrication and initial electrical characterisation of JNT-based electronic sensors for detection of atmospheric free radicals such as hydroxyl (•OH) and nitrate (•NO3), which are the main drivers of chemical processes in the atmosphere. The aim of this work is to develop small, low-cost JNT-based nanosensors for radical detection. Silicon-on-insulator wafers were doped by ion implantation and flash-lamp annealing. Device patterning was based on electron beam lithography, inductively-coupled reactive ion etching, metal deposition and lift-off. Initial electrical characterisation and gas sensing experiments on fabricated devices proved their good performance and potential suitability for detection of atmospheric free radicals

The electrical properties of single molecules can be investigated using atomically sharp metallic electrodes in mechanically controllable break junctions (MCBJs). The current-voltage (IV) characteristics of single molecules in such junctions are affected by the binding positions of the end groups on the tip-facets and tip-tip separation. In this poster, we present MCBJ experiments on N,N’-Bis(5-ethynylbenzenethiol-salicylidene)ethylenediamine (Salen). We discuss the evolution of the single level model (SLM) parameters namely, a) the energetic level (epsilon) of the dominant conducting channel and b) the coupling (Gamma) of the dominant conducting channel to the metallic electrodes. The SLM-parameters were evaluated for IV-curves recorded during opening measurements and fitted to the single level model. We explain the recurring peak-like features/protusions in the experimentally measured evolution of Gamma with increasing tip-tip separation, which we relate not only to the deformation of the molecule but also to the sliding of the anchor group above the electrode surface. We propose a novel, high-throughput approach to model the evolution of the SLM-parameters and perform transport calculations using the self-consistent charge scheme of the density-functional-based tight binding (SCC-DFTB) approach and the Green’s function formalism. Thereby, we consider many thermodynamically relevant configurations and assess the evolution of SLM-parameters using the SLM-curve fitting of the zero-bias transmission. The SLM-parameters are averaged using statistical weights obtained from a Metropolis simulation considering up to 200 000 configurations for selected tip-tip separations. The behavior of the averaged quantities with respect to the tip-tip separation reflects the experimentally observed evolution of the SLM-parameters astonishingly well.

Innovative material and processing concepts are needed to further enhance the performance of complementary metal-oxide-semiconductor (CMOS) transistors-based circuits as the scaling limits are being reached. To achieve that, we report on the development of an atomic layer etching (ALE) [1] process to fabricate smooth and thin nanowires using a conventional dry etching tool. Firstly, a negative tone resist (hydrogen silsesquioxane) is spin-coated on SiGe-on-insulator (SiGeOI) samples and electron beam lithography performed to create nano-patterns. These patterns act as an etch mask and are transferred into the SiGeOI layer using an inductively-coupled plasma reactive ion etching (ICP-RIE) process. Subsequently, an SF6 and Ar+ based ALE process is employed to smoothen the nanowires and reduce their widths. SF6 modifies the surface of the samples, while in the next step Ar+ removes the modified surface. The ALE cycle sequence is surface modification with 60 sccm SF6 for 20 s, 60 sccm Ar purge for 15 s, removal of the layer with 60 sccm Ar for 10 s at 25 W platen power, and 40 sccm Ar purge for 10 s. To investigate the effect of ALE on the nanowire roughness and width, several ALE cycles are performed. The surface of the etched features is studied using scanning electron microscopy and atomic force microscopy. With the increasing number of ALE cycles, a reduction in the width of the nanowires, as well as surface roughness, is observed. The roughness reduced from ca. 6 nm to 1 nm (the resolution of the AFM tip) as the number of ALE cycles is increased from 78 to 102. An etch per cycle of 1.1 Å is obtained. Sub-12 nm nanowires with smooth sidewalls were achieved after performing 63 ALE cycles. This process, developed on a conventional ICP-RIE tool, can be used to further down-scale semiconductor nanowires. 1. Kanarik, Keren J., et al. "Overview of atomic layer etching in the semiconductor industry." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 33.

Heterojunctions made of two-dimensional (2D) semiconducting materials provide promising properties for the realization of tunnel field effect transistors (TFETs). The absence of dangling bonds allows the formation of sharp hetero-interfaces, which enables the reduction of parasitic components arising due to interface traps. In this work, we demonstrate band-to-band tunneling (BTBT) between layers of WSe2 and MoS2 that are contacted with few-layered graphene (FLG) on both sides of the junction and completely encapsulated with hexagonal boron nitride (h-BN). Additionally, we also use the FLG as a gate electrode, which allows us to realize devices made entirely of different 2D materials. We observe negative differential resistance (NDR) confirming the tunneling transport in our devices showing the potential in terms of further optimization.

Single-photon sources are one of the elementary building blocks for photonic quantum information and optical quantum computing [1]. One of the upcoming challenges is the monolithic photonic integration and coupling of single-photon emission, reconfigurable photonic elements and single-photon detection on a silicon chip in a controllable manner. Particularly, fully integrated single-photon emitters on-demand are required for enabling a smart integration of advanced functionalities in on-chip quantum photonic circuits [2]. This work presents a mask-free nanofabrication method involving a quasi-deterministic creation of scalable extrinsic color centers in silicon emitting in the optical telecom O-band [3] on a commercial silicon-on-insulator platform using focused ion beam writing. We also show the local writing of an intrinsic color center in silicon, which is linked to a tri-interstitial complex and reveals quantum emission close to the telecom band [4]. The successful integration of these telecom quantum emitters into photonic structures such as micro-resonators, nanopillars [5] and photonic crystals with sub-micrometer precision paves the way toward a monolithic, all-silicon-based semiconductor-superconductor quantum circuit. [1]D. D. Awschalom et al.,Nature Photonics 12,516 (2018) [2]J. C. Adcock et al.,IEEE, 27, 2, (2021) [3]M. Hollenbach et al.,Optics Express 28,26111 (2020) [4]Y. Baron et al.,arXiv:2108.04283 (2021) [5]M. Hollenbach et al.,arXiv:2112.02680 (2021)

Single photon emitters (SPE) are fundamental building blocks for future quantum technology applications. However, many ap- proach lack the required spatial placement accuracy and Si tech- nology compatibility required for many of the envisioned applica- tions. Here, we present a method to fabricate at will placed single or few SPEs emitting in the telecom O-band in Silicon [1] . The successful integration of these telecom quantum emitters into photonic structures such as micro-resonators, nanopillars and photonic crystals with sub-micrometer precision paves the way to- ward a monolithic, all-silicon-based semiconductor-supercon- ductor quantum circuit for which this work lays the foundations. To achieve our goal we employ home built AuSi liquid metal alloy ion sources (LMAIS) and an Orsay Physics CANION M31Z+ focused ion beam (FIB). Silicon-on-insulator substrates from different fabri- cation methods have been irradiated with a spot pattern. 6 to 500 Si2+ ions have been implanted per spot using an energy of 40 keV. For the analysis and confirmation of the fabrication of true SPEs a home build photo luminescence setup has been used. G-centers formed by the combination of two carbon atoms and a silicon atom are confirmed by measurements of zero phonon lines (ZPL) at the expected wave length of 1278 nm for the case of carbon rich SOI wafers. In the case of ultra clean SOI wafers and high ion fluxes emission from tri-interstitial Si complexes is observed. The SPE nature of these so called W-centers has also been confirmed by ZPL measurements at 1218 nm. The achieved lateral SPE placement accuracy is below 100 nm in both cases and the success rate of SPE formation is more than 50%. After a discus- sion of the formation statistic we also present an approach how our FIB based approach can be upscaled to wafer-scale nanofabrication of telecom SPEs compatible with complementary metal oxide semiconductor (CMOS) technology for very large scale integration (VLSI).