Search

Stacked mosfet structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked mosfet driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-μm process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 μA under no-load conditions. [ABSTRACT FROM AUTHOR]

An area-efficient pulsewidth modulation (PWM)-residual-aliasing reduction technique is proposed for Class-D audio amplifiers by utilizing a low-complexity feed-forward path to cancel the PWM high-frequency components inside the feedback loop. The proposed technique reduces the PWM-residual-aliasing distortion without increasing the required switching frequency or power-hungry controller circuits, thereby lowering both the quiescent current and total harmonic distortion plus noise (THD+N) in Class-D audio amplifiers. Measurement results show that the proposed technique improves the THD+N of second-order Class-D amplifiers by 16.2 dB with a 1-kHz input; in addition, the Class-D amplifier of this paper achieves a minimum THD+N of 0.0032% while operating at a 215-kHz switching frequency, resulting in a reduction in quiescent current of more than 33%. Compared with other state of the arts, this paper implemented in 0.5- $\mu \text{m}$ CMOS technology features a competitive THD+N while consuming the lowest quiescent current of 0.96 mA and occupying the smallest active area of 0.49 mm2. [ABSTRACT FROM AUTHOR]

A non-local delayed reaction-diffusion model with a quiescent stage is investigated. It is shown that the spreading speed of this model withoutquasi-monotonicity is linearly determinate and coincides with the minimal wavespeed of traveling waves. [ABSTRACT FROM AUTHOR]

This paper presents a chip-scale ultralow quiescent current power management system that interfaces with electromechanical energy harvester for enabling self-powering, batteryless wireless sensors. A piezoelectric transducer scavenges and transforms mechanical vibration energy into electricity in ac form, which is then converted into dc power by a full bridge rectifier and collected into a small filter capacitor. A buck–boost converter, as an impedance matching converter to achieve maximum power point tracking, further transfers the energy into a supercapacitor, from which a low-dropout (LDO) regulator powers an on-chip CMOS sensor with clean power supply. Additionally, the energy stored in the supercapacitor can be used to drive a radio frequency transmitter. These components form a complete wireless sensor node, applicable for the Internet of Things sensor networks. The chip is fabricated by using a standard 0.5 μm CMOS process. From measurements we have verified all the key merits of this design: first, a high voltage converting efficiency (up to 97.1%) of the rectifier; second, a minimum of 102 s charging time to charge a 1 mF supercapacitor from 0 to 3.3 V of the buck–boost converter with impedance matching method; and third, a 10 nA to 100 μA load current range and at least 85° phase margin LDO regulator with ultralow quiescent bias current as low as 750 pA. [ABSTRACT FROM AUTHOR]

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide  (CMOS) circuits based on the quiescent current supply  (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design. [ABSTRACT FROM AUTHOR]

Abstract Forty sediment cores collected on the Chukchi shelf and adjacent portions of the East Siberian Sea have been assayed for the sedimentation tracer 137Cs and 34 were also assayed for 210Pb. While both sedimentation and bioturbation influence how these tracers are distributed vertically in sediment cores, only about half of the cores had distinct, single mid-depth or subsurface maximum activity peaks associated with 137Cs originating from bomb fallout. For the same reasons, only 14 of the 34 cores assayed showed a consistent decline in excess sedimentary 210Pb with depth in the core. Furthermore, sedimentation rate estimates from 210Pb assays were only consistent with estimated 137Cs sedimentation rates in 4 of the 14 cores from north of Bering Strait. A high degree of bioturbation on the shelf is primarily responsible for these patterns, but the influence of sedimentation on vertical profiles is also important, particularly in areas of low accumulation where shallow burial of maximum burdens of 137Cs in high current areas such as Herald Canyon can be observed. Shallow burial of radiocesium is also observed in comparatively low sedimentation areas such as Hanna Shoal, on the northeast Chukchi Shelf. By contrast, elsewhere on the northeast Chukchi Shelf and in productive benthic "hotspots," the stronger influence of bioturbation leads to radiocesium that is more evenly distributed vertically within sediments, i.e., no distinct mid- or subsurface depth maximum activity associated with bomb fallout. These sediment profiles of radiocesium reflect several other sediment characteristics that are affected by current flow. These sediment characteristics in turn impact biological activity, including grain size, carbon to nitrogen ratios of the organic fraction of surface sediments and total organic carbon content. The distribution patterns of the radionuclides, particularly the depth where 137Cs reaches maximum activity, reflects sedimentation under both quiescent and strong currents. The activity of 137Cs at that depth of maximum activity provide insights on how much the vertical distribution of the radionuclide has been impacted by bioturbation, as well as the characteristics of the sediments that play a role in influencing deposition and total inventories of radiocesium on continental shelves. [ABSTRACT FROM AUTHOR]

Free vibration of layered circular cylindrical shell filled with fluid with an anti-symmetric angle-ply walls including first-order shear deformation theory is presented. The fluid is assumed to be quiescent and inviscid. The permeability condition on the fluid-shell interface is applied to ensure the contact between the fluid and shell wall. The governing equations are obtained in terms of displacement and rotational functions. These functions are assumed in a separable form, resulting into a system of ordinary differential equation. Bickley-type spline of order three is applied to the problem, along with the equations of boundary conditions, bringing out into the system of homogeneous equations and become as a generalized eigenvalue problem. This problem is solved for frequency parameter with an associated eigenvectors. The effect of shell geometry, types of material, ply-orientations, number of layers and boundary conditions on frequencies are studied. [ABSTRACT FROM AUTHOR]

Background: Skeletal muscle satellite (stem) cells are quiescent in adult mice and can undergo multiple rounds of proliferation and self-renewal following muscle injury. Several labs have profiled transcripts of myogenic cells during the developmental and adult myogenesis with the aim of identifying quiescent markers. Here, we focused on the quiescent cell state and generated new transcriptome profiles that include subfractionations of adult satellite cell populations, and an artificially induced prenatal quiescent state, to identify core signatures for quiescent and proliferating. Methods: Comparison of available data offered challenges related to the inherent diversity of datasets and biological conditions. We developed a standardized workflow to homogenize the normalization, filtering, and quality control steps for the analysis of gene expression profiles allowing the identification up- and down-regulated genes and the subsequent gene set enrichment analysis. To share the analytical pipeline of this work, we developed Sherpa, an interactive Shiny server that allows multi-scale comparisons for extraction of desired gene sets from the analyzed datasets. This tool is adaptable to cell populations in other contexts and tissues. Results: A multi-scale analysis comprising eight datasets of quiescent satellite cells had 207 and 542 genes commonly up- and down-regulated, respectively. Shared up-regulated gene sets include an over-representation of the TNFα pathway via NFKβ signaling, Il6-Jak-Stat3 signaling, and the apical surface processes, while shared down-regulated gene sets exhibited an over-representation of Myc and E2F targets and genes associated to the G2M checkpoint and oxidative phosphorylation. However, virtually all datasets contained genes that are associated with activation or cell cycle entry, such as the immediate early stress response genes Fos and Jun. An empirical examination of fixed and isolated satellite cells showed that these and other genes were absent in vivo, but activated during procedural isolation of cells. Conclusions: Through the systematic comparison and individual analysis of diverse transcriptomic profiles, we identified genes that were consistently differentially expressed among the different datasets and shared underlying biological processes key to the quiescent cell state. Our findings provide impetus to define and distinguish transcripts associated with true in vivo quiescence from those that are first responding genes due to disruption of the stem cell niche. [ABSTRACT FROM AUTHOR]

A buck converter in 65-nm CMOS is optimized for a low quiescent power of 240 pW. It operates with input 1.2–3.3 V and regulates the output from 0.7–0.9 V. Control circuits are designed for low leakage and static current, and scale in power over a hertz to megahertz frequency range, resulting in a wide load current dynamic range of 2\times 10^6 . With a 2-V input, the converter has a peak efficiency of 89% and delivers load currents of 500 pA to 1 mA with efficiency better than 50%. The peak efficiency is 92% for a 1.2-V input. [ABSTRACT FROM AUTHOR]

Purpose: This study evaluates long-term visual acuity (VA) outcomes in patients with prolonged clinically quiescent neovascular age-related macular degeneration (AMD) after treatment with a pro re nata (PRN) regimen of anti-vascular endothelial growth factor agents (bevacizumab, ranibizumab, and/or aflibercept).Methods: This retrospective study analyzes VA changes in 105 eyes from 72 patients with a period of AMD disease quiescence (determined by retinal examination) not requiring treatment for at least 180 days. All patients were seen at Colorado Retina Associates between October 31, 2005 and December 31, 2015. VA was measured at the time of first treatment, last treatment, and final clinic visit showing changes in VA during the treatment and quiescent periods. The sample was stratified to compare those with VA gain throughout the study to those with VA loss.Results: The aggregate group showed VA stability during the treatment period (20/117 to 20/116) with a significant decline during the quiescent period (to 20/235; P < 0.001). The VA gainers had a significant increase in VA during the treatment period (20/187 to 20/88; P < 0.001) and VA stability during the quiescent period (to 20/93). VA losers had a significant decline in VA during both the treatment and quiescent periods (P < 0.001).Conclusion: Overall, PRN treatment resulted in a decline in VA during a period of apparent disease quiescence. There is a group of patients that does not lose VA during this period, and if patients like these can be identified, their treatment could be optimized to include a period of clinically justified nontreatment. [ABSTRACT FROM AUTHOR]

Controlling stability behavior of single-phase natural circulation loops, without significantly affecting its steady-state characteristics, is a topic of wide research interest. Present study explores the role of loop inclination on a particular loop geometry. Accordingly a 3D computational model of a rectangular loop is developed and transient conservation equations are solved to obtain the temporal variation in flow parameters. Starting from the quiescent state, simulations are performed for selected sets of operating conditions and also with a few selected inclination angles. System experiences instability at higher heater powers and also with higher sink temperatures. Inclination is found to have a strong stabilizing influence owing to the reduction in the effective gravitational acceleration and subsequent decline in local buoyancy effects. The settling time and highest amplitude of oscillations substantially reduces for a stable system with a small inclination. Typically-unstable systems can also suppress the oscillations, when subjected to tilting, within a reasonable period of time. It is possible to stabilize the loop within shorter time span by increasing the tilt angle, but at the expense of reduction in steady-state flow rate. Overall a tilt angle of 15° is suggested for the selected geometry. Results from the 3D model is compared with the predictions from an indigenous 1D code. While similar qualitative influence of inclination is observed, the 1D model predicts early appearance of the stability threshold and hence hints towards larger instability. Accordingly the limitations of 1D approach in terms of the dependence on correlations is highlighted. [ABSTRACT FROM AUTHOR]

A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ \mu \texts and −87 to −152.5 V/ \mu \texts , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- \mu \textm CMOS technology. [ABSTRACT FROM AUTHOR]

Previous numerical studies of the dissipation of internal tides in idealized settings suggest the existence of a critical latitude (~29°) where dissipation is enhanced. But observations only indicate a modest enhancement at this latitude. To resolve this difference between observational and numerical results, the authors study the latitudinal dependence of internal tides' dissipation in more realistic conditions. In particular, the ocean is not a quiescent medium; the presence of large-scale currents or mesoscale eddies can impact the propagation and dissipation of internal tides. This paper investigates the impact of a weak background mean current in numerical simulations. The authors focus on the local dissipation of high spatial mode internal waves near their generation site. The vertical profile of dissipation and its variation with latitude without the mean current are consistent with earlier studies. But adding a weak mean current has a major impact on the latitudinal distribution of dissipation. The peak at the critical latitude disappears, and the dissipation is closer to a constant, albeit with two weak peaks at ~25° and ~35° latitude. This disappearance results from the Doppler shift of the internal tides' frequency, which hinders the nonlinear transfer of energy to small-scale secondary waves via the parametric subharmonic instability (PSI). The new two weak peaks correspond to the Doppler-shifted critical latitudes of the left- and right-propagating waves. The results are confirmed in simulations with simple sinusoidal topography. Thus, although nonlinear transfers via PSI are efficient at dissipating internal tides, the exact location of the dissipation is sensitive to large-scale oceanic conditions. [ABSTRACT FROM AUTHOR]

In this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC–DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC–DC converter has variable conversion ratios and synchronous controller that lets the DC–DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0–10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%. [ABSTRACT FROM PUBLISHER]

A novel near-threshold voltage startup monolithic boost converter is presented in this paper using an adaptive sleeping time control (ASTC) scheme for low-power applications. The proposed ASTC scheme can promote the power efficiency of the current-mode boost converter under light load by automatically adjusting the sleep time of the converter, and the converter's quiescent current drops down to 4A during the sleeping period. In addition, a new soft-start method is introduced to make the boost converter start up with a near-threshold input voltage. The proposed boost converter was fabricated in a standard 0.18m CMOS process and occupies a small chip area of 0.50mm. Experimental results show that the boost converter achieves the minimum 0.5-V startup voltage when the output voltage is set to 1.8V. After startup, the input voltage range can be expanded from 0.3V to 1.5V with a switching frequency of 1MHz. In addition, a peak efficiency of 94% and a minimum efficiency of 81% are measured at the 1.5-V input voltage as the load current ranges from 0.1mA to 100mA. [ABSTRACT FROM AUTHOR]

In this paper, an output-capacitorless, low-dropout (LDO) voltage regulator with excellent load regulation and fast recovery time was designed using two amplifiers, which provided high gain, high bandwidth (HBW), and high slew rate (HSR). In addition, a one-shot current boosting (OSCB) circuit was added for current control to charge and discharge the parasitic capacitance at the power transistor gate during the load-current transition to improve the response time. The experimental results show that the proposed LDO regulator consumes a quiescent current of only 4.5 $$\upmu \hbox {A}$$ and can deliver a maximum load current of 200 mA, while regulating the output voltage at $${\text {1\,V}}$$ with a 1.2 V power supply. We experimentally verified that for a current transition from 0.1 to 200 mA, the undershoot and overshoot voltages were 260 and $${\text {190\,mV}}$$ , with recovery times of only 0.8 and 0.85 $${\upmu }\hbox {s}$$ , respectively. [ABSTRACT FROM AUTHOR]

A detailed study is performed on the parameter space of the mechanical system of a driven pendulum with damping and constant torque under feedback control. We report an interesting bow-tie shaped bursting oscillatory behaviour, which is exhibited for small driving frequencies, in a certain parameter regime, which has not been reported earlier in this forced system with dynamic feedback. We show that the bursting oscillations are caused because of a transition of the quiescent state to the spiking state by a saddle-focus bifurcation, and because of another saddle-focus bifurcation, which leads to cessation of spiking, bringing the system back to the quiescent state. The resting period between two successive bursts (Trest) is estimated analytically. [ABSTRACT FROM AUTHOR]

Although I DDQ testing has become a widely accepted defect detection technique in CMOS ICs, its effectiveness in nanometer technologies is threatened by the increased leakage current variations. In this paper, a current monitoring technique that overcomes the current variations problem in I DDQ testing is proposed. According to this, a core is partitioned into two subcircuits and the intrinsic leakage current of the one subcircuit is used to control the leakage current at the I DDQ sensing node of the other and vice-versa during test application. This way process related leakage current variations are taken into account and small defective currents turn to be detectable according to the needs of modern nanometer technologies. Additionally, a Built-In Current Sensor is presented, which exploits the proposed technique and experimental results are illustrated by its application on a fabricated chip. [ABSTRACT FROM AUTHOR]

Iddq testing is an integral component of test suites for the screening of unreliable devices. As the scale of silicon technology continues shrinking, Iddq values and associated fluctuations increase. In addition, increased design complexity makes defect-induced leakage currents difficult to differentiate from full-chip currents. Consequently, traditional Iddq methods result in more test escapes and yield loss. This brief proposes a new test method, called $\sigma $ -Iddq to provide the following: 1) Iddq analysis with process-parameter deduction and 2) the algorithm for automatic chip-classification called collective analysis without the need to manually determine threshold values. We randomly inserted a number of multiple defects into samples of ISCAS’89 and IWSL’05 benchmark circuits. Experimental results demonstrate that the proposed $\sigma $ -Iddq method can achieve higher classification accuracy than single-threshold Iddq testing or $\Delta $ Iddq in a 45-nm technology. The overall classification accuracy of the collective analysis achieve averaged 99.28% and 99.70% on $\sigma $ -Iddq data from process-parameter deductions with average-case search and multilevel search, respectively, demonstrating that the influence of process variation and design scaling can be significantly reduced to enable a better identification of defective chips. [ABSTRACT FROM AUTHOR]

This paper presents a solution for controlling integrated DC–DC converters with high switching frequency (>20 MHz). The increase of the switching frequency is a trend biased by output filter volume restrictions and integration demand. The control of DC–DC converters operating at high frequency presents an opportunity to speed up the converter response time but also a challenge specially for the control solution, quiescent current and to limit the sensitivity to process and operating conditions for the mixed signal circuits involved. The solution presented in this work relies on separating the duty-cycle into three parts: a load-free value that depends only on the input and output voltages, a transient fast correction contribution, and an accurate compensation for the IR drop that depends on the load current. The load-free portion of the duty-cycle has a compensation of PVT variations and the fast transient part of the duty-cycle uses a non-linear sliding mode control solution. All the analog blocks required for the implementation of the proposed solution are detailed. [ABSTRACT FROM AUTHOR]

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23 dB with respect to the use of conventional biasing. A THD value better than −35 dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5 µm CMOS technology, are able to operate with a supply voltage of 1.2 V and a quiescent power consumption of only 36 µW, using a silicon area <0.025 mm 2 . [ABSTRACT FROM AUTHOR]

A high slew-rate CMOS voltage buffer has been presented in this article. The slew-rate enhancement is achieved by an embedded driver stage activated by internal nodes in the voltage buffer through capacitive coupling. The capacitive coupling provides one-shot auto-off feature for the driver stage. Therefore, the drive stage can be turned off automatically after activation. The auto-off feature of the proposed driver stage guarantees a reliable operation. The proposed voltage buffer is implemented in a commercial 0.35-μm CMOS technology. The active chip area is 345 μm × 246 μm. The single supply voltage is 3.3 V, and the quiescent current is about 7 μA. When the proposed buffer drives a capacitive load of 220 pF, the measured positive and negative slew rates are 0.714 and 1.548 V/μs, respectively. The improvement corresponds to about 22 times for the positive slew rate and 48 times for the negative slew rate when comparing with the voltage buffer without the proposed the slew-rate enhancement circuit. [ABSTRACT FROM PUBLISHER]

An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18µm CMOS process to supply the load current between 0 and 100mA. The dropout voltage of the LDO is set to 200mV for 1.2–2V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7µA. A final benchmark comparison considering all relevant performance metrics is presented. [ABSTRACT FROM AUTHOR]

We introduce two extremely low quiescent current ( I) low-dropout (LDO) voltage regulators. The Low I-LDO (L I-LDO) uses 13 μA of total quiescent current and is designed for a maximum load current of 50 mA. The Micro I-LDO (M I-LDO) uses only 1.2 μA of total quiescent current and is designed for a maximum load current of 5 mA. Detailed pole/zero analysis is performed to aid in the design of the LDOs. Two LHP zeros cancel the two non-dominant poles which extend the bandwidth and improve transient response. Both designs are fully integrated, stabilized with an on-chip capacitive load of 100 pF. In load transient, the total variation in output voltage for L I-LDO and M I-LDO is 1 V and 950 mV, respectively, and the total line transient variation is 668 and 599 mV, respectively. Both designs occupy an area of 0.26 mm in a 0.5-μm CMOS process. Two process-independent figures of merit are proposed to compare L I-LDO and M I-LDO with other published work. [ABSTRACT FROM AUTHOR]

Abstract: This work is devoted to the numerical study of the influence of heterogeneous kinetics on the oxidation rates of a single carbon particle in quiescent and non-quiescent environments. The coal particle is represented by moisture- and ash-free nonporous carbon while the coal rank is implemented using several kinetic rate expressions. The model includes six gaseous chemical species (O2, CO2, CO, H2O, H2, N2). Three heterogeneous reactions are employed (C+O2, C+CO2 and C+H2O), along with two homogeneous semi-global reactions, namely carbon monoxide oxidation and the water–gas shift reaction. Several semi-global reaction rate expressions taken from the literature are utilized. The Navier–Stokes equations coupled with the energy and species conservation equations are used to solve the problem by means of the pseudo-steady state approach. At the surface of the particle, the balance of mass, energy and species concentration is applied including the effect of the Stefan flow and heat loss due to radiation at the surface of the particle. The model and the code used are validated against an analytic two-film model. Good agreement is observed. The numerical simulations performed reveal that the origin of heterogeneous kinetics has a significant effect on the carbon consumption rates of the particle. In particular, the maximal discrepancy between results is achieved in a kinetically controlled regime and is proportional by a factor of 10 in respect to carbon mass flux on the particle surface. Additionally, the influence of the particle Reynolds number referring to the laminar flow regime, the ambient O2 mass fraction and the temperature on the regimes of combustion and gasification is discussed. [Copyright &y& Elsevier]

Acidic interfacial growth can provide a number of industrially important mesoporous silica morphologies including fibers, spheres, and other rich shapes. Studying the reaction chemistry under quiescent (no mixing) conditions is important for understanding and for the production of the desired shapes. The focus of this work is to understand the effect of a number of previously untested conditions: acid type (HCl, HNO 3, and H 2SO 4), acid content, silica precursor type (TBOS and TEOS), and surfactant type (CTAB, Tween 20, and Tween 80) on the shape and structure of products formed under quiescent two-phase interfacial configuration. Results show that the quiescent growth is typically slow due to the absence of mixing. The whole process of product formation and pore structuring becomes limited by the slow interfacial diffusion of silica source. TBOS-CTAB-HCl was the typical combination to produce fibers with high order in the interfacial region. The use of other acids (HNO 3 and H 2SO 4), a less hydrophobic silica source (TEOS), and/or a neutral surfactant (Tweens) facilitate diffusion and homogenous supply of silica source into the bulk phase and give spheres and gyroids with low mesoporous order. The results suggest two distinct regions for silica growth (interfacial region and bulk region) in which the rate of solvent evaporation and local concentration affect the speed and dimension of growth. A combined mechanism for the interfacial bulk growth of mesoporous silica under quiescent conditions is proposed. [ABSTRACT FROM AUTHOR]

The acoustic emissions from single cavitation clouds at an early stage of development in 0.521MHz focused ultrasound of varying intensity, are detected and directly correlated to high-speed microscopic observations, recorded at 1×106 frames per second. At lower intensities, a stable regime of cloud response is identified whereby bubble-ensembles exhibit oscillations at half the driving frequency, which is also detected in the acoustic emission spectra. Higher intensities generate clouds that develop more rapidly, with increased nonlinearity evidenced by a bifurcation in the frequency of ensemble response, and in the acoustic emissions. A single bubble oscillation model is subject to equivalent ultrasound conditions and fitted to features in the hydrophone and high-speed spectral data, allowing an effective quiescent radius to be inferred for the clouds that evolve at each intensity. The approach indicates that the acoustic emissions originate from the ensemble dynamics and that the cloud acts as a single bubble of equivalent radius in terms of the scattered field. Jetting from component cavities on the periphery of clouds is regularly observed at higher intensities. The results may be of relevance for monitoring and controlling cavitation in therapeutic applications of focused ultrasound, where the phenomenon has the potential to mediate drug delivery from vasculature. [ABSTRACT FROM AUTHOR]

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit. [ABSTRACT FROM AUTHOR]

Supercritical fluid injection using a single round injector into a quiescent atmosphere at subcritical and supercritical conditions was studied experimentally with particular attention paid to supercritical-into-subcritical injection and the reassertion of surface tension. The entire system was binary since the surrounding atmosphere consisted of an inert gas of a different composition than that of the injected fluid. Average densities and density gradients were quantified and a method was applied to quantify the resulting drop formation due to the disintegration of the jet based on the experimental conditions. The evolution of drop size with distance from the injector was identified. [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, a low power, output-capacitor-free, low-dropout regulator (LDO) is proposed with a new dynamic biased, multiloop feedback strategy. Initially, a theoretical macromodel is presented based on the analogy between the capless LDO and the mechanical non-linear harmonic oscillator, enabling to shed new light on the non-linear amplification, dynamic and adaptive biasing techniques used in the multiloop feedback LDO control in the large signal context. To implement some of the unexplored abilities of this model the new capless LDO topology is proposed. The output class AB stage of the error amplifier and the non-linear derivative current amplifier of the LDO feedback loop ensure dynamical extended close-loop bandwidth gain and dynamical damping enhancement for fast load and line LDO transients. Using the new dynamic biasing of the derivative loop, an improvement is obtained in the derivative sensing of the fast output voltage variations, enabling a significant enhancement in the transient response of the capless LDO. The proposed LDO, designed for a maximum current of 50mA in UMC RF 1P8M 0.13μm, requires a quiescent current of only 4.1μA and presents excellent transient response when compared to the state-of-the-art. [Copyright &y& Elsevier]

Cellular proliferation depends on the integration of mitogenic stimuli with environmental conditions. Increasing evidence suggests that microRNAs play a regulatory role in this integration. Here we show that during periods of cellular quiescence, mature microRNAs are stabilized and stored in Argonaute protein complexes that can be activated by mitogenic stimulation to repress mitogen-stimulated targets, thus influencing subsequent cellular responses. In quiescent cells, the majority of microRNAs exist in low molecular weight, Argonaute protein-containing complexes devoid of essential components of the RNA-induced silencing complex (RISC). For at least 3 wk, this pool of Argonaute-associated microRNAs is stable and can be recruited into RISC complexes subsequent to mitogenic stimulation. Using several model systems, we demonstrate that stable Argonaute protein-associated small RNAs are capable of repressing mitogen-induced transcripts. Therefore, mature microRNAs may represent a previously unappreciated form of cellular memory that allows cells to retain posttranscriptional regulatory information over extended periods of cellular quiescence. [ABSTRACT FROM AUTHOR]

A wideband feedback linearization technique for a power amplifier (PA), PA-closed loop, is presented. In order to achieve wideband operation, it employs a two-path feedback scheme where the input and output phases and amplitudes are detected at RF and compared to directly control and linearize the PA. The wideband characteristic of the loop suppressed the adjacent channel leakage ratio (ACLR) for WCDMA standard by 6 dB. The advantage of the feedback is demonstrated by measuring the performance against the load variation. The required back-off is degraded by only 1 dB with a voltage standing wave ratio (VSWR) of 1.5, whereas it is 3 dB without the loop. The loop consumes 28.3 mW and it reduces the quiescent power consumption of the PA by 78 mW. The chip, which integrates the loop and PA, is fabricated in a 0.13 \mum CMOS technology and the loop occupies 0.3 mm by 0.7 mm. The PA delivers WCDMA output power of 27.1 dBm with a power added efficiency (PAE) of 28% and ACLR of 40 dBc. This topology makes possible the wideband feedback linearization of a watt-level PA. [ABSTRACT FROM AUTHOR]

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90 nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3 μV/mA with a 1.2 V input and 1 V output. For a 100 mA load current step with the rise/fall time of 100 ps, the LDO achieves maximum output voltage drop and overshoot of less than 95 mV when loaded by a 600 pF decoupling capacitor and consumes an average bias current of 408 μA. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005 mm. Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves. [ABSTRACT FROM AUTHOR]

Geophysical observations have shown that transient slow slip events, with average slip speeds v on the order of 10-8 to 10-7 m/s, occur in some subduction zones. These slip events occur on the same faults hut at greater depth than large earthquakes (with slip speeds of order ∼1 m/s). We explore the hypothesis that whether slip is slow or fast depends on the competition between dilatancy, which decreases fault zone pore pressure p, and thermal pressurization, which increases p. Shear resistance to slip is assumed to follow an effective stress law τ = f( σ - p)  fσ. We present two-dimensional quasidynamic simulations that include rate-state friction, dilatancy, and heat and pore fluid flow normal to the fault. We find that at lower background effective normal stress (σ), slow slip events occur spontaneously, whereas at higher a, slip is inertially limited. At intermediate σ dynamic events are followed by quiescent periods, and then long durations of repeating slow slip events. In these cases, accelerating slow events ultimately nucleate dynamic rupture. Zero-width shear zone approximations are adequate for slow slip events but substantially overestimate the pore pressure and temperature changes during fast slip when dilatancy is included. [ABSTRACT FROM AUTHOR]

A 1.5 V low-power stereo audio codec in 0.13 \mum CMOS is described. The microphone path includes a programmable gain stage with an enhanced transconductance cell followed by a continuous-time \Sigma \Delta ADC with capacitive feed-forward and capacitive direct feedback. The speaker path employs a 1 mA Class-AB speaker amplifier with an improved quiescent current control circuit that delivers 30 mW to a 32 \Omega speaker. The audio input and output paths achieve 92 and 98 dB dynamic range, respectively, with 6.5 mA total quiescent current. [ABSTRACT FROM PUBLISHER]