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This paper deals with the design and analysis of a new 4-2 compressor which can be used in high-speed multipliers. The proposed compressor features eliminated glitch at the output waveform. By optimum tuning of the width of the transistors, Cout is produced more quickly, and therefore higher operating speeds can be achieved. The effect of process variation on the circuit has been studied and a new structure is proposed to overcome the effect of process variation by utilizing a reference voltage generator circuit. A 32 × 32-bit multiplier has been developed utilizing these compressors in order to evaluate the new compressor in a practical environment. The total multiplier circuit was simulated with HSPICE simulator (BSIM3v3 parameters) using CMOS standard cell library of 0.18 µm and the Layouts were extracted with Cadence Virtuoso v 5.1 Layout Plus tool. The simulation results represent 185 × 10−3 pj Power-Delay-Product (PDP) and 40 pj × ps Energy Delay Product (EDP) with 221 ps delay from input to output. [ABSTRACT FROM AUTHOR]

The article presents a root mean square (RMS) to direct current (dc) converter based on an externally linear-internally nonlinear (ELIN) filter. The converter contains an averaging filter and two nonlinear blocks. The principle of operation of an ELIN circuit using an example of the ELIN integrator was presented. Three converters were developed and simulated each using four multiplier/divider integrated circuits. Preliminary tests of the input dynamic range of the three circuits were made by SPICE simulations. The prototype of the RMS-to-dc converter with a third-degree ELIN filter shows an improved dynamic range in comparison to classic “implicit square-rooting” converters as its error is reduced at lower amplitudes of the input voltage. The measured bandwidth of the ELIN converter prototype is wider in comparison to the “implicit square-rooting” converter prototype, built from nominally the same nonlinear components. The converter based on the presented circuit can be used in applications, where a wide voltage range and wide bandwidth are needed. [ABSTRACT FROM AUTHOR]

In this paper, a low-voltage and low-power current mode analog multiplier design is presented. The multiplier is based on dynamic threshold MOS (DTMOS) structure. The proposed topology consists of four current squarer circuits and one subtractor structure. Each squarer cell has two MOS transistors and the subtractor consists four MOS transistors. Therefore, the multiplier employs 12 MOS transistors excluding resistors and biasing current sources. The introduced circuit consumes low power and requires low voltage power supplies thanks to DTMOS structure. The current mode analog multiplier architecture has a power consumption of 99.76nW and involves a single supply voltage of 0.3 V owing to including DTMOS transistor. The analysis results agree well with the expected results. The behaviour of the suggested multiplier has been verified through the analysis results with the help of LTspice simulation software and 0.13 µm IBM CMOS technology parameters have been used for simulation. [ABSTRACT FROM AUTHOR]

Inference efficiency is the predominant design consideration for modern machine learning accelerators. The ability of executing multiply-and-accumulate (MAC) significantly impacts the throughput and energy consumption during inference. However, MAC operation suffers from significant ineffectual computations that severely undermines the inference efficiency and must be appropriately handled by the accelerator. The ineffectual computations are manifested in two ways: first, zero values as the input operands of the multiplier, waste time and energy but contribute nothing to the model inference; second, zero bits in nonzero values occupy a large portion of multiplication time but are useless to the final result. In this article, we propose an ineffectual-free yet cost-effective computing architecture, called split-and-accumulate (SAC) with two essential bit detection mechanisms to address these intractable problems in tandem. It replaces the conventional MAC operation in the accelerator by only manipulating the essential bits in the parameters (weights) to accomplish the partial sum computation. Besides, it also eliminates multiplications without any accuracy loss, and supports a wide range of precision configurations. Based on SAC, we propose an accelerator family called Tetris and demonstrate its application in accelerating state-of-the-art deep learning models. Tetris includes two implementations designed for either high performance (i.e., cloud applications) or low power consumption (i.e., edge devices), respectively, contingent to its built-in essential bit detection mechanism. We evaluate our design with Vivado HLS platform and achieve up to 6.96 × performance enhancement, and up to 55.1 × energy efficiency improvement over conventional accelerator designs. [ABSTRACT FROM AUTHOR]

Stochastic computing offers an area‐efficient solution for power‐greedy computations in error‐resilient applications such as image processing. However, stochastic computing produces only approximated results and suffers from long latency especially for multiplication. The authors present a multiplier design technique for stochastic computing which guarantees exact output and has latency in the order of 2N (N = input precision), utilising the counter for unary‐to‐binary conversion. Compared to state‐of‐the‐art deterministic methods the proposed design is faster by a factor of 2N. Besides, the area of proposed design scales up in proportion to N instead of N2, as opposed to conventional binary multipliers. The design technique can be further extended for multiple inputs and parallel computing, Extensive mathematical analysis and simulation results are presented for each variation throughout this Letter. [ABSTRACT FROM AUTHOR]

Nowadays, convolutional neural networks (CNNs) have become a research hotspot because of their high performance in computer vision and pattern recognition. However, as the high energy consumption of traditional graphic processing units‐based CNNs, it is difficult to deploy them into portable devices. To deal with this problem, a hybrid CNN structure (XNORCONV) was proposed and implemented on field‐programmable gate array (FPGA) in this study. Two improvements have been applied in XNORCONV. Firstly, the multiplications in the convolutional layer (CONV) were replaced by XNOR operations to save the multiplier and reduce computational complexity. Secondly, an inter‐layer pipeline was designed to further accelerate the calculation. XNORCONV was implemented on Xilinx Zynq‐7000 xc7z020clg400‐1 under the clock frequency of 150 MHz and tested with MNIST dataset. The results of the experiment show that XNORCONV can classify each picture from MNIST in 18.97μs, and achieve 98.4% recognition accuracy. Compared with traditional Lenet‐5 on different platforms, XNORCONV reduced multiplication by 85.6% with only 0.4% accuracy loss. [ABSTRACT FROM AUTHOR]

A frequency multiplier for the direct generation of the fourth, sixth, or eighth harmonic of an input signal in a single stage is presented. By analyzing the effect of clipping both half-waves in the output signal asymmetrically, beneficial clipping thresholds are identified. Based on the ideal signal analysis, circuit simulations are carried out to investigate and implement the proposed approach using a heterojunction bipolar transistor (HBT) push–push cascode amplifier, which enables the independent adjustment of the clipping thresholds. Finally, the circuit is combined with an input balun and an output amplifier and fabricated in a 130-nm SiGe BiCMOS process for verification. Measurement results of the prototype are compared with simulations based on available VBIC and HICUM models for the HBTs, providing insight on their capabilities to predict the high-order nonlinear effects essential for the operation of the presented multiplier. The circuit performs in general agreement with the HICUM model simulations and represents a versatile times-four, times-six, and times-eight frequency multiplier with a 37-GHz output-referred bandwidth from 173 to 210 GHz and an output power of up to −6 dBm. To the the best of the authors’ knowledge, the conversion gain of 10 dB is the highest in class reported up to date, even when compared to III/V-based circuits. A maximum harmonic suppression of 40 dB and a total dc power consumption of 63 mW are measured. [ABSTRACT FROM AUTHOR]

Summary: This paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5M + 4S + 2D and 5M + 4S + 1D, respectively, where, M, S, and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields F 2 163 and F 2 233 are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works. [ABSTRACT FROM AUTHOR]

In this Letter, a reconfigurable processing element (PE) for pipelined SDF FFT architecture is presented, which can be configured to compute 2, 3 and 5-point DFTs. Foremost, the proposed PE architecture for the 5-point DFT computation is designed by factorising the 5-point DFT computation operation into $2\times 2$2×2 cyclic convolution units and then the 2- and 3-point DFTs structures are mapped on to it using multiplexers. Thus, all three configurations are possible. In the case of prior 5-point PE designs, the PE can start its operation only after the arrival of all the five-input data, whereas the proposed PE completes a part of computation after the arrival of the first three inputs and reuse the same hardware to process the next two inputs. As a result, the proposed PE requires less hardware, at the same time, preserving the throughput of prior PE. The proposed PE required 25% less multiplier and one adder less compared to the Winograd algorithm based 5-input PE. [ABSTRACT FROM AUTHOR]

In this Letter, a reconfigurable processing element (PE) for pipelined SDF FFT architecture is presented, which can be configured to compute 2, 3 and 5‐point DFTs. Foremost, the proposed PE architecture for the 5‐point DFT computation is designed by factorising the 5‐point DFT computation operation into 2×2 cyclic convolution units and then the 2‐ and 3‐point DFTs structures are mapped on to it using multiplexers. Thus, all three configurations are possible. In the case of prior 5‐point PE designs, the PE can start its operation only after the arrival of all the five‐input data, whereas the proposed PE completes a part of computation after the arrival of the first three inputs and reuse the same hardware to process the next two inputs. As a result, the proposed PE requires less hardware, at the same time, preserving the throughput of prior PE. The proposed PE required 25% less multiplier and one adder less compared to the Winograd algorithm based 5‐input PE. [ABSTRACT FROM AUTHOR]

Circuit approximation has been introduced in recent years as a viable method for constructing energy‐efficient electronic systems. An open problem is how to effectively obtain approximate circuits showing good compromises between key circuit parameters – the error, power consumption, area and delay. The use of evolutionary algorithms in the task of circuit approximation has led to promising results. Unfortunately, only relatively small circuit instances have been tackled because of the scalability problems of the evolutionary design method. This study demonstrates how to push the limits of the evolutionary design by choosing a more suitable representation on the one hand and a more efficient fitness function on the other hand. In particular, the authors show that employing full adders as building blocks leads to more efficient approximate circuits. The authors focused on the approximation of key arithmetic circuits such as adders and multipliers. While the evolutionary design of adders represents a rather easy benchmark problem, the design of multipliers is known to be one of the hardest problems. The authors evolved a comprehensive library of energy‐efficient 12‐bit multipliers with a guaranteed worst‐case error. The library consists of 65 Pareto dominant solutions considering power, delay, area and error as design objectives. [ABSTRACT FROM AUTHOR]

This paper presents a new method called optimal shift reassignment (OSR), used for reconfigurable multiplication circuits. These circuits consist of adders, subtractors, shifts, and multiplexers (MUXs). They calculate the multiplication of an input number by one out of several constants which can be selected dynamically during run-time. The OSR method is based on the idea that shifts can be placed at different positions along the circuit, while the calculated output constant stays the same. This differs from previous approaches, which were limited by the fact that all constants within the constant multiplier were forced to be odd. The OSR method subsequently releases this restriction. As a result, the number of required MUXs in the circuit can be reduced. This happens when the shift reassignment aligns the shift values of different inputs of an MUX. Experimental results show MUX savings of up to 50% and average savings between 11% and 16% using the OSR method compared to previous approaches. [ABSTRACT FROM PUBLISHER]

Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic‐curve cryptography (ECC) and Rivest–Shamir–Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40‐channel RNS moduli‐set is proposed for this architecture to benefit from the short‐channel width of the RNS moduli‐set. The throughput of the architecture is enhanced by pipelining and pre‐computations. The proposed architecture is fabricated as an ASIC using 65‐nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low‐voltage and energy‐efficient ECCs. [ABSTRACT FROM AUTHOR]

The fused-multiply-add (FMA) instruction is a common instruction in RISC processors since 1990. A 3-stage, 8-level pipelined, dual-precision FMA is proposed here that can perform operations either at one double precision (SISD) or at two single precision in parallel (SIMD). The 53-bit mantissa-multiplier (MM) is optimally segmented by Karatsuba–Offman (KO) algorithm such that both modes can be performed. The 6-stage pipelined MM uses only 6 of 10 multipliers and 13 of 33 adder/subtractors in SIMD. Thus hardware area of the proposed MM is reduced by 23.82% and throughput is maintained to be 923M samples/s. The arithmetic operational units in the data path are shared among the modes by having four data rearrangement units (DRU) which rearranges the data systematically at the input, the outputs of MM and the final output. Though these DRUs bring some hardware overhead, the resulting architecture is modular and uniform for both modes of computation. The proposed FMA has been implemented using TSMC 1P6M CMOS 130 nm library and takes 48% less overall area and consumes 49% less power at 308.7 MHz compared to previous results. The area-delay-product (ADP), 0.48 × 10 −15 shows that the area optimization by proposed KO based MM can also keep the computation time as 3.24 ns. [ABSTRACT FROM AUTHOR]

Due to dependency on Plug Setting (PS), Time Dial Setting (TDS), size of the network, more than one back-up relays for one primary relay and other technical constraints, coordination of Directional Overcurrent Relays (DOCRs) is an extremely constrained and nonlinear optimization problem. In this paper, a new Gravitational Search (GS) based algorithm is presented for achieving optimal coordination of directional overcurrent relays. The proposed algorithm utilizes user defined characteristic for inverse time overcurrent relays than the predefined standard curves. The user defined relay characteristic deals with constants that control the shape of the characteristics as variable adjustable values which are optimally chosen along with TDS and Plug Setting Multiplier (PSM). The performance of the proposed algorithm has been evaluated on 8-bus, 15-bus and IEEE 30-bus distribution network at different fault locations (near-end, far-end and middle point). In addition, the time of operation of some of the primary relays at different fault locations on IEEE 30-bus distribution network is also presented. At the end, comparative evaluation of the proposed algorithm with other optimization algorithms having different relay characteristics presented in the literature clearly indicates its effectiveness and superiority in terms of the sum of total primary relays operating time. [ABSTRACT FROM AUTHOR]

This paper introduces a new heuristic to generate pipelined run-time reconfigurable constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to the optimum. It is based on an optimal algorithm which fuses already optimized pipelined constant multipliers generated by an existing heuristic called reduced pipelined adder graph (RPAG). Switching between different single or multiple constant outputs is realized by the insertion of multiplexers. The heuristic searches for a solution that results in minimal multiplexer overhead. Using the proposed heuristic reduces the run-time of the fusion process, which raises the usability and application domain of the proposed method of run-time reconfiguration. An extensive evaluation of the proposed method confirms a 9%–26% FPGA resource reduction on average compared to previous work. For reconfigurable multiple constant multiplication, resource savings of up to 75% can be shown compared to a standard generic lookup table based multiplier. Two low level optimizations are presented, which further reduce resource consumption and are included into an automatic VHDL code generation based on the FloPoCo library. [ABSTRACT FROM PUBLISHER]

Linear programming decoding with the alternating direction method of multipliers (ADMM) is a promising decoding technique for low-density parity-check (LDPC) codes, where the computational complexity of Euclidean projections onto check polytopes becomes a prominent problem. In this paper, the problem is circumvented by building lookup tables (LUTs) and quantizing the inputs to approach approximate Euclidean projections at low computational complexities. To challenge the huge memory cost of LUTs, we first propose two commutative compositions of Euclidean projection and self-map, and show the existence of a small quantization range which does not alter the Euclidean projection. Then, we investigate the design and simplification of the LUTs by exploiting the commutative compositions and check node decomposition techniques. An efficient algorithm for the LUT-based projection is demonstrated by using one simplification method. Simulation results show that for both the regular and irregular LDPC codes, the ADMM decoding using LUT-based projection can substantially reduce the decoding time while maintaining the error rate performance at a comparatively large memory cost. [ABSTRACT FROM PUBLISHER]

In this paper we propose techniques for decreasing the power consumption of multipliers. The proposed techniques exploit data statistics. Specifically we propose two architectures for two-input signed multipliers, namely selective activation multiplier and partitioned multiplier. To illustrate the benefits achieved by the proposed architectures, their application in the implementation of multipliers used in DCT and DWT is detailed. The power reduction reported is up to 20:7 percent for cases of practical interest. The proposed multipliers can be easily implemented, adapted, and combined with prior-art low-power techniques with a moderate area and time overhead. [ABSTRACT FROM AUTHOR]

This study presents a scalable hardware architecture for modular multiplication in prime fields GF(p). A novel iterative digit–digit Montgomery multiplication (IDDMM) algorithm is proposed and two hardware architectures that compute that algorithm are described. The input operands (multiplicand, multiplier and modulus) are represented using as radix β = 2k. Multiplication over GF(p) is possible using almost the same hardware since the complexity of multiplier's kernel module depends mainly on k and not on p. The novel hardware architectures of GF(p) multipliers were evaluated on three Xilinx FPGA families. Design trade‐offs were analysed considering different operand sizes commonly used in cryptography and different digits sizes. The proposed designs for IDDMM are well suited to be implemented in modern FPGAs, making use of available dedicated multipliers and memory blocks reducing drastically the FPGA's standard logic while keeping an acceptable performance compared with other implementation approaches. From the Virtex5 implementation, the proposed MM multiplier reaches a throughput of 242 Mbps using only 219 FPGA slices and achieving a 1024‐bit modular multiplication in 4.21μs. This is 26 times less area resources than similar related works in the literature with an improved efficiency of 7x. [ABSTRACT FROM AUTHOR]

A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60 to 90 % in ancilla qubits count over the existing work on reversible quantum integer multipliers. [ABSTRACT FROM AUTHOR]

We propose and investigate an electrical-to-optical clock multiplier, based on a bismuth-substituted yttrium iron garnet (Bi:YIG) magnetoplasmonic Mach-Zehnder interferometer (MZI). Transient magnetic fields induce a precession of the magnetization vector of the Bi:YIG, which in turn modulates the nonreciprocal phase shift in the MZI arms, and hence the intensity at the output port. We show that the device is capable of modulation depth of 16.26 dB and has a tunable output frequency between 279.9 MHz and 5.6G Hz. Correspondingly, the input electrical modulation frequency can be multiplied by factors of up to 2:1 x 10³ in the optical signal. Such a device is envisioned as a critical component in the development of hybrid electrical-optical circuitry. [ABSTRACT FROM AUTHOR]

In this paper, we introduce an architecture of pre-encoded multipliers for digital signal processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values $\lbrace -1,0,+1,+2 \rbrace$ or $\lbrace -2,-1,0,+1 \rbrace$ , is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme. [ABSTRACT FROM AUTHOR]

This article presents a novel structure to design miniaturized dual-band filtering power dividers. It is realized by combining the feeding lines and coupled stub-loaded quarter-wavelength resonators. The operating frequencies can be adjusted easily by controlling the stub length of the resonator. Source–load coupling is employed to generate transmission zeros to enhance the selectivity. A resistor is added to guarantee the isolation and port matching. For demonstration, a dual-band filtering power divider is implemented. Good agreement between the prediction and measurement validates the proposed method. [ABSTRACT FROM AUTHOR]

ABSTRACT In this article, a miniaturized multiband antenna for multiple input and multiple output (MIMO) system is proposed. The proposed structure consists of two methods to obtain size reduction with a meandering monopole antenna and a quarter-wavelength slot antenna. The antenna element is implemented on a FR4 PCB with dimensions of 20.6 × 29.5 × 0.8 mm3 for USB dongle applications. Measurements show that the isolation is below l0 dB and |S11| and |S22| is smaller than −6 dB at 2.5 GHz, 3.5 GHz, and 5.5 GHz. To evaluate the mutual coupling effect of MIMO system, the correlation coefficients are determined by the measured scattering parameters. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2555-2558, 2015 [ABSTRACT FROM AUTHOR]

ABSTRACT A five-port power divider with single-ended input and two differential-ended outputs is proposed. The frequency ranges from 9 to 11 GHz with a central frequency of 10 GHz. A stepped impedance line with open stubs is used between differential pairs for broadening the bandwidth and miniaturization of the divider. The divider is fabricated and the measurement results comply with the simulation. A proper performance for differential mode signal is achieved. The insertion loss is within 1.8 dB, the isolation is more than 15 dB, and the return loss is more than 11 dB. In addition, the common mode suppression is reached as well. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2669-2673, 2015 [ABSTRACT FROM AUTHOR]

Conventional array multiplier based on carry save adders is optimized in this letter. Some specific full adders in the adders array for partial products accumulation are simplified without any cost. By modifying the logic expressions of two special full adders, circuit complexity is reduced, resulting in decreased power dissipation and propagation delay. Static circuit structures for the adders are provided to demonstrate the effectiveness. Furthermore, logical AND gates to produce partial products are redesigned to save area and power. The layout regularity of array multiplier is well preserved. Circuit simulation shows that speed and power can be improved 9.7% and 3.1% for a 4*4 structure, and the number of transistors decreases 5.3%. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

One of the most popular tools used for risk assessment of marine machinery systems is Failure Mode and Effect Analysis (FMEA). With this analysis tool, risk is represented in the form of a risk priority number (RPN) which is computed by multiplying the severity rating (S) by the occurrence probability (O) and the detection rating (D) for all failure modes of the system. This conventional FMEA has been criticised as having several limitations such as inability to aggregate imprecise ratings of multiple experts and inability to incorporate more than three risk criteria. These challenges have been addressed in this paper by developing two novel methodologies for prioritising the risk of failure modes for marine machinery systems. The first methodology integrates an averaging technique with VIKOR (Vlsekriterijumska Optimizacija Ikompromisno Resenje, meaning: Multicriteria Optimisation and Compromise Solution). The second methodology integrates an averaging technique with the Compromise Programming (CP) technique. While the averaging technique is applied as a means of aggregating imprecise risk criteria ratings from multiple experts, VIKOR and CP are used in the ranking of risk of failure modes. The applicability and suitability of these methodologies for risk prioritisation is demonstrated using two case studies. [ABSTRACT FROM AUTHOR]

The quest continues for microelectronic implementations with higher throughput and reduced power consumption, particularly for digital signal processing, graphic processing unit and CPU portable applications. This Letter focuses on the digital multiplier circuit, which is a key component in determining the power‐delay‐product for numerous battery powered applications. A proposed radix‐4 8 × 8 Booth multiplier is implemented using four stages with a unique optimised stage‐1 architecture. Instead of using adder/subtractor in stage‐1, it is replaced with a novel binary‐to‐2's complement converter and a 2:1 MUX to reduce the delay and power consumption by 7.08 and 49.46%, respectively, compared to the other stages. The proposed design is implemented using CMOS 90 nm technology with 1.2 V supply to demonstrate performance. [ABSTRACT FROM AUTHOR]

New superconductor single flux quantum logics with no static power dissipation in bias resistors, such as Reciprocal Quantum Logic (RQL), offer opportunities to create energy-efficient superconductor processors operating at high frequencies with ultra-low power consumption. This paper discusses the results of our work on the cell-level design and analysis of a benchmark set of 32-/64-bit RQL processor integer and floating-point units such as adders, multipliers, an arithmetic-logic unit, and an array shifter, as well as small 1–4 Kbit RQL on-chip storage components such as register files, on-chip memory, and the top level caches. Our layout-aware design process includes the complete cell-level design and approximate physical layout of the circuits followed by the VHDL simulation, verification, and energy profiling using our RQL VHDL cell library tuned to the future MIT Lincoln Laboratory 10 \kA/cm^2 248 nm process with 10 Nb metal layers and the minimum JJ critical current of 38 \mu\A. Our designs have the energy efficiency of $\sim$1.0 single-precision TFLOPS/W and $\sim$0.5 double-precision TFLOPS/W for floating-point units, and $\sim$1–24 TOPS/W for 32-bit integer units at room temperature using the cryocooling efficiency of 0.1 $\%$ (1000 W/W). The 1–4 Kbit 32-/64-bit multi-ported scratchpad memory, register files, write-through and write-back caches designed with RQL Non-Destructive Read-Out storage cells have the average energy consumption of 3.0–9.5 fJ/bit/operation at room temperature using the cryocooling efficiency of 0.1 $\%$. While these results are very promising, more work is needed to evaluate the contribution of the energy costs of instruction scheduling and off-chip main memory access to the energy efficiency of RQL computing across a whole system. [ABSTRACT FROM PUBLISHER]

Techniques of a dual-path error amplifier and two capacitor multipliers for providing on-chip frequency compensation and soft-start function are proposed in this paper. The concept of the dual-path error amplifier is to use two currents to charge and discharge a compensation capacitor simultaneously. As a result, the equivalent capacitance is enlarged significantly with little additional power and silicon area. The dc-dc converter with the dual-path architecture also has great performance in transient response because the compensation capacitor is reduced significantly. For the soft-start function, the subtractive-type and time-average capacitor multipliers are used to relax the restriction of the capacitance and the charging current. Consequently, it is easy to integrate the soft-start capacitance into a chip and the output overshoot voltage can be suppressed. A prototype converter fabricated with TSMC 0.35-μm 2P4M CMOS process verifies the effectiveness of the techniques of a dual-path error amplifier and two capacitor multipliers. Experimental results demonstrate the converter stability, transient response, and soft-start function. The transient recovery time and transient ripple are less than 20 μs and 25 mV, respectively, for the load current swing from 50 to 500 mA. Moreover, the soft-start time is up to 8 ms. With the proposed techniques, the external pins of the dc-dc converters are minimized and their performance is improved significantly. [ABSTRACT FROM AUTHOR]

Balanced ternary number representation and arithmetic, based on the symmetric radix‐3 digit set {−1, 0, +1}, has been studied at various times in the history of computing. Among established advantages of balanced ternary arithmetic are representational symmetry, favourable error characteristics and rounding by truncation. In this study, we show an additional advantage: that of lower‐error truncated multiplication with the same relative cost reduction as in truncated binary multipliers. [ABSTRACT FROM AUTHOR]

The paper presents an extension of the Hybrid Transport Point Kinetic (HTPK) model to initially-critical multiplying structures, i.e. in a source-free medium with transients starting from the equilibrium between neutron distribution and precursor concentrations. The mathematical model behind the HTPK methodology is derived from the detailed time-dependent balance equations and with reference to the limiting cases (i.e., point model and multi-collision models). Numerical simulations of transient systems demonstrate the interesting features of HTPK, which is shown to sensibly increase the accuracy of classical point kinetics models even at low truncation orders. [ABSTRACT FROM AUTHOR]

Floating‐point (FP) multiply‐add fused (F1*F2±F3) and multiply‐accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital signal processing (DSP). This study proposes FP multiply‐add fused units for low‐precision formats (IEEE 16‐bit half precision or the 32‐bit single precision) which rely on modern Field Programmable Gate Array (FPGA) features such as the available integer multiply‐accumulate‐based support built‐in the FPGA DSP blocks. These are employed as building‐blocks within the mantissa data‐path processing for the multiplication and the add/subtract operations. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply‐add stage: a right shift on the addend, and, a right shift for one of the multiplicands. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are obtained for the multiply‐add fused operation. [ABSTRACT FROM AUTHOR]

The realization of capacitive converters based on a modular approach is presented and analyzed in this paper. The converters are based on topologies with identical capacitors. First, the switching network (SN) of a basic series–parallel topology is presented. The analysis reveals the assembly and growth rules for expanding the topology to any number of capacitors. Subsequently, the SN for the more versatile and complex general transposed series–parallel (GTSP) topology is presented. The topology is expanded by defining a basic cell comprising a capacitor and five peripheral switches. The expansion of this converter improves its performance by ameliorating accuracy and regulation in the dc/dc voltage ratio. The control schemes of these converters are also presented with emphasis on the GTSP topology, whose switches are not assigned in advance. The control scheme for achieving the desired voltage ratio is described. A five-capacitor converter with its control is built to illustrate the theory in open-loop mode, which provides experimental results that are in full agreement with the analytical predictions. [ABSTRACT FROM PUBLISHER]

This letter expands upon an optimum design of integrated switched-capacitor Dickson charge pump multipliers for minimizing the power, which considers the parasitic capacitance of both the top and bottom plates of pump capacitors. This letter also discusses an optimum design with area power balance, and suggests that the number of stages should be ϵ N\bf MIN, where \varepsilon is 1.5–1.7 and N\bf MIN is the minimum number of stages required to meet the condition that the output current is zero at a given output voltage. [ABSTRACT FROM AUTHOR]

Numerous contributions on reverse conversion methods based on the Chinese Remainder Theorem (CRT), for residue number systems (RNS), have been regularly appearing in relevant literature. Reverse conversion is known as a slow RNS operation that becomes more complicated and slower for larger moduli sets. In this study, the authors examine four previous reverse converters for moduli set ƒ = {2q − 1, 2q + 3, 2q + 1, 2q − 3}. Three of these converters heavily utilise Read Only Memories (ROM), and the other one uses a Montgomery multiplier. In order to cut the costs and improve performance, the authors propose an adder‐only two‐stage New CRT conversion scheme that uses conjugate grouping of the moduli as {{2q± 1, 2q± 3}}. Also, manipulation of multiplicative inverse coefficients that are expressed as a series of power‐of‐two terms takes place via multi‐operand addition instead of using ROMs and/or multipliers. This leads to roughly 22, 19 and 8% improvement in delay, area consumption and power dissipation, respectively, in comparison to the only previous ROM‐less design for ƒ. Moreover, use of no ROMs allows for pipelining, if desired. They also address four state‐of‐the‐art converters and compare their performance with the authors (i.e. that of ƒ), where none is faster than the proposed converter. They support their claims with analytical gate‐level comparisons and via synthesis results. [ABSTRACT FROM AUTHOR]

This paper deals with the development of an analog electronic wattmeter based on a high-accuracy electronic four-quadrant multiplier and appropriate amplifying and averaging circuits. The proposed instrument presents a simple design and is constructed using commercially available components. Its main advantage is that it can be integrated with the signal conditioning circuit, obtaining low cost, high resolution, and reduced dimensions. It can measure in circuits with very low power factors and nonsinusoidal waveforms. The implemented prototype is a portable laboratory instrument, integrated with a digital system capable of processing the signals, and displaying the main parameters of both electric power and energy. It has been designed to easily integrate the main blocks in that either industrial or civil equipment requiring the power measurement for monitoring or control purposes. A Fluke 6100 A power standard is used to calibrate the wattmeter over a wide range of current magnitudes and widths and at power factors down to 0.02; several results are reported and discussed. [ABSTRACT FROM PUBLISHER]

Energy-efficient computation is critical if we are going to continue to scale performance in power-limited systems. For floating-point applications that have large amounts of data parallelism, one should optimize the throughput/mm2 given a power density constraint. We present a method for creating a trade-off curve that can be used to estimate the maximum floating-point performance given a set of area and power constraints. Looking at FP multiply-add units and ignoring register and memory overheads, we find that in a 90 nm CMOS technology at 1 W/mm2, one can achieve a performance of 27 GFlops/mm2 single precision, and 7.5 GFlops/mm double precision. Adding register file overheads reduces the throughput by less than 50 percent if the compute intensity is high. Since the energy of the basic gates is no longer scaling rapidly, to maintain constant power density with scaling requires moving the overall FP architecture to a lower energy/performance point. A 1 W/mm2 design at 90 nm is a "high-energy" design, so scaling it to a lower energy design in 45 nm still yields a 7× performance gain, while a more balanced 0.1 W/mm2 design only speeds up by 3.5× when scaled to 45 nm. Performance scaling below 45 nm rapidly decreases, with a projected improvement of only ~3x for both power densities when scaling to a 22 nm technology. [ABSTRACT FROM AUTHOR]

Efficient GF(2m) arithmetic clearly affects the performance of compute‐intensive applications. A new low‐complexity parallel‐in/out systolic AB2 multiplier based on the least significant bit‐first scheme is presented. Compared with related works, the scheme yields significantly lower area‐time complexity. [ABSTRACT FROM AUTHOR]

In this Letter, an efficient implementation of the bit‐parallel polynomial basis (PB) multiplier over the binary field GF(28) generated by the type I irreducible pentanomial f(y) = y8 + y4 + y3 + y + 1 is presented. This pentanomial is especially important because it is used in the advanced encryption standard (AES). Therefore, any optimisation of the multiplier complexity over this finite field is very relevant because efficient AES implementation can be obtained. The bit‐parallel multiplier here presented has the lowest delay known to date for similar multipliers based on this irreducible pentanomial. [ABSTRACT FROM AUTHOR]

The demand for improved SIMD floating-point performance on general-purpose x86-compatible microprocessors is rising. At the same time, there is a conflicting demand in the low-power computing market for a reduction in power consumption. Along with this, there is the absolute necessity of backward compatibility for x86-compatible microprocessors, which includes the support of x87 scientific floating-point instructions. The combined effect is that there is a need for low-power, low-cost floating-point units that are still capable of delivering good SIMD performance while maintaining full x86 functionality. This paper presents the design of an x86-compatible floating-point multiplier (FPM) that is compliant with the IEEE-754 Standard for Binary Floating-Point Arithmetic [12] and is specifically tailored to provide good SIMD performance in a low-cost, low-power solution while maintaining full x87 backward compatibility. The FPM efficiently supports multiple precisions using an iterative rectangular multiplier. The FPM can perform two parallel single-precision multiplies every cycle with a latency of two cycles, one double-precision multiply every two cycles with a latency of four cycles, or one extended-double-precision multiply every three cycles with a latency of five cycles. The iterative FPM also supports division, square-root, and transcendental functions. Compared to a previous design with similar functionality, the proposed iterative FPM has 60 percent less area and 59 percent less dynamic power dissipation. [ABSTRACT FROM AUTHOR]

Fully homomorphic encryption (FHE) is a technique enabling processing to be performed directly on encrypted data in a commercial cloud environment, thereby preserving privacy. Large integer multiplication is the most time-consuming operation during the FHE. Concerning this issue, this paper proposes an operands merging method of the number theoretic transform (NTT) multiplication butterfly unit. By using the operands merging method and a fast modulo method, the operands of the radix-16 units are reduced to 43.8%. The hardware architecture of the NTT radix-16 unit is designed and implemented. The proposed design has been synthesized using 90-nm process technology and Xilinx Kintex UltraScale+ FPGA. The results show that the maximum frequency of the circuit is 600 MHz at the cost of 243k gates and 144 mW and 430 MHz at the cost of 19.6k CLB LUTs, 11.5k CLB registers, and 1.2k CARRY8 respectively. The multiplier implementation results also show that the optimization methods improve the area requirements and performance. [ABSTRACT FROM AUTHOR]

An architecture of a matrix-vector multiplier (MVM) is devised, which is dedicated to MPEG-4 natural/synthetic video decoding. The MVM can perform the matrix-vector multiplication both in the inverse discrete cosine transform (IDCT) and in the geometrical transformation of three-dimensional computer graphics (3-D CG); or, specifically, it can achieve the multiplication of a 4×4 matrix by a four-tuple vector necessary in the one-dimensional IDCT for eight pixels and in the geometrical transformation for a point in a 3-D space. This paper describes a new architecture of this MVM and also shows the implementation result of a functional module composed of four MVMs with the use of 440-k transistors, which can operate at 20 MHz or less [ABSTRACT FROM PUBLISHER]