Search

Summary: One of the basic issues in orthogonal frequency‐division multiplexing (OFDM) frameworks is the peak‐to‐average power ratio (PAPR). There are several PAPR reduction methods available. The partial transmit sequence (PTS) technique is considered one of the superior techniques for overcoming this issue. In this study, an efficient VHSIC hardware description language VHDL implementation of the PTS design utilising roundabout circular shifting CS was planned. The proposed structured method was designed as a real‐time prototype circuit over a field programmable gate array (FPGA) utilising the VHDL language. The implementation results of the prototype circuit in terms of the resources used in the FPGA using the Xilinx synthesis tool on the Virtex‐5 board for SISO, 2 × 2 MIMO and 4 × 4 MIMO models for N‐IFFT 64 and 256 points are presented. The structured framework effectively combined to be a compact framework with low intricacy and high speed. Testing of the implemented circuit verified its functionality. A comparison of our proposed CS‐PTS scheme with previously used PTS schemes, such as the subblock scheme, showed that our proposed method is superior in terms of hardware complexity reduction. [ABSTRACT FROM AUTHOR]

This paper deals with development of an n-bit binary to decimal conversion, decimal to n bit binary conversion and decimal to IEEE-754 conversion for floating point arithmetic logic unit (FPALU) using VHDL. Normally most of the industries now a days are using either 4-bit conversion of ALU or 8-bit conversions of ALU, so we have generalized this, thus we need not to worry about the bit size of conversion of ALU. It has solved all the problems of 4-bit, 8-bit, 16-bit conversions of ALU's and so on. Hence, we have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task of development of conversions processes of ALU. [ABSTRACT FROM AUTHOR]

This paper describes the architecture design of novel massively parallel self-organizing map (SOM) neural networks. The proposed architecture, referred to as the planar SOM (PSOM), is described as a soft IP core synthesized in VHDL. The SOM neural network's size and the input data vectors' dimension are adjustable parameters. In this work, several SOM architectures are synthesized and their performance is evaluated for Xilinx Virtex-7 FPGAs. The presented hardware architecture allows online learning and can be easily adapted to a large variety of SOM topologies without a considerable design effort. A 1 6 × 1 6 SOM hardware is validated through the FPGA implementation and its performances with an estimated working frequency of 297 MHz for a 23-element input vector will reach 21,970 MCUPS in the learning phase and 35,902 MCPS in the recall one. [ABSTRACT FROM AUTHOR]

Simulation-based fault injection is a well-known technique to assess the dependability of hardware designs specified using hardware description languages (HDL). Although logic faults are usually introduced in models defined at the register transfer level (RTL), most accurate results can be obtained by considering implementation-level ones, which reflect the actual structure and timing of the circuit. These models consist of a list of interconnected technology-specific components (macrocells), provided by vendors and annotated with post-place-and-route delays. Macrocells described in the very high speed integrated circuit HDL (VHDL) should also comply with the VHDL initiative towards application specific integrated circuit libraries (VITAL) standard to be interoperable across standard simulators. However, the rigid architecture imposed by VITAL makes that fault injection procedures applied at RTL cannot be used straightforwardly. This work identifies a set of generic operations on VITAL-compliant macrocells that are later used to define how to accurately simulate the effects of common logic fault models. The generality of this proposal is supported by the definition of a platform-specific fault procedure based on these operations. Three embedded processors, implemented using the Xilinx's toolchain and SIMPRIM library of macrocells, are considered as a case study, which exposes the gap existing between the robustness assessment at both RTL and implementation-level. [ABSTRACT FROM AUTHOR]

The paper proposes a novel formal verification method of reconfigurable modules implemented in FPGA devices. The modules are specified by Petri nets and can be exchanged in the already implemented and running system using dynamic partial reconfiguration. The model checking technique is used together with the abstract rule-based logical model to verify whether the new modules still satisfy the global requirements for the whole control system. The additional advantage of using the rule-based logical model is the possibility to automatically generate the VHDL code, hence the final implementation reflects the already verified specification. It allows to ensure high quality of the released product and eliminates errors related to hand-code writing. A case study is presented to illustrate the approach, as well as some experimental results. [ABSTRACT FROM AUTHOR]

An improved method is proposed in this design to reduce the phase jitter after the synchronization or the random noise induced phase jitter in a bit synchronization clock extraction circuit. By using a newly added digital filter between the phase detector and the controller, the phase difference pulses from the phase detector are counted and processed, before being transmitted to the controller for adjusting the phase of the output clock. The design is completed by using FPGA chip and VHDL hardware description language and performs the simulation verification on Quartus II. The results show that the improved system performs the accurate extraction of bit synchronized clock, reduces the phase jitter problem, improves the system running efficiency and the ability of anti-interference, and guarantees the synchronization performance of the digital communication system. [ABSTRACT FROM AUTHOR]

This paper represents the review of VHDL which is a hardware description language that can be used to model a digital system at many level of abstraction. It is contemporary as it incorporates the popular and widely used IEEE. STD_LOGIC_1164 package. This language not only defines the syntax but also defines very clear simulation semantic for each language construct. The look is described by abstract interpretation of a static analysis for the popular hardware language VHDL. From a VHDL description, the analysis computes a superset of the state accessible throughout any simulation run. This information is beneficial within the validation of safety properties of hardware elements. The development of the analysis relies on the formal definition of linguistics for VHDL. Soundness with relevance this linguistics is shown. Varied techniques permit a compromise between the specified accuracy and therefore the value of the ultimate algorithmic rule. [ABSTRACT FROM AUTHOR]

This paper continues the study of high quality test derivation for verifying digital components which are used in various physical systems; those are sensors, data transfer components, etc. We have used logic circuits b01-b010 of the package of ITC’99 benchmarks (Second Release) for experimental evaluation which as stated before, describe digital components of physical systems designed for various applications. Test sequences are derived for detecting the most known faults of the reference logic circuit using three different approaches to test derivation. Three widely used fault types such as stuck-at-faults, bridges, and faults which slightly modify the behavior of one gate are considered as possible faults of the reference behavior. The most interesting test sequences are short test sequences that can provide appropriate guarantees after testing, and thus, we experimentally study various approaches to the derivation of the so-called complete test suites which detect all fault types. In the first series of experiments, we compare two approaches for deriving complete test suites. In the first approach, a shortest test sequence is derived for testing each fault. In the second approach, a test sequence is pseudo-randomly generated by the use of an appropriate software for logic synthesis and verification (ABC system in our study) and thus, can be longer. However, after deleting sequences detecting the same set of faults, a test suite returned by the second approach is shorter. The latter underlines the fact that in many cases it is useless to spend ‘time and efforts’ for deriving a shortest distinguishing sequence; it is better to use the test minimization afterwards. The performed experiments also show that the use of only randomly generated test sequences is not very efficient since such sequences do not detect all the faults of any type. After reaching the fault coverage around 70%, saturation is observed, and the fault coverage cannot be increased anymore. For deriving high quality short test suites, the approach that is the combination of randomly generated sequences together with sequences which are aimed to detect faults not detected by random tests, allows to reach the good fault coverage using shortest test sequences. [ABSTRACT FROM AUTHOR]

In this paper a reconfigurable FPGA implementation for the maximum power point tracking (MPPT) in photovoltaic systems (PV) is presented. The proposed MPPT controller is based on fuzzy logic and operates under variable irradiance and temperature conditions. The fuzzy controller is developed at first using matlab Simulink model. It includes the PV panel, boost converter and MPPT controller. The tested controller is implemented in VHDL. The pro- posed design has the advantage of high flexibility and re-configurability, while maintaining faster response than other hardware implementations. The design has also the advantage of low cost and power consumption. To validate the design, simulation comparison between the Matlab Simulink and VHDL results are provided. The VHDL controller is implemented and synthesized on Spartan 6 field programmable gate arrays FPGA. A graphical user interface GUI is implemented to help the system designer reconfigure the fuzzy controller. [ABSTRACT FROM AUTHOR]

High-performance embedded architectures typically contain many stand-alone blocks which communicate and exchange data; additionally a high-speed network interface is usually needed at the boundary of the system. The software-based data processing is typically slow which leads to a need for hardware accelerated approaches. The problem is getting harder if the supported protocol stack is rapidly changing. Such problem can be effectively solved by the Field Programmable Gate Arrays and high-level synthesis which together provide a high degree of generality. This approach has several advantages like fast development or possibility to enable the area of packet-oriented communication to domain oriented experts. However, the typical disadvantage of this approach is the insufficient performance of generated system from a high-level description. This can be a serious problem in the case of a system which is required to process data at high packet rates. This work presents a generator of high-speed input (Parser) and output (Deparser) network blocks from the P4 language which is designed for the description of modern packet processing devices. The tool converts a P4 description to a synthesizable VHDL code suitable for the FPGA implementation. We present design, analysis and experimental results of our generator. Our results show that the generated circuits are able to process 100 Gbps traffic with fairly complex protocol structure at line rate on Xilinx Virtex-7 XCVH580T FPGA. The approach can be used not only in networking devices but also in other applications like packet processing engines in embedded cores because the P4 language is device and protocol independent. [ABSTRACT FROM AUTHOR]

Analog components are fundamental blocks of smart systems, as they allow a tight interaction with the environment, in terms of both sensing/actuation and communication. This impacts on the design of the overall system, and mainly on the validation phase, that thus requires the joint simulation of digital and analog aspects. In this scenario, this paper proposes the automatic conversion of analog models to C++-based languages, to remove the overhead of co-simulation with traditional virtual platform tools. The proposed methodology allows to convert a given analog description to either: 1) a fully equivalent description or 2) an abstract representation for faster simulation which models only the aspects of interest. Effectiveness and correctness have been proved on a number of case studies that highlight the effectiveness and potentiality of the proposed methodology. [ABSTRACT FROM AUTHOR]

In this paper, we synthesize a Breakout game code which runs on an FPGA development and education board. For this purpose, an original Breakout game code that runs exclusively on the FPGA board is designed in VHDL hardware description language. The strength of this design is that the code does not require any SRAM modules for storage which eliminates the memory requirements and results in faster operation. Altera DE0 development and education board is used for the implementation. However, since only the standard VHDL functions is used in the code, it can run on any other FPGA boards. [ABSTRACT FROM AUTHOR]

This work proposes a methodology to synthesize arithmetic operations maximizing the reuse of the DSP48E1 blocks presented in the new reconfigurable architectures. The input for DSPONE48 is a VHDL code without any reference to the FPGA hardware resources. This input code is modified, so the synthesis tool is able to implement it with DSP slices. In order to achieve this objective we use DSP block instantiation templates and we encourage the use of SIMD mode within the DSP block. This methodology replaces automatically the most common arithmetic operations by their equivalents on DSP slices. The methodology guarantees that the new code preserves the functionality and the number of execution cycles of the original design. Experimental results, on a Virtex 7 FPGA, show that the designs obtained by DSPONE48 use less DSPs than those obtained automatically by Xilinx ISE or Vivado. Moreover, these designs have lower area and higher frequency. [ABSTRACT FROM AUTHOR]

Introduction: This article presents a finite field multiplier (GF) model, studying the generalized architecture of the LFSR component (linear regression displacement records), in order to generate a concurrent description. Concepts of structural analysis, description of parameterized components and mathematical treatment of signals have been applied. Method: The design was performed by the tabulation of the terms in the variable time function and the position in the circuit, the components of the modular reduction, thus creating an array of combined operations. This model was described in VHDL, for testing behavior and optimization of hardware. Results: The research established the equations for the implementation of the VHDL model in its generic expression with operator concatenation for the hardware configuration. It is estimated that the hardware resources, a level of logical operators, obtained a 7.89% savings in the energy consumption associated with the signal in the multiplier design by the proposed optimization technique. Conclusions: The model simplified the description of parallel circuits, high performance from a mathematical model approach to hardware description. The proposed method contributes to the field of optimization in the efficient modeling of advanced logic systems, which can be extrapolated to more complex components. [ABSTRACT FROM AUTHOR]

Rapid growth in the number of Intellectual Property (IP) cores in System-on-Chip (SoC) resulted in the need for effective and scalable interconnect scheme for system components – Network-on-Chip (NoC). Router is a key component in an NoC design that impacts the overall area utilization. It is crucial to evaluate the area efficiency of NoC routers. In this paper, we evaluate and compare two recent NoC routers for Field Programmable Gated Arrays (FPGAs). The first one is generated using the automated NoC synthesis tool CONfigurable NEtwork Creation Tool (CONNECT). The second one is an NoC router manually designed using VHDL and synthesized Altera Quartus II CAD tool. Three NoC topologies namely ring, mesh and torus are used for evaluating the two routers based on area utilization metric. The routers are evaluated by varying the node sizes from 4 to 16 for each topology. For smaller NoC topologies, CONNECT router uses less area but as the NoC size increases manual router design provides up to 85% reduction in area utilization. The results presented in this paper will be useful to designers interested in NoC implementation on FPGAs. [ABSTRACT FROM AUTHOR]

Telecommunication standards are documents that contain consolidated knowledge about communication systems and implementation best practices. They are created based on long consensus processes in order to meet practical constraints. This article describes how the DVB-S2 standard is used in the electrical engineering curricula at KU Leuven within a design and implementation course called EAGLE. The goal of the course is to teach third-year Bachelor students how to apply the abstract knowledge gathered in the theoretical courses (control theory, communication theory, software, and hardware) to the design of a complex and real engineering project. Based on their progress during the academic year, we illustrate how standards can be used to teach a broad skill set and act as an accelerator to abstract system implementation complexity. We give an overview of the objectives of the EAGLE project and the relevance of the DVB-S2 standard, the design and implementation task that the students need to accomplish, and how they finally learn to master the complexity of a real communication standard, VHDL coding, and system verification and integration. [ABSTRACT FROM PUBLISHER]

A compact solution for onboard tolerant image compression is studied and the effectiveness of the soft-error mitigation strategy is evaluated by using a simulation-based susceptibility analysis method. The low complexity JPEG-LS compression algorithm allows considering medium-size flash or antifuse COTS FPGAs as a target for future use in small satellites. Fault mitigation methods, like Triple Modular Redundancy and Hamming code, with scrubbing to mitigate residual error accumulation, were selected taking into account operation in LEO space missions. The results point out the viability of implementing a tolerant image compression system in a single device with two orders-of-magnitude reduction in the susceptibility estimate based on a non-tolerant reference VHDL code. The effectiveness of the mitigation strategy, the injection model accuracy and possible improvements are discussed herein. [ABSTRACT FROM AUTHOR]

The article proposes a novel architecture to perform modular multiplication in the Residue Number System (RNS) by using sum of residues. Topics include the highly parallel architecture implemented using (VHSIC Hardware Description Language (VHDL) and verified by extensive simulations in ModelSim SE simulation and the high scalability and flexibility of the proposed architecture allow it to be used for a wide range of high-speed applications.

This paper explores neuromorphic approach capabilities applied to real-time speech processing. A spiking recognition neural network composed of three types of neurons is proposed. These neurons are based on an integrative and fire model and are capable of recognizing auditory frequency patterns, such as vowel phonemes; words are recognized as sequences of vowel phonemes. For demonstrating real-time operation, a complete spiking recognition neural network has been described in VHDL for detecting certain Spanish words, and it has been tested in a FPGA platform. This is a stand-alone and fully hardware system that allows to embed it in a mobile system. To stimulate the network, a spiking digital-filter-based cochlea has been implemented in VHDL. In the implementation, an Address Event Representation (AER) is used for transmitting information between neurons. [ABSTRACT FROM AUTHOR]

Artificial neural networks (ANNs) are implemented in hardware when software implementations are inadequate in terms of performance. Implementing an ANN as hardware without using design automation tools is a time consuming process. On the other hand, this process can be automated using pre-designed neurons. Thus, in this work, several artificial neural cells were designed and implemented to form a library of neurons for rapid realization of ANNs on FPGA-based embedded systems. The library contains a total of 60 different neurons, two-, four- and six-input biased and non-biased, with each having 10 different activation functions. The neurons are highly pipelined and were designed to be connected to each other like Lego pieces. Chip statistics of the neurons showed that depending on the type of the neuron, about 25 selected neurons can be fit in to the smallest Virtex-6 chip and an ANN formed using the neurons can be clocked up to 576.89MHz. ANN based Rössler system was constructed to show the effectiveness of using neurons in rapid realization of ANNs on embedded systems. Our experiments with the neurons showed that using these neurons, ANNs can rapidly be implemented as hardware and design time can significantly be reduced. [ABSTRACT FROM AUTHOR]

Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors. [ABSTRACT FROM AUTHOR]

Time-domain induced polarization (TDIP) measurement is seriously affected by power line interference and other field noise. Moreover, existing TDIP instruments generally output only the apparent chargeability, without providing complete secondary field information. To increase the robustness of TDIP method against interference and obtain more detailed secondary field information, an improved dataprocessing algorithm is proposed here. This method includes an efficient digital notch filter which can effectively eliminate all the main components of the power line interference. Hardware model of this filter was constructed and Vhsic Hardware Description Language code for it was generated using Digital Signal Processor Builder. In addition, a time-location method was proposed to extract secondary field information in case of unexpected data loss or failure of the synchronous technologies. Finally, the validity and accuracy of the method and the notch filter were verified by using the Cole-Cole model implemented by SIMULINK software. Moreover, indoor and field tests confirmed the application effect of the algorithm in the fieldwork. [ABSTRACT FROM AUTHOR]

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper. [ABSTRACT FROM AUTHOR]

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources. [ABSTRACT FROM AUTHOR]

This paper presents a new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator. This system dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC’s sampling frequency to the input signal’s fundamental frequency with a few parts per million accuracy. The trade-off between straightforwardness and performance that motivated the choice of the ADC’s architecture are preliminary discussed. It particularly comes along with design considerations of an ultra-steep direct-form FIR that is optimised in terms of size and operating speed. Thanks to compact standard VHDL language description, the architecture of the proposed system is particularly suitable for application-specific integrated circuit (ASIC) implementation-oriented low-power and low-cost power meter applications. Field programmable gate array (FPGA) prototyping and experimental results validate the adjustable sampling frequency concept. They also show that the system can perform better in terms of implementation and power capabilities compared to dedicated IP resources. [ABSTRACT FROM AUTHOR]

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2(4.58 × 4.58 mm2with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock. [ABSTRACT FROM AUTHOR]

This paper presents a set of eight novel configurations for the design of single event soft error (SE) tolerant latches. Each latch uses a three-transistor building block called 1P-2N and its complementary block 2P-1N. It is shown that all proposed latches have better soft error rate (SER) performance as compared to the SE-tolerant latches reported till date. It is also shown that the proposed configurations provide a more relaxed tradeoff between SER and other specifications mainly delay, power dissipation and area. RTL implementation of a proposed latch is also shown to verify the behaviour subjected to the transient faults. The benefit of implementing a SE tolerant circuit in VHDL language is the feasibility to exhaustively check the immunity of the circuit against transient faults at every sensitive node by just writing simple boolean expressions of each element in the circuit. The proposed configurations and a few selected reported configurations have been also designed, laid out and post layout extracted in 90 nm CMOS logic technology. Post layout simulations have been performed on all proposed latch configurations with clock frequency of 500 MHz and performance comparison results are presented. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a crypto channel coder with very low hardware complexity and high security for securing communication in resource-constrained applications such as Wireless Sensor Networks (WSNs). The integrated secure channel coder system is proposed as a modification of the Rao–Nam (RN) scheme by embedding security in a structured Low-Density Parity-Check (LDPC) code. A novel stream ciphering method based on the Linear Feedback Shift Register (LFSR) with high throughput is incorporated to generate random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with simple hardware. An efficient design method to vary the encryption matrix and the intentional error vector with each message block provides high degrees of freedom for an intended receiver without compromising hardware simplicity. Prototypes of the proposed encoder architecture with both (28, 14) and (248, 124) Quasi-Cyclic (QC) LDPC codes have been implemented on Xilinx Field Programmable Gate Array (FPGA) Spartan 3E kit using Very High Speed Integrated Circuit Description Language (VHDL). Analytical and synthesis results show that this scheme is highly suitable for resource-constrained applications such as wireless sensor networks due to its low hardware complexity and high security. [ABSTRACT FROM AUTHOR]

The electric powered aircraft's secondary system has advantages of cost and efficiency when compared to the conventional aircraft power system. However, the advantages come at the cost of increased design and analysis complexity. To support computer based modeling and simulation of aircraft electrical system, this paper presents two libraries in ANSYS Simplorer. At system level, a VHDL-AMS based behavioral aircraft electrical library is developed to provide a convenient way for designers to prototype and analyze the electric power distribution systems. The library components are developed as generic components, which can easily be reused and have the ability to be modified (with experimental data) to fit specific applications. Various subsystems of the aircraft electrical system are discussed in combination with the multilevel components provided by the library. At device level, a library of detailed power semiconductor models is provided for accurate simulation of power electronics. Using the device characterization tool in Simplorer, parameters of these models can be extracted from electrical and thermal characteristics given in manufacturers' datasheet. Finally, a simplified aircraft electric power generation and distribution system with multiple control loops is discussed to demonstrate the usage of the library. [ABSTRACT FROM AUTHOR]

As scaling is more and more aggressive, intermittent faults are increasing their importance in current deep submicron complementary metal-oxide-semiconductor (CMOS) technologies. This work shows the dependability assessment of a fault-tolerant computer system against intermittent faults. The applied methodology lies in VHDL-based fault injection, which allows the assessment in early design phases, together with a high level of observability and controllability. The evaluated system is a duplex microcontroller system with cold stand-by sparing. A wide set of intermittent fault models have been injected, and from the simulation traces, coverages and latencies have been measured. Markov models for this system have been generated and some dependability functions, such as reliability and safety, have been calculated. From these results, some enhancements of detection and recovery mechanisms have been suggested. The methodology presented is general to any fault-tolerant computer system. [ABSTRACT FROM AUTHOR]

Autonomous measurement units are indispensable for the development of the smart grid in order to get faster processing responses, stability, and to provide the user with information regarding power quality (losses, harmonics, outages, steady-state and transient events). In this paper, the development of a novel FPGA-based real-time analyzer is presented. The signal processing nucleus is based on higher-order statistics, introducing the Spectral Kurtosis as an online assessment. Indeed, this fourth-order spectrum enhances non-Gaussian behavior in very unfavorable noise conditions. In the Power Quality assessment frame, the outline of this spectrum can be used to reveal the presence of underlying electrical perturbations. In this paper it is presented an autonomous analyzer that uses the Spectral Kurtosis to detect the presence of low level harmonics. These harmonics are difficult to detect using conventional techniques and can generate problems in power distribution when they are associated to a resonant response in the powered load. The proposed system has been described in synthesizable VHDL and performs an indirect estimator of a poly-spectrum slide, based on the FFT. This synthesizable description has been implemented using a low cost FPGA, enabling a continuous monitoring of the power signal (without dead times) with a high oversampling rate. The proposed solution has been conceived to be introduced in smart grids with high penetration of Distributed Energy Resources (DER). [ABSTRACT FROM AUTHOR]

The paper presents a new efficient H.264/AVC4 x 4 intraprediction scheme. The new prediction scheme is based on the best prediction matrix mode. The main idea behind the new prediction scheme is to combine the most usable intraprediction modes, {vertical - horizontal - DC}, into a new efficient prediction mode. The new prediction scheme is implemented using VHDL and hence it uses the full advantages of inherent parallelism in the hardware. We evaluate the performance of this prediction scheme in terms of compression ratio, peak signal to noise ratio, and bit rate using seven video sequences. Moreover, we analyze the power consumption, the delay, and FPGA area utilization of the implemented H.264 encoder after utilizing the new prediction scheme. The performance measures as well as the area and power consumption are compared to other best known prediction algorithms. [ABSTRACT FROM AUTHOR]

The description of the program memory models with the ordered access is presented in the article. Memory is described in VHDL language. The synthesis of memory was implemented in programmable logic devices using modern technologies and design tools. [ABSTRACT FROM AUTHOR]

The CoMet approach on designing application specific instruction set processors (ASIPs) is targeting a non-cyclic design space exploration (DSE). The design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step, the intermediate code can be simulated and profiled. Based on that profiling information, it can be further transformed to an optimized or refined intermediate code. The whole transformation process is implemented in a GUI-based design tool, whose main component is a configurable simulator for intermediate codes. It will be shown how the configurable intermediate code simulator is used and how the intermediate code transformation and the VHDL generation of the ASIP model will work in the CoMet tool. [ABSTRACT FROM AUTHOR]

This paper proposes hardware implementation of evolutionary algorithms using dynamic reconfiguration technology. In this paper two types of dynamic reconfiguration for evolutionary algorithm are introduced. The processor was designed by using VHDL and the circuit was simulated. The effectiveness of the proposal processor was confirmed. [ABSTRACT FROM AUTHOR]

SUMMARY Inverse filters are used in many fields, including audio circuits, metal and optical telecom line equalization, and wireless equalization. The purpose of such filters is to compensate for distortion in the signal caused by the transmission medium. Design methods for an inverse filter using an IIR filter, FFT/IFFT, and an adaptive FIR filter are available. However, an IIR filter has some problems as regards stability. The FFT/IFFT method requires significant calculation and the adaptive FIR filter needs substantial time. This paper proposes a new method of generating the FIR inverse filter coefficients through serial calculations of the impulse response and its expected value. At first, all coefficients of the FIR filter except the first are set to zero. When an input of the impulse response data XN is applied to the filter, the temporal output of the FIR filter WN is compared to the expectation value EN, and the FIR inverse filter coefficients gN are calculated using [ABSTRACT FROM AUTHOR]

SUMMARY There are many subjects that relate to electrical and electronics circuits. Practical education for those subjects usually introduce hardware description languages such as VHDL and Verilog HDL, but it is not easy to understand the relation to basic logic circuits drawn as circuit diagrams. In this paper, we introduce practical education in which basic digital circuits are drawn, simulated, and executed on an experiment board with a programmable logic device, and then newly designed 2-bit CPUs which use those basic digital circuits are drawn, simulated, and executed on the experiment board. Students can learn basic digital circuits themselves, and their operations which relate to each other in the newly designed 2-bit CPU. The effectiveness of the newly introduced practical education is confirmed by tests and a questionnaire survey. [ABSTRACT FROM AUTHOR]

Data security becomes one of the things that need to be considered. The Sum of Product (SOP) Encryption is one of simple algorithm. The SOP encryption is not a public-key system to encrypt data. it is almost unbreakable through brute force method and vulnerable to attack because the encryption models have a fixed pattern. However, this drawback can be avoided through the compression process to remove the pattern file. SOP encryption algorithm can use a Boolean algebra combination functions such as AND gate and OR gate. Simple algorithm in hardware language VHSIC Hardware Description Language (VHDL) is on data bits level. The purpose of this research is implementation of image encryption algorithm to produce a quick image encryption system. From result test, the image processing time without encryption average 4.999ns/px and 13.51ns/px with encryption. [ABSTRACT FROM AUTHOR]

Square root is one of the mathematical operations which are widely used in digital signal processing. Its implementation on hardware such as FPGA will provide several advantages compare to the performance offered in software. There are several algorithms which can be utilized for this calculation, but they are difficult to be implemented in FPGA. This paper presents a model of FPGA based square root calculator, which requires very low resources usage, thus occupying very low area of FPGA. The model is designed to suit the needs of medium-speed and low-speed applications which don't need very high processing speed, while optimizing the number of resources utilized. The modified non-restoring algorithm is used in this design to compute the square root. The design is coded in RTL VHDL, and implemented in Altera DE2-board for hardware validation. The implementation produced very precise square root calculation, with low latency computation and low area consumption, for various input data width tested. [ABSTRACT FROM AUTHOR]

In modern computing technique, calculation of leading zeros in a data represented as strings of digits is used very often. Those techniques require high speed of the circuit, as well as its fast design. In this paper we propose a design of such a counter, which is applicable to data length of w = 4 j bits, for 4 < j ≤ 8. With this solution it is also possible to process longer data, since the suggested technique offers a good modularity. This is very important, considering the current technology scaling trends. In this paper, a delay behavior of the proposed circuit has also been investigated using equations and VHDL simulation based worst-case delay estimation method. The results show a significant improvement of the circuit speed, compared to the known solutions. [ABSTRACT FROM AUTHOR]

One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on the batched MIT iLab Architecture. With a hardware system under test designed around an Altera EP2C20F484 field-programmable gate array (FPGA), the lab makes it possible for students to implement finite-state machines on a field-programmable device using VHDL. A study was carried out to evaluate the lab. Study results indicated that the Advanced Digital Lab is an effective pedagogical tool. Some observations drawn from the results of the study are also discussed; these may have far-reaching implications for the argument about the effectiveness of the general class of remote laboratories. An important contribution of this paper is that it provides a template for the proper evaluation of remote laboratories along multiple dimensions, particularly those of pedagogy, logistics, and cost. [ABSTRACT FROM PUBLISHER]

An in-house, Advanced Telecom Computing Architecture (ATCA) based control and data acquisition (C&DAQ) subsystem has been developed at Instituto de Plasmas e Fusão Nuclear (IPFN), aiming for compliance with the ITER Fast Plant System Controller (FPSC). Timing and synchronization for the ATCA modules connects to ITER Control, Data Access and Communication (CODAC) through the Timing Communication Network (TCN), which uses IEEE 1588-2008 Precision Time Protocol (PTP) to synchronize devices to a Grand Master Clock (GMC). The TCN infrastructure was tested for an RMS jitter under the limit of 50 ns. Therefore, IPFN's hardware, namely the ATCA-PTSW-AMC4 hub-module, which is in charge of timing and synchronization distribution for all subsystem endpoints, shall also perform within this jitter limit. This paper describes a relevant upgrade, applied to the ATCA-PTSW-AMC4 hardware, to comply with these requirements – in particular, the integration of an add-on module “RMC-TMG-1588” on its Rear Transition Module (RTM). This add-on is based on a commercial FPGA-based module from Trenz Electronic, using the ZHAW “PTP VHDL code for timestamping unit and clock”, which features clock offset and drift correction and hardware-assisted time stamping. The main advantage is that timestamps are generated closer to the Physical Layer, at the Gigabit Ethernet Media Independent Interface (GMII), avoiding the timing uncertainties accumulated through the upper layers. PTP code and user software run in a MicroBlaze™ soft-core CPU with Linux in the same FPGA, adding programmability and quick implementation of the desired features and upgrades. The paper briefly presents an overview of the ATCA C&DAQ, presenting the PTP and time stamping solution and how it was hardware-implemented, resulting in the RMC-TMG-1588 module. Finally it will describe the synchronization performance tests and results obtained at ITER site as well as indicating further developments to the system, in order to fulfil ITER's requirements. [ABSTRACT FROM AUTHOR]