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This paper presents the design of a 4-bit switched attenuator operating in the frequency range of DC to 8 GHz band. The attenuator is fabricated using a 28-nm bulk CMOS process for verification. The designed attenuator employs switched T-type and π-type structures, with a simplified π-type circuit to reduce size for the 0.5 dB bit. Additionally, an inductor is added between the 0.5 dB bit and the 1 dB bit to improve input and output matching. Measured input and output return loss in the frequency band of DC to 8 GHz is greater than 11.45 dB, insertion loss is less than 2.69 dB, the measured RMS gain error is less than 0.64 dB, and the RMS phase error is less than 1.42°. The actual size of the attenuator, excluding the RF and DC pads, is 0.236×0.146 mm². [ABSTRACT FROM AUTHOR]

This paper discusses the design of a driver amplifier operating in the Ku-band using a 130 nm SOI CMOS process. The amplifier consists of two stages: a cascode amplifier in the first stage for high gain, and a CS amplifier in the final stage for high OP1dB. In the cascode amplifier structure of the first stage, a series inductor is added between the CS and CG amplifiers to simplify input matching. This modification shifts the maximum Gm point of the cascode amplifier to a lower frequency, resulting in a high gain at the target frequency. The measured amplifier achieves a maximum gain of 13.7 dB and an OP1dB of −0.3 dBm. It consumes 12 mW of power at 1.2 V and occupies an area of 0.188 mm², excluding the DC and RF pads. [ABSTRACT FROM AUTHOR]

This paper presents a 6-bit phase shifter operating in the 11∼13 GHz band. The designed phase shifter is fabricated using a 130-nm SOI process to validate its performance. For fine phase adjustment, the phase shifter employs six single-bit phase shifters ranging from 5.625° to 180°. To expand the bandwidth and minimize the phase and gain errors, the 90° bit uses low-pass and high-pass filters. Additionally, the 180° bit uses a transformer-based switch structure. The fabricated phase shifter measures 0.87×0.4 mm², with a return loss of more than 10 dB, an average insertion loss of 6.41 dB, RMS phase errors ranging from 3.19° to 4.13°, and RMS gain errors between 0.52 dB and 0.56 dB. [ABSTRACT FROM AUTHOR]

This study deals with a 5-bit attenuator operating in the 10∼15 GHz band. This attenuator actively uses transistors with a large effective width to reduce insertion loss, reduces process variation with an attenuator using a 'π-type structure with removed tail resistance,' and minimizes size and insertion loss using a 'simplified T-type attenuator' that short circuits the RF power input and output. This 5-bit attenuator has a core size of 0.1 mm×0.3 mm, minimum return loss of 14.5 dB, maximum insertion loss of 1.86 dB, maximum RMS (root mean square) phase error of 3.37°, and an RMS gain error of 0.24 dB. [ABSTRACT FROM AUTHOR]

In the front-end receiver of a GPS, the noise figure is extremely important and requires a low-noise amplifier with a low noise figure and small size. This study aims to investigate the design of an L-band low-noise amplifier using the 0.18-μm CMOS process. For low-noise characteristics, the input series inductor was removed, the effective width of the transistor was increased to achieve impedance matching, and the inductors requiring high inductance had laminated structures with small chip sizes. The low-noise amplifier achieved a noise figure of less than 2.5 dB, a return loss of more than 10.57 dB, a peak gain of 17.3 dB, and a size of 1.05 mm×0.78 mm in frequency from 1.4∼2.1 GHz. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of an LO chain implemented using the CMOS 65 nm bulk process. The LO chain was fabricated for driving the short-range radar IQ mixer in the 77∼81 GHz band. The LO chain comprised a poly phase filter (PPF), driver amplifiers to compensate for PPF losses, and a 3-bit 7-dB attenuator to ensure the appropriate power conditions. Measurement results indicated that the maximum gain within the target band was 8 dB, and the gain and phase difference between the IQ outputs were 0.5 dB and 74°, respectively. The LO chain consumed 74 mW of power at 1 V, and the size of the fabricated chip was 1.027×0.45 mm², including RF and DC pads. [ABSTRACT FROM AUTHOR]

This paper discusses the design of a 4.4∼5.0 GHz low-noise amplifier (LNA) using a 0.5-μm GaAs pHEMT process. The transistor size was optimized to address the mismatch between optimal noise and input impedance owing to the unique noise sources of the transistor and parasitic characteristics, achieving a low noise figure with high input and noise optimal impedance matching without additional inter-stage loss components. The designed low-noise amplifier consumed 48 mW of power in the 4.4∼5.0 GHz range, demonstrating more than 23 dB of gain and a low noise figure of less than 0.9 dB. The size of the fabricated circuit was 1.8×1.4 mm². [ABSTRACT FROM AUTHOR]

This paper discusses the design of a 3.5-GHz band Doherty power amplifier using a 0.5-μm GaAs process. The design was optimized through load-pull simulations, employing the second harmonic trap filter at the output of the peaking amplifier to maintain high linearity. Measurement results of the fabricated power amplifier showed a maximum saturated power of 27.8 dBm and power-added efficiency (PAE) of 34.3 % in the 3.5 GHz band. Additionally, with a 5G NR 64-QAM 100-MHz modulated signal, it achieved a linear output power of 22 dBm with an EVM of 5.6 % and a linear output power added efficiency of 19.8 %. [ABSTRACT FROM AUTHOR]

This paper presents the design of a driving amplifier intended for use in W-band RFICs. The amplifier adopts a differential two-stage common-source configuration to ensure robust output power. Furthermore, it has been enhanced through the incorporation of a neutralized capacitor to improve stability and maximize gain. The driving amplifier was fabricated using a 65-nm bulk CMOS process for validation. The measured performance of the amplifier demonstrated characteristics, including an input/output return loss exceeding 10 dB and a peak gain of 14.1 dB, achieved within the frequency range of 77∼88 GHz. The power consumption of the amplifier was only 34 mW at a voltage of 1 V, and it exhibited an OP1dB of 3.8 dBm. The size of the driving amplifier, excluding DC and RF pads, was 0.401×0.14 mm². [ABSTRACT FROM AUTHOR]

This paper presents the design and fabrication of a rectenna that receives 2.45 GHz RF signals and converts them into DC power. The rectenna comprises a patch antenna, matching network, and rectifier. It was manufactured and measured using a 0.76-mm thick RF-35A2 board. The matching network was implemented using transmission lines and open stubs and designed to stably convert the RF signal into a fixed DC voltage by employing parallel inductors. The measured rectenna achieved a maximum RF–DC conversion efficiency of 38 % at 2.3-dBm input power and a 1.5-kΩ load. When used in conjunction with the fabricated patch antenna, it transmitted 1.8 V of power at 36 mW into a 90-Ω load at a distance of 10 cm. [ABSTRACT FROM AUTHOR]

This paper discusses the design of a W-band down-conversion mixer, fabricated using a 65-nm bulk CMOS process. The mixer employs a passive double-balanced structure, resulting in no power consumption. It includes LC matching circuits for RF and LO input voltage amplification via resonance and RC filter circuits for precise IF signal separation. The manufactured mixer measured 0.614×0.25 mm², including RF and DC pads. Measurement results showed input return losses of more than 8 dB, a maximum conversion gain of －5.5 dB, and RF-IF isolation of 37.3 dB at 77–81 GHz. [ABSTRACT FROM AUTHOR]

This paper presents the design of W-band Wilkinson power divider using 65 nm bulk CMOS process. In this design, the quarter-wavelength (λ/4) transmission line was replaced with a lumped element, and a CRC structure was applied to the isolation network circuit. In addition, a metal wall was installed between the two output lines to enhance isolation. This power divider had a maximum insertion loss of 1.93 dB and a minimum isolation of 13.3 dB in the 75~110 GHz band. The return loss was more than 7.2 dB, and the size of the core was 0.2×0.12 mm². [ABSTRACT FROM AUTHOR]

This paper presents a 6-bit phase shifter designed and fabricated using a 150-nm GaN HEMT process. The designed phase shifter operates in the n257 (26.5-29.5 GHz) band of the 5G NR standard, and the structure of a switched-filter phase shifter is used. The designed phase shifter connects six single-bit phase shifters in series from 180° to 5.625° to change the phase within the phase range of 360°. An LCL low-pass T-type filter is used to reduce the size of the filter element. The 180° phase shifter mixes low-pass and high-pass T-type filters. The fabricated phase shifter has an average insertion loss of 8.45 dB and an RMS phase error of less than 4.54° at 26.5-29.5 GHz. Herein, the phase shifter had a low insertion loss per bit and a small RMS phase error. [ABSTRACT FROM AUTHOR]

This study presents a Q-band wideband low-noise amplifier (LNA), which is implemented and verified using a 65-nm bulk CMOS process, for millimeter-wave applications. The proposed low-noise amplifier uses a transformer structure at the input stage to obtain broadband input-matching characteristics. Under 1-V supply voltage, the proto-type LNA achieves a simulated peak gain of 22.74 dB with gain variation of ±0.37 dB in frequency band. The simulated noise figure (NF) was 3.27 dB at 40 GHz while consuming 17 mW. The core occupies an area of 0.13 mm². [ABSTRACT FROM AUTHOR]

This article presents the design of a W-band wideband low-noise amplifier (LNA) using a 65-nm bulk complementary metal-oxide semiconductor process. A negative feedback transformer is used as an input matching network for wideband matching of the LNA. The transformer is composed of the input shunt inductor and the source inductor of the transistor. The transformer is optimized to achieve low-noise performance and to prevent gain degradation while achieving wideband matching. The LNA has a size of 0.45×0.53 mm, including radio frequency and direct-current pads. As a result of the design, the return loss is more than 10 dB in the 75-85 GHz band, with a peak gain of 17 dB and a minimum noise figure of 4.8 dB. [ABSTRACT FROM AUTHOR]

This study entailed the development of a K-Band power amplifier (PA). The proposed PA was implemented and verified using a 65-nm bulk CMOS process. The PA was designed with two stages to obtain sufficient gain in the K band. The PA had a chip area of 0.93×0.47 mm² including RF and DC pads. The manufactured power amplifier design had a maximum saturation power of 22.4∼22.7 dBm in the 19–21 GHz frequency band, and a power added efficiency (PAE) of 39 %∼40 %. In the two-tone simulation results, the linear power and efficiency levels satisfying third-order inter-modulation distortion (IMD3) below −30 dBc were confirmed to be 16∼17 dBm and 24%∼26 % in the 19∼21 GHz frequency band, respectively. [ABSTRACT FROM AUTHOR]

This study entailed the design of a K-band low noise amplifier (LNA) by using the 65-nm bulk CMOS process. In the designed low noise amplifier, a large transistor was used to reduce the size of the lossy gate series inductor, resulting in low noise and high gain. In addition, the source generation and shunt inductors were used at the input stage to enable simultaneous noise and input matching. The LNA had a size of 0.67×0.39 mm² including RF and DC pads. A peak gain of 19.5 dB and a minimum noise figure of 2.31 dB were achieved. Owing to the design, the input and output return loss was more than 10 dB at 17∼23 GHz. [ABSTRACT FROM AUTHOR]

Diplexers are one of the key devices required to separate uplink and downlink signals in transceivers using a single grounded antenna. This study presents the design of an X-band diplexer for satellites. First, bandpass filters of the transmitter and receiver are designed. Next, an X-band diplexer is designed by combining the two bandpass filters. Simulation results show that the insertion loss is less than 0.75 dB and the return loss is more than 20 dB. Additionally, the channel isolation property is greater than 103 dB, thereby satisfying the requirements for diplexers. [ABSTRACT FROM AUTHOR]

This paper presents a W-band broadband low noise amplifier (LNA). The proposed LNA was designed and verified using a 100 nm GaAs pHEMT. To achieve broadband low noise and gain characteristics, peak gain distribution was employed. The LNA comprised four gain stages and a shunt inductor at the input stage to prevent the device damage. The LNA achieved a 16.2 dB gain and 5.5 dB noise figure in an area of 1.78×0.743 mm². [ABSTRACT FROM AUTHOR]

In this paper, we present a low noise amplifier with a merged duplexer. The input matching network of the electrical balance duplexer(EBD) and the low-noise amplifier were integrated to minimize input insertion loss in the RX path. The low noise amplifier was designed with a differential structure because its input matching network was integrated with the EBD. The first stage of the low-noise amplifier was designed with a common-source structure while considering noise characteristics. The second stage of the low-noise amplifier was designed with a cascode structure to minimize the effects of impedance mismatch and phase mismatch on the output balun. In addition, the interstage matching network was designed symmetrically using lumped elements while considering the mismatch. The low noise amplifier with a merged duplexer had a gain of over 18.04 dB at the RX path, a return loss of over 8.7 dB, an insertion loss of 4.3 dB at the TX path, a noise figure of 5.21 to 5.23 dB at the RX path in the frequency range of 14.3 to 15.9 GHz, and its chip size was 0.85⨯0.33 mm2. [ABSTRACT FROM AUTHOR]

A power amplifier for subgigahertz short-range wireless communication using 0.18-μm CMOS technology is presented. It is designed as a differential structure to form easily a virtual ground node, to increase output power, and to design a cascode structure to prevent breakdown. The transistor gate width was determined to maximize the output power and power-added efficiency(PAE), and the balun was optimized through electromagnetic simulation to minimize the loss caused by the matching network. This power amplifier had a gain of more than 49.5 dB, a saturation power of 26.7 dBm, a peak PAE of 20.7 % in the frequency range of 860 to 960 MHz, and a chip size of 2.14 mm2. [ABSTRACT FROM AUTHOR]