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This paper presents a low-noise 320 x 240 digital readout integrated circuit (ROIC) for SiGe microbolometers with a pitch size of 17 mu m. The ROIC architecture uses a column-shared capacitive transimpedance amplifier (CTIA) that senses the change in resistance of the SiGe microbolometers with respect to the column-shared reference microbolometer pixel. The output voltage of the CTIA is then digitized using a split-successive approximation register (SAR) analog-to-digital converter (ADC). Each 40 columns of the CTIA is connected to a SAR ADC with the help of a 40x1 MUX, which makes 8 parallel-operating ADCs in total. In this way, speed and power requirements of ADCs are relaxed. The offset calibration for the comparator, in the split-SAR ADC is designed using a novel two-step coarse and fine current adjusted technique. The prototype ROIC consumes 118.75 mu W power per column while has an NETD of less than 9mK. Simulation results of the proposed offset-calibration technique offers a minimum conversion time of 71.78 ns with a minimum residual voltage of 42 mu V.

Uncooled infrared imaging systems are a light weight and low cost alternative to their cooled counterparts. Uncooled microbolometer IR focal plane arrays (IRFPAs) for applications such as medical imaging, thermography, night vision, surveillance and industrial process control have recently been under focus. These systems have small pixel pitches (< 25 um) and require power efficiency, low noise equivalent temperature difference (NETD) (< 50 mK) and adequate scene dynamic range (> 250 K). Low NETD demands excellent microbolometer and readout noise performance. If sensitive analog circuits, driving long metal interconnects, are part of the pre-digitization readout channel, this necessitates the use of power consuming buffers, potentially in conjunction with noise cancellation circuits that result in power and area overhead. Thus re-thinking at the architectural level is crucial to meet these demands. Accordingly, in this thesis a column-parallel readout architecture for frame synchronous microbolometer imagers is proposed that enables low power operation by employing a time mode digitizer. The proposed readout circuit is based on a bridge type detector network with active and reference microbolometers and employs a capacitive transimpedance amplifier (CTIA) incorporating a novel two-step integration mechanism. By using a modified reset scheme in the CTIA, a forward ramp is initiated at the input side followed by the conventional backward integrated ramp at the output. This extends the measurement interval and improves signal-to-noise ratio (SNR). A synchronous counter based TDC measures this interval providing robust digitization. This technique also provides a way of compensating for self-heating effects. Being highly digital, the proposed architecture offers robust frontend processing and achieves a per channel power consumption of 66 uW, which is considerably lower than the most recently reported designs, while maintaining better than 10-mK readout NETD. Soğutmasız kızılötesi görüntüleme sistemleri, soğutmalı emsallerine göre hafif ve düşük maliyetli bir alternatiftir. Soğutmasız kızılötesi görüntüleme sistemlerinin en bilinenlerinden biri olan mikrobolometreler tıbbi görüntüleme, termografi, gece görüşü, gözetleme ve endüstriyel proses kontrolü gibi uygulamalar için son yıllarda artarak devam eden araştırmalara konu olmuştur. Bu sistemlerin küçük piksel aralıklarına (< 25 um) sahip olması, enerji verimliliklerinin yüksek olması, gürültü performansının yüksek olması (NETD) (< 50 mK) ve yüksek dinamik aralığa (> 250 K) sahip olması gerekmektedir. Düşük NETD mükemmel mikrobolometre ve okuma gürültüsü performansı gerektirir. Eğer hassas analog sinyaller uzun metal bağlantılarla bağlanmışsa, bu durum genellikle gürültü performansını iyileştirmek için yüksek güç tüketen ve fazla alan kaplayan tampon devreler gerektirir. Bu nedenle hem yüksek gürültü performansına ulaşan hem de düşük güç tüketip az alan kaplayan okuma devrelerinin geliştirilmesi için mimari düzeyde yenilikler gerekmektedir. Buna bağlı olarak, bu tezde zaman uyumlu bir sayısallaştırıcı kullanarak düşük gürültülü çalışmayı mümkün kılan mikrobolometre okuma devreleri için sütun-paralel bir okuma mimarisi önerilmiştir. Önerilen okuma devresi, aktif ve referans mikrobolometrelere sahip olan köprü tipi bir dedektör ağına dayanmaktadır ve yeni bir iki aşamalı entegrasyon mekanizmasını içeren kapasitif bir transpedans yükseltecini (CTIA) kullanmaktadır. CTIA'da modifiye edilmiş bir sıfırlama şeması kullanılarak, giriş tarafında ileri bir rampa ve ardından çıkışta geleneksel geriye entegre eden rampa kullanılır. Bu metod, ölçüm aralığını uzatır ve sinyal-gürültü oranını (SNR) iyileştirir. Senkron bir sayaç tabanlı zamandan sayısala çevirici (TDC), bu aralığı ölçerek sağlam dijitalleştirme sağlar. Dahası, bu teknik aynı zamanda kendi kendine ısınma etkilerini telafi etmenin bir yolunu sağlar. Yüksek dijitalliğe sahip olan önerilen mimari, güçlü ön uç işleme sunuyor ve en son bildirilen tasarımlardan oldukça düşük olan, kanal başına 66 uW güç tüketiyor. Bununla beraber 10 mK NETD değeri ile oldukça iyi bir gürültü performansı sunuyor. 109

This paper presents a partially pixel-parallel digital readout integrated circuit (DROIC) that overcomes the limitation of achievable digital resolution seen in megapixel-format infrared digital focal plane arrays (IR-DFPAs). It incorporates 5-bit inpixel pulse frequency modulation (PFM) based charge-todigital converters and 10-bit successive approximation register (SAR) column analog to digital converters (ADCs). To increase the readout resolution, the residue charge at the end of the integration phase is fine converted to a 10-bit digital word and combined with the in-pixel data. This method is a compromise between fully pixelparallel and fully column-parallel conversion approaches and favors the ever-growing trend towards small pitch FPAs by allowing a compact pixel size. A prototype consisting of a 32×32 array of pixels, 32 column SAR ADCs and a timing controller block is designed and fabricated in a 90nm bulk CMOS process. A modified version of the conventional PFM based pixel is designed to help hold the residue charge. The design is targeted at mediumwave IR-DFPAs with frame rates up to 400 Hz. An SNR of 79 dB is achieved with a full-well capacity of 2.4 Me-.

Digital pixels based on pulse frequency modulation (PFM) employ counting techniques to achieve very high charge handling capability compared to their analog counterparts. Moreover, extended counting methods making use of left-over charge (residue) on the integration capacitor help improve the noise performance of these pixels. However, focal plane arrays (FPAs) with small pixel pitch are constrained in terms of pixel area, which makes it difficult to benefit from in-pixel extended counting circuitry. Thus, in this paper, the authors propose a novel approach to measure the residue outside the pixel using an analog-to-digital converter (ADC). A first prototype of the proposed pixel, in the form of a testbed, has been developed which is aimed at medium-wave infrared (MWIR) imaging arrays having small pixel pitch. The prototype is composed of a pixel front end, a 12-bit SAR ADC, a counter, and a comparator. The front-end is a modified version of the conventional design and has been designed and fabricated in 90nm CMOS, whereas off-the-shelf discrete components have been used to implement the ADC, comparator, and counter. Measured signal-to-noise ratio (SNR) at low illumination levels is 55dB.