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Conventionally, a linear feedback shift register (LFSR) constitutes linear sets of sequences with predictable periods, which are considered vulnerable to intruders. Besides, an LFSR limits the sequences of scan-for-test patterns. This work introduces a private key, which is a collection of keywords, to program the feedback coefficients and initial states of the LFSR, where each keyword modulates the LFSR with a different polynomial of the same degree. That is, each polynomial generates a linear set of sequences. Consequently, the aggregate polynomial has a set of unpredictable and nonlinear sequences with high statistical randomness. The keyword, which holds the coefficients and initial states of the LFSR, can be managed in a few bits and stored in first-in first-out memory array. HSPICE simulations for 90 nm CMOS technology verify the functionality and speed of the proposed programmable feedback shift register (PFSR) of size 16-bit with 64 keywords. Results show a clock speed of 500 MHz with a power consumption of 73 µW and transistor count of 37,593, wherein the overall period has 4,194,240 unpredictable nonlinear sequences that surpass most LFSR structures. The PFSR can be suited for ASIC and reconfigurable HDL synthesis for efficient stream cipher and scan-for-test applications. [ABSTRACT FROM AUTHOR]

A memory Alias Table holds a major role in Register Renaming Unit (RRU), which is responsible for maintaining the translation between logical registers to physical registers under the given instruction(s). This work presents the design of the memory Alias Table based on the SRAM‐based 8T‐Cell with multiport write, read, and content‐address operations for two‐way three operands machine cycle. The design of the memory Alias Table of size 32‐row × 6‐bit has SRAM‐based CAM cell of type 21T‐Cell that comprises four‐read ports, two‐write ports, and two‐content‐address ports. The content‐address examines the register under‐test against all contents of the memory Alias Table in parallel and releases the associated match index address. Results show that the four read ports operate simultaneously within the half‐cycle, while the two write ports operate simultaneously within the other half‐cycle. The operation of the two content‐address ports is managed during the half‐cycle of the read phase. Thus, the three operations occur within a single cycle without latency. HSPICE simulations using 90 nm/1 V CMOS process reveal that the memory Alias Table provides the three operations within a one‐cycle of 1 GHz consuming an average power of 0.13 mW. [ABSTRACT FROM AUTHOR]

In this work, the circuit for unsigned integer restoring division divides each bit in one clock cycle, resulting in total delay cycles equal to the number of bits (n) plus an extra cycle for the final result. Thus, the proposed n-bit division circuit has an access time of (n+1) clock cycles. The hardware cost includes a subtractor and six registers, aligned with a two-phase clocking system. The novelty lies in the shift register, which shifts to the left during the high phase and restores data during the low phase of the clock. Although there are two phases of operations, the subtractor completes a full cycle for computation. As a result, the subtractor's delay time determines the clock period. The control unit is a simple ring shifter triggered at the clock's low phase. The simulation results obtained from synthesized HDL and HSPICE at 90 nm TSMC technology validate the circuit's functionality and characteristic feature of a performance rate of O(n). Using a standard CMOS library component, the 32-bit arithmetic divider requires 33 ns to produce exact Quotient and Remainder values. The circuit operates at a 1 GHz clock cycle and consumes a power of 752 µW. The total number of transistors used in this circuit is 8,860. [ABSTRACT FROM AUTHOR]

We present a new FIFO (first‐in first‐out) architecture for both synchronous and asynchronous communication for high‐speed and low‐power operation. Our FIFO design is reconfigurable and scalable using a separate datapath with an 8T‐Cell SRAM and control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals such that one signal increments the address pointer, while the other signal activates the memory decoder for data reading and writing. This structure halves the critical path delay and simplifies the timing operations between the memory decoder and address pointer while maintaining robustness against process‐voltage‐temperature (PVT) variations. Our design uses two alternative control circuits to manage separate synchronous and asynchronous operations by generating nonoverlapping control signals that drive the datapath circuit. The empty‐full flag circuitry records only the state of the address pointers' rollover independent of the memory size, and, thus, improves scalability and reconfigurability. Compared to prior works, our design is 5X faster with a 2.3X lower power consumption and has a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle. Additionally, our design functions clocklessly with the synthesizable structure for asynchronous communication that leverages Internet of Things (IoT) and Networks on Chip (NoCs) applications. The presented FIFO design is reconfigurable and scalable using separate datapath and synchronous/asynchronous control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals with 8T‐Cell memory. Our design operates 5X faster with a 2.3X lower total power consumption with a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle for the synchronous communication, and it serves for asynchronous Internet of Things (IoT) and Networks on Chip (NoCs) applications. [ABSTRACT FROM AUTHOR]

This paper presents a new sorting algorithm that sorts input data elements without any comparison operations between the data—comparison-free sorting. Our algorithm’s time complexity is on the order of O(N) for both single- and multi-threaded CPU and many-core GPU implementations. Our results show speedups on average of 4.6 × , 4 × , and 3.5 × for single-threaded CPU, 8-threaded CPU, and many-threaded GPU implementations, respectively, for input sizes ranging from 27 to 230 elements as compared to common sorting algorithms for a wide variation of element distributions, ranging from all unique elements to a single repeated element. In addition, our proposed algorithm more efficiently utilizes the GPU architecture as compared to a multi-core CPU architecture, showing a speedup of approximately 4 × for input sizes ranging from 27 to 230 elements. [ABSTRACT FROM AUTHOR]

In this paper, two essential components of the Flash ADC are designed and integrated within a new Flash ADC architecture. The power consumption is reduced by realizing a switched-capacitor positive feedback (SCPF) comparators structure as a replacement for conventional comparators structure. The SCPF comparator is tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision. Furthermore, the encoding stage is implemented using N parallel independent components of one single AND gate each, where N is the number of quantized regions. This structure provides fast encoding with minimal encoding activities. The design architecture exploits two stages, which are separated by latches. The first stage allocates the analog input to a quantized region, while the second stage converts the level of the quantized region into its corresponding binary code. This separation is considered the key success for incorporating the SCPF comparators structure into our Flash ADC architecture. HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technology and 1-V power supply. The simulation results show that our 5-bit Flash ADC can function at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz at Nyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with an overall maximum power consumption of 3 mW. [ABSTRACT FROM AUTHOR]

We present a scalable high-speed divide-by- N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling effect. The pipeline latencies are precluded due to the use of a subtractor circuit that 'swallows' any additional cycles. Furthermore, our frequency divider is easily scalable to large divider widths due to the use of modular component architecture. The fan-in and fan-out are independent of the divider width, thus making the structure attractive for regular VLSI implementation and continued technology scaling. We implemented our proposed divider using a 0.15-μm TSMC digital cell library and achieved a maximum operating frequency of 2 GHz, an area of 112 848 μm (900 transistors), and consumed 15.47 mW of power operating at 2 GHz for an 8-bit design, which offers 252 different frequency divisions. [ABSTRACT FROM AUTHOR]

Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock, thereby maintaining one active line per column and eliminating the use of traditional sense amplifier with all its synchronization schemes. The simulation results show that the embedded SRAM of size 128-bit × 128-bit is operating at a maximum frequency of 200 MHz for Write and Read clock cycles with 1.62 V power supply, and measures a total average power consumption of 22.60 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 × 3.0 μm2. The circuit is not meant to replace the SRAM with 6T-Cell transistor structure; however, it is attractive for applications related to high density with automation road-map design, such as graphic and network processor chips. In these applications, memory sizes are introduced in many different irregular geometries and uses all over the chip with storage sizes less than 20 k-bit, in addition, it is susceptible to large substrate noise as well as large coupling wire routing. [ABSTRACT FROM AUTHOR]