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This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software (NESS) which is currently under development at the Device Modeling Group of the University of Glasgow. NESS is designed with the main aim to provide an open, flexible, and easy to use simulation environment where users are able not only to perform numerical simulations but also to develop and implement new simulation methods and models. Currently, NESS is organized into two main components: the structure generator and a collection of different numerical solvers; which are linked to supporting components such as an effective mass extractor and materials database. This paper gives a brief overview of each of the components by describing their main capabilities, structure, and theory behind each one of them. Moreover, to illustrate the capabilities of each component, here we have given examples considering various device structures, architectures, materials, etc. at multiple simulation conditions. We expect that NESS will prove to be a great tool for both conventional as well as exploratory device research programs and projects.

The modelling of conventional and novel memory devices has gained significant traction in recent years. This is primarily because the need to store increasingly larger amount of data demands a better understanding of the working of the novel memory devices, to enable faster development of the future technology generations. Furthermore, in-memory computing is also of great interest from the computational perspectives, to overcome the data transfer bottleneck that is prevalent in the von-Neumann architecture. These important factors necessitates the development of comprehensive TCAD simulation tools that can be used for modeling carrier dynamics in the gate oxides of the Flash type memory cells. In this work, we introduce the kinetic Monte Carlo module that we have developed and integrated within the Nano Electronic Simulation Software (NESS) - to model electronic charge transport in Flash memory type structures. Using the developed module, we perform retention time analysis for a polyoxometalate (POM) molecule-based charge trap flash memory. Our simulation study highlights that retention characteristics for the POM molecules has a unique features that depends on the properties of the tunneling oxide.

Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on SixGe1−x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from sp3d5s∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.

In this paper, we report a hierarchical simulation\ud study of the electromigration problem in Cu-CNT composite\ud interconnects. Our work is based on the investigation of the\ud activation energy and self-heating temperature using a multiscale\ud electro-thermal simulation framework. We first investigate the\ud electrical and thermal properties of Cu-CNT composites, including\ud contact resistances, using the Density Functional Theory and\ud Reactive Force Field approaches, respectively. The corresponding\ud results are employed in macroscopic electro-thermal simulations\ud taking into account the self-heating phenomenon. Our simulations\ud show that although Cu atoms have similar activation\ud energies in both bulk Cu and Cu-CNT composites, Cu-CNT\ud composite interconnects are more resistant to electromigration\ud thanks to the large Lorenz number of the CNTs. Moreover,\ud we found that a large and homogenous conductivity along the\ud transport direction in interconnects is one of the most important\ud design rules to minimize the electromigration.

In this paper, we report a hierarchical simulation study of the electromigration (EM) problem in Cu-carbon nanotube (CNT) composite interconnects. This paper is based on the investigation of the activation energy and self-heating temperature using a multiscale electrothermal simulation framework. We first investigate the electrical and thermal properties of Cu-CNT composites, including contact resistances, using the density functional theory and reactive force field approaches, respectively. The corresponding results are employed in macroscopic electrothermal simulations taking into account the self-heating phenomenon. Our simulations show that although Cu atoms have similar activation energies in both bulk Cu and Cu-CNT composites, Cu-CNT composite interconnects are more resistant to EM thanks to the large Lorenz number of the CNTs. Moreover, we found that a large and homogenous conductivity along the transport direction in interconnects is one of the most important design rules to minimize the EM.

2-D numerical simulations are used to demonstrate the Z²-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

The Z²-FET operation as capacitorless DRAM\ud is analyzed using advanced 2-D TCAD simulations for IoT\ud applications. The simulated architecture is built based on\ud actual 28-nm fully depleted silicon-on-insulatordevices. It is\ud found that the triggering mechanism is dominated by the\ud front-gate bias and the carrier’s diffusion length. As in other\ud FB-DRAMs, the memory window is defined by the ON voltage\ud shift with the stored body charge. However, the Z²-FET’s\ud memory state is not exclusively defined by the inner charge\ud but also by the reading conditions.

This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here. Our discussions are based on numerous theoretical approaches starting from first principle methods and continuing with discussions based on more well stablished methods such as Drift-Diffusion, Monte Carlo and Non-Equilibrium Green’s Function formalism.

In this work we establish a link between positions of a single discrete charge trapped in an oxide interface and between the performance of ultra-scaled FinFET transistors. The charge trapped in the oxide induces gate voltage shift (∆VG). This ∆VG is presented as a function of the device geometry for two regimes of\ud conduction – from a sub-threshold to an ON-state. For specific trap positions in the oxide, we show that the trap impact decreases with scaling down of the FinFET size and of the applied gate voltage. We also compare the Drift-Diffusion (DD) calculations with the Non Equilibrium Green Functions (NEGF) simulations in order to investigate the importance of quantum charge confinement in transport and of reliability resilience in\ud ultra-scaled non-planar transistors, such as FinFETs.

The core of this thesis is a thorough investigation of the scaling properties of conventional nano-CMOS MOSFETs, their physical and operational limitations and intrinsic parameter fluctuations. To support this investigation a well calibrated 35 nm physical gate length real MOSFET fabricated by Toshiba was used as a reference transistor. Prior to the start of scaling to shorter channel lengths, the simulators were calibrated against the experimentally measured characteristics of the reference device. Comprehensive numerical simulators were then used for designing the next five generations of transistors that correspond to the technology nodes of the latest International Technology Roadmap for Semiconductors (lTRS). The scaling of field effect transistors is one of the most widely studied concepts in semiconductor technology. The emphases of such studies have varied over the years, being dictated by the dominant issues faced by the microelectronics industry. The research presented in this thesis is focused on the present state of the scaling of conventional MOSFETs and its projections during the next 15 years. The electrical properties of conventional MOSFETs; threshold voltage (VT), subthreshold slope (S) and on-off currents (lon, Ioffi ), which are scaled to channel lengths of 35, 25, 18, 13, and 9 nm have been investigated. In addition, the channel doping profile and the corresponding carrier mobility in each generation of transistors have also been studied and compared. The concern of limited solid solubility of dopants in silicon is also addressed along with the problem of high channel doping concentrations in scaled devices. The other important issue associated with the scaling of conventional MOSFETs are the intrinsic parameter fluctuations (IPF) due to discrete random dopants in the inversion layer and the effects of gate Line Edge Roughness (LER). The variations of the three important MOSFET parameters (loff, VT and Ion), induced by random discrete dopants and LER have been comprehensively studied in the thesis. Finally, one of the promising emerging CMOS transistor architectures, the Ultra Thin Body (UTB) SOl MOSFET, which is expected to replace the conventional MOSFET, has been investigated from the scaling point of view.