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In this paper, we design and fabricate a Schottky-metal-insulator-semiconductor (MIS) cascode anode GaN lateral field-effect diode (CA-LFED) to achieve ultralow reverse leakage current (ILEAK). The device based on AlGaN/GaN high-electron-mobility-transistor (HEMT) includes a normally-off MIS-controlled channel that is cascoded with a high barrier height Schottky contact. At reverse bias, the high electric-field is effectively prevented by the normally-off MIS-controlled channel edge. Together with the high barrier height Schottky contact, this feature significantly suppresses the ILEAK. Supported by the device fabrication, the CA-LFED with high breakdown voltage (BV) > 600 V shows an ultralow ILEAK of 3.6 × 10−9 A/mm as well as a low forward voltage drop (VF) of 2.2 V. The performance suggests that the CA-LFED can be a promising candidate for ultralow ILEAK and better VF-ILEAK trade-off GaN power diode applications. [ABSTRACT FROM AUTHOR]

The small-signal S parameters of the fabricated double-finger gate AlGaN/GaN high electron mobility transistors (HEMTs) were measured at various direct current quiescent operating points (DCQOPs). Under active bias conditions, small-signal equivalent circuit (SSEC) parameters such as Rs and Rd, and intrinsic parameters were extracted. Utilizing fT and the SSEC parameters, the effective electron velocity ( ν e − e f f ) and intrinsic electron velocity ( ν e − int ) corresponding to each gate bias (VGS) were obtained. Under active bias conditions, the influence mechanism of VGS on ν e − e f f was systematically studied, and an expression was established that correlates ν e − e f f , ν e − int , and bias-dependent parasitic resistances. Through the analysis of the main scattering mechanisms in AlGaN/GaN HEMTs, it has been discovered that the impact of VGS on ν e − e f f should be comprehensively analyzed from the aspects of ν e − int and parasitic resistances. On the one hand, changes in VGS influence the intensity of polar optical phonon (POP) scattering and polarization Coulomb field (PCF) scattering, which lead to changes in ν e − int dependent on VGS. The trend of ν e − int with changes in VGS plays a dominant role in determining the trend of ν e − e f f with changes in VGS. On the other hand, both POP scattering and PCF scattering affect ν e − e f f through their impact on parasitic resistance. Since there is a difference in the additional scattering potential corresponding to the additional polarization charges (APC) between the gate-source/drain regions and the region under the gate, the mutual effects of PCF scattering on the under-gate electron system and the gate-source/drain electron system should be considered when adjusting the PCF scattering intensity through device structure optimization to improve linearity. This study contributes to a new understanding of the electron transport mechanisms in AlGaN/GaN HEMTs and provides a novel theoretical basis for improving device performance. [ABSTRACT FROM AUTHOR]

In this study, AlGaN/GaN HEMTs with Au-free Ti/Al/Ni/Ti ohmic contacts were fabricated. The device presents a contact resistance (R c) of 0.64 Ω·mm and high linearity characteristics. The two-tone measurement at 28 GHz shows that the 2 × 50 μ m device exhibits an excellent third-order intercept point (OIP3) value of 41.64 dBm at V DS = 28 V, and an OIP3/ P DC of 24.2. An OIP3 of 46.59 dBm was achieved when the device's gate width was increased to 8 × 50 μ m at V DS = 48 V. These results demonstrate that AlGaN/GaN HEMTs with Ti/Al/Ni/Ti ohmic contacts have potential for Ka-band applications. [ABSTRACT FROM AUTHOR]

The InAlN/GaN HEMT has been identified as a promising alternative to conventional AlGaN/GaN HEMT due to its enhanced polarization effect contributing to higher 2DEG in the GaN channel. However, the InAlN barrier usually suffers from high leakage and therefore low breakdown voltage. In this paper, we propose an asymmetrical GaN HEMT structure which is composed of an InAlN barrier at the source side and an AlGaN barrier at the drain side. This novel device combines the advantages of high 2DEG density at the source side and low electrical-field crowding at the drain side. According to the TCAD simulation, the proposed asymmetric device exhibits better drain current and transconductance compared to AlGaN/GaN HEMT, and enhanced breakdown voltage compared to InAlN/GaN HEMT. The current collapse effects have also been evaluated from the process-related point of view. Possible higher interface traps related to the two-step epitaxial growth for the asymmetric structure fabrication will not exacerbate the current collapse and reliability. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the electrical characteristics of AlGaN/GaN HEMTs at the lowest temperature of 20 K. The measurement results indicate that the output current of the device decreases significantly with increasing temperature at temperature ranging from 40 K to 260 K, and the saturation drain current decreases by 19%. The gate leakage current rises slightly when the temperature increases. However, both the transfer and C-V characteristics indicate that the threshold voltage shift slightly in a negative direction as the temperature rises. In order to determine the physical mechanism of electrical characteristics change, the low-frequency noise (LFN) characteristics at different temperatures were measured and the density of traps was extracted. Finally, we consider that there are two competing mechanisms affecting the electrical characteristics of devices. The trap density reduction caused by temperature rise leads to threshold voltage’s negative shift, while the drop of 2DEG mobility is the main reason for the decrease of output current.

The small-signal S parameters of the fabricated double-finger gate AlGaN/GaN high electron mobility transistors (HEMTs) were measured at various direct current quiescent operating points (DCQOPs). Under active bias conditions, small-signal equivalent circuit (SSEC) parameters such as Rs and Rd, and intrinsic parameters were extracted. Utilizing fT and the SSEC parameters, the effective electron velocity (νe−eff) and intrinsic electron velocity (νe−int) corresponding to each gate bias (VGS) were obtained. Under active bias conditions, the influence mechanism of VGS on νe−eff was systematically studied, and an expression was established that correlates νe−eff, νe−int, and bias-dependent parasitic resistances. Through the analysis of the main scattering mechanisms in AlGaN/GaN HEMTs, it has been discovered that the impact of VGS on νe−eff should be comprehensively analyzed from the aspects of νe−int and parasitic resistances. On the one hand, changes in VGS influence the intensity of polar optical phonon (POP) scattering and polarization Coulomb field (PCF) scattering, which lead to changes in νe−int dependent on VGS. The trend of νe−int with changes in VGS plays a dominant role in determining the trend of νe−eff with changes in VGS. On the other hand, both POP scattering and PCF scattering affect νe−eff through their impact on parasitic resistance. Since there is a difference in the additional scattering potential corresponding to the additional polarization charges (APC) between the gate-source/drain regions and the region under the gate, the mutual effects of PCF scattering on the under-gate electron system and the gate-source/drain electron system should be considered when adjusting the PCF scattering intensity through device structure optimization to improve linearity. This study contributes to a new understanding of the electron transport mechanisms in AlGaN/GaN HEMTs and provides a novel theoretical basis for improving device performance.

Cooling is important for AlGaN/GaN high-electron mobility transistors (HEMTs) performance. In this paper, the advantages and disadvantages of the cooling performance of three cooling schemes: remote cooling (R-cool), near-chip cooling (NC-cool), and chip-embedded cooling (CE-cool) are compared. The influences of distinct geometric parameters and operating conditions on thermal resistance are investigated. The results show that the thermal resistances of NC-cool and CE-cool are almost the same as each other. Decreasing microchannel base thickness (hb) significantly increases the thermal resistance of CE-cool, and when its thickness is less than a critical value, NC-cool exhibits superior cooling performance than CE-cool. The critical thickness increases when decreasing the heat source pitch (Ph) and the convective heat transfer coefficient (hconv) or increasing the thermal conductivity of the substrate (λsub). Moreover, increasing Ph or λsub significantly improves the thermal resistance of three cooling schemes. Increasing hconv significantly decreases the thermal resistances of NC-cool and CE-cool while hardly affecting the thermal resistance of R-cool. The influence of the boundary thermal resistance (TBR) on the thermal resistance significantly increases at higher λsub and larger hconv. [ABSTRACT FROM AUTHOR]

The effect of different SiNx thicknesses on the performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) was investigated in this paper. The current, transconductance (Gm), cut-off frequency (fT), maximum oscillation frequency (fmax), power performance, and output third-order intercept point (OIP3) of devices with three different SiNx thicknesses (150 nm, 200 nm, and 250 nm) were measured and analyzed. The DC measurements revealed an increase in both the drain-source current (IDS) and Gm values of the device with increasing SiNx thickness. The S-parameter measurement results show that devices with a higher SiNx thickness exhibit improved fT and fmax. Regarding power performance, thicker SiNx devices also improve the output power density (Pout) and power-added efficiency (PAE) in the Ka-band. In addition, the two-tone measurement results at 28 GHz show that the OIP3 increased from 35.60 dBm to 40.87 dBm as the SiNx thickness increased from 150 nm to 250 nm. The device's characteristics improved by appropriately increasing the SiNx thickness. [ABSTRACT FROM AUTHOR]

We present the mean time to failure (MTTF) of on-wafer AlGaN/GaN HEMTs under two distinct electric field stress conditions. The channel temperature (Tch) of the devices exhibits variability contingent upon the stress voltage and power dissipation, thereby influencing the long-term reliability of the devices. The accuracy of the channel temperature assumes a pivotal role in MTTF determination, a parameter measured and simulated through TCAD Silvaco device simulation. Under low electric field stress, a gradual degradation of IDSS is noted, accompanied by a negative shift in threshold voltage (ΔVT) and a substantial increase in gate leakage current (IG). Conversely, the high electric field stress condition induces a sudden decrease in IDSS without any observed shift in threshold voltage. For the low and high electric field conditions, MTTF values of 360 h and 160 h, respectively, were determined for on-wafer AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

We present a high-performance AlGaN/GaN high electron mobility transistors (HEMTs) on silicon substrate with novel stacked passivation layer (HfO2/SiO2). The stacked passivation structure can effectively modulate the electric field and reduce the electric field peak on the gate side, thus improving the breakdown voltage of the device. The prepared device with a gate length of 450 nm has a unit current gain cutoff frequency (fT) of 31.5 GHz, a maximum oscillation frequency (fMAX) of 46.3 GHz, and a three-terminal OFF-state breakdown voltage (BVgd) of 140 V at the gate-drain distance of $2.3~\mu \text{m}$ . The estimated Johnson’s figure of merit (J-FOM = BVgd $\times \text{f}$ T) is 4.4 THz•V, which is three and five times higher than that of the device with single HfO2 passivation layer and single SiO2 passivation layer, respectively. Furthermore, a significant suppression of the current collapse (~5.7%) is observed due to the electric field redistribution near the drain region. The results show that the AlGaN/GaN HEMTs with stacked passivation layer proved to be a promising candidate for high-performance radio frequency (RF) power device applications.

This study investigated the electrical properties of AlGaN/GaN high-electron-mobility transistors (HEMTs) with varied recess depths under the gate electrode. We demonstrated a recess depth of approximately 6 nm, which was achieved through neutral beam etching (NBE) technique with a low etch rate of 1.8 nm/min, resulting in device enhancement-mode (E-mode) behavior with threshold voltage (Vth) of 0.49 V. The effects of post-metallization annealing (PMA) on the device performance were also examined. The results revealed that PMA treatment improves the DC characteristics of the devices, including maximum drain current (IDMAX), transconductance (gm), subthreshold swing (SS), on-off ratio, and off-state leakage current, with maximum enhancement percentage of 18.3% for IDMAX, 3758% for on-off ratio, and 54.3% for SS. Moreover, this study compared the recess depths of metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with the SiN dielectric layer. The results showed that MIS-HEMTs exhibit more negative Vth values, which can be attributed to the controlled surface states achieved through passivation.

In this paper, a P-type GaN buried layer is introduced into the buffer layer of AlGaN/GaN HEMTs, and the effect of the P-type GaN buried layer on the device's temperature characteristics is studied using Silvaco TCAD software. The results show that, compared to the conventional device structure, the introduction of a P-type GaN buried layer greatly weakens the peak of the channel electric field between the gate and drain of the device. This leads to a more uniform electric field distribution, a substantial reduction in the lattice temperature of the device, and a more uniform temperature distribution. Therefore, the phenomenon of negative resistance caused by self-heating effect is significantly mitigated, while the breakdown performance of the device is also notably enhanced. [ABSTRACT FROM AUTHOR]

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate–source current and the gate–drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected. [ABSTRACT FROM AUTHOR]

In this paper, AlGaN/GaN high electron mobility transistors (HEMTs) with etched-fin gate structures fabricated to improve device linearity for Ka-band application are reported. Within the proposed study of planar, one-etched-fin, four-etched-fin, and nine-etched-fin devices, which have 50-μm, 25-μm, 10-μm, and 5-μm partial gate widths, respectively, the four-etched-fin gate AlGaN/GaN HEMT devices have demonstrated optimized device linearity with respect to the extrinsic transconductance ( G m ) value, the output third order intercept point (OIP3), and the third-order intermodulation output power (IMD3) level. The IMD3 is improved by 7 dB at 30 GHz for the 4 × 50 μm HEMT device. The OIP3 is found to reach a maximum value of 36.43 dBm with the four-etched-fin device, which exhibits high potential for the advancement of wireless power amplifier components for Ka band applications. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron-mobility transistors (HEMTs) with two different gate–drain distances (30 μm and 10 μm) were exposed to 1 MeV, 0.6 MeV, and 0.4 MeV protons at a fluence of 2.16 × 1012 cm−2. The gate–channel electron density and low-field mobility were obtained by measuring the capacitance–voltage characteristics and current–voltage characteristics. After proton irradiation, the gate–channel low-field electron mobility of the AlGaN/GaN HEMT with a 30 μm gate–drain distance increases and that with a 10 μm gate–drain distance decreases. It is studied and found that the mobility behavior is related to the polarization Coulomb field scattering, and the proton irradiation influences the intensity of the polarization Coulomb field scattering by changing the polarization/strain distribution in the barrier layer. The different gate–drain distances correspond to different variation trends of scattering intensity. The effect of 1 MeV protons on the barrier layer is smaller compared with 0.6 MeV and 0.4 MeV protons, so the mobility variation is smaller. [ABSTRACT FROM AUTHOR]

The aim of this paper is to model the effects of threading dislocations on both gate and drain currents of AlGaN/GaN high electron mobility transistors (HEMTs). The fraction of filled traps increases with the threading dislocations, while the trapping effects cause a decrease in drain current and an increase in gate leakage current. To model the drain current drop, the two simplified RC subcircuits with diodes are proposed to capture the charge trapping/detrapping characteristics. The trap voltages Vg_trap and Vd_trap generated by RC networks are fed back into the model to capture the effects of traps on drain current. Considering acceptor-decorated dislocations, we present a novel Poole–Frenkel (PF) model to precisely describe the reverse leakage gate current, which plays a dominant role in the gate leakage current. The proposed model, which uses physical parameters only, is implemented in Verilog-A. It is in excellent agreement with the experimental data. [ABSTRACT FROM AUTHOR]

In this study, AlGaN/GaN HEMTs with Au-free Ti/Al/Ni/Ti ohmic contacts were fabricated. The device presents a contact resistance ( R _c ) of 0.64 Ω·mm and high linearity characteristics. The two-tone measurement at 28 GHz shows that the 2 × 50 μ m device exhibits an excellent third-order intercept point (OIP3) value of 41.64 dBm at V _DS = 28 V, and an OIP3/ P _DC of 24.2. An OIP3 of 46.59 dBm was achieved when the device’s gate width was increased to 8 × 50 μ m at V _DS = 48 V. These results demonstrate that AlGaN/GaN HEMTs with Ti/Al/Ni/Ti ohmic contacts have potential for Ka-band applications.

Cooling is important for AlGaN/GaN high-electron mobility transistors (HEMTs) performance. In this paper, the advantages and disadvantages of the cooling performance of three cooling schemes: remote cooling (R-cool), near-chip cooling (NC-cool), and chip-embedded cooling (CE-cool) are compared. The influences of distinct geometric parameters and operating conditions on thermal resistance are investigated. The results show that the thermal resistances of NC-cool and CE-cool are almost the same as each other. Decreasing microchannel base thickness (hb) significantly increases the thermal resistance of CE-cool, and when its thickness is less than a critical value, NC-cool exhibits superior cooling performance than CE-cool. The critical thickness increases when decreasing the heat source pitch (Ph) and the convective heat transfer coefficient (hconv) or increasing the thermal conductivity of the substrate (λsub). Moreover, increasing Ph or λsub significantly improves the thermal resistance of three cooling schemes. Increasing hconv significantly decreases the thermal resistances of NC-cool and CE-cool while hardly affecting the thermal resistance of R-cool. The influence of the boundary thermal resistance (TBR) on the thermal resistance significantly increases at higher λsub and larger hconv.

In this paper, Silvaco TCAD software is used to simulate the buffer traps in AlGaN/GaN high electron mobility transistors (HEMTs), and its effects on the breakdown performance and key parameters of the devices are investigated by changing the position and concentration of the acceptor traps in the buffer layer. The results show that with the increase of trap concentration, the traps capture electrons and reduce the off-state leakage current, which can improve breakdown voltage of the devices. At the same time, as the trap concentration increases, the ionized traps make a high additional electric field near the drain edge, leading to the decrease of breakdown voltage. With the combined two effects above, the breakdown voltage almost ultimately saturates. When the source-to-gate (Access-S) region in the GaN buffer layer is doped alone, the minimum and most linear leakage current for the same trap concentrations are obtained, and the additional electric field has a relatively small effect on the electric field peak near the drain as the ionized traps are furthest from drain. All these factors make the breakdown voltage increase more controllably with the Access-S region doping, and it is a more potential way to improve the breakdown performance. [ABSTRACT FROM AUTHOR]

We present the mean time to failure (MTTF) of on-wafer AlGaN/GaN HEMTs under two distinct electric field stress conditions. The channel temperature (Tch) of the devices exhibits variability contingent upon the stress voltage and power dissipation, thereby influencing the long-term reliability of the devices. The accuracy of the channel temperature assumes a pivotal role in MTTF determination, a parameter measured and simulated through TCAD Silvaco device simulation. Under low electric field stress, a gradual degradation of IDSS is noted, accompanied by a negative shift in threshold voltage (ΔVT) and a substantial increase in gate leakage current (IG). Conversely, the high electric field stress condition induces a sudden decrease in IDSS without any observed shift in threshold voltage. For the low and high electric field conditions, MTTF values of 360 h and 160 h, respectively, were determined for on-wafer AlGaN/GaN HEMTs.

In AlGaN/GaN high electron mobility transistors (HEMTs), high temperature processes (such as ohmic annealing with >800°C value) could deform the crystal structure and induce trap states within the bulk and surface. Expanded defect densities cause crucial problems, such as threshold voltage ($\text{V}_{\text {th}}$) instability, current collapse, and high leakages. In this work, a low temperature ohmic contact process (630°C, 10 minutes) is adopted with recess etch, and contact resistances $< 0.1\Omega ~\cdot $ mm with low sheet resistances are achieved. The positive impact of this low thermal budget process on surface morphology, DC operation, long-term stability, and forward gate bias stress of the device is studied. [ABSTRACT FROM AUTHOR]

Nanocrystalline diamond capping layers have been demonstrated to improve thermal management for AlGaN/GaN HEMTs. To improve the RF devices, the application of the technology, the technological approaches and device characteristics of AlGaN/GaN HEMTs with gate length less than 0.5 μm using nanocrystalline diamond capping layers have been studied systematically. The approach of diamond-before-gate has been adopted to resolve the growth of nanocrystalline diamond capping layers and compatibility with the Schottky gate of GaN HEMTs, and the processes of diamond multi-step etching technique and AlGaN barrier protection are presented to improve the technological challenge of gate metal. The GaN HEMTs with nanocrystalline diamond passivated structure have been successfully prepared; the heat dissipation capability and electrical characteristics have been evaluated. The results show the that thermal resistance of GaN HEMTs with nanocrystalline diamond passivated structure is lower than conventional SiN-GaN HEMTs by 21.4%, and the mechanism of heat transfer for NDC-GaN HEMTs is revealed by simulation method in theory. Meanwhile, the GaN HEMTs with nanocrystalline diamond passivated structure has excellent output, small signal gain and cut-off frequency characteristics, especially the current–voltage, which has a 27.9% improvement than conventional SiN-GaN HEMTs. The nanocrystalline diamond capping layers for GaN HEMTs has significant performance advantages over the conventional SiN passivated structure. [ABSTRACT FROM AUTHOR]

In the current study, the effects of cracks in source field plates (SFPs) on the electrical performance of AlGaN/GaN high electron mobility transistors (HEMTs) are investigated systematically using numerical simulation. In detail, the influence of crack width and junction angle in SFPs on device performance is studied. The results indicate that the SFP structure increases the breakdown voltage of a device, but the occurrence of cracks causes premature breakdown, which is confirmed experimentally by the structural analysis of these devices after breakdown. With an increase in crack width, the electrical performance becomes worse. A beveled SFP architecture is proposed by increasing the angle at the SFP junction to reduce the probability of cracking and enhance the reliability of the device. However, with an increase in bevel angle, the modulation effect of the SFP on the channel electric field is gradually weakened. Therefore, it is necessary to balance the relationship between electrical performance and bevel angle according to the actual demands. This work provides potential support for SFP structural optimization design for AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, a P-type GaN buried layer is introduced into the buffer layer of AlGaN/GaN HEMTs, and the effect of the P-type GaN buried layer on the device’s temperature characteristics is studied using Silvaco TCAD software. The results show that, compared to the conventional device structure, the introduction of a P-type GaN buried layer greatly weakens the peak of the channel electric field between the gate and drain of the device. This leads to a more uniform electric field distribution, a substantial reduction in the lattice temperature of the device, and a more uniform temperature distribution. Therefore, the phenomenon of negative resistance caused by self-heating effect is significantly mitigated, while the breakdown performance of the device is also notably enhanced.

• A novel method to determine bias-dependent source and drain parasitic series resistances in AlGaN/GaN high electron mobility transistors has been proposed. • The physical mechanism that causes R s and R d to vary with bias voltage is studied. • The bias voltage can affect the magnitude of R s and R d by affecting the optical phonon temperature and the intensity of the inverse piezoelectric effect. The AlGaN/GaN high electron mobility transistors (HEMTs) with T-gate that suitable for high frequency applications were fabricated. A novel method to extract the bias-dependent source and drain parasitic series resistances (R s and R d) of AlGaN/GaN HEMTs is proposed. By analyzing the distributed capacitance and current generator network in the velocity saturated regions of the AlGaN/GaN HEMTs, a new restriction relationship between small-signal equivalent circuit elements is found. The R s and R d can be determined under active bias through wideband S-parameter measurements, which can better reflect the physical mechanism of AlGaN/GaN HEMTs under normal operation. The S-parameters and extrinsic transconductance calculated based the small-signal equivalent circuit element values extracted by the method proposed in this paper are very consistent with the experimental values, which reflects the accuracy of this element extraction method. In this paper, the physical mechanism that causes R s and R d to vary with bias voltage is also studied. This study has a deeper insight into the bias-dependence of R s and R d , which modifies the understanding for physical mechanisms of AlGaN/GaN HEMTs. The research results provide new ideas for establishing small-signal equivalent circuit models containing more physical effects and is of great significance to GaN-based integrated circuit design. [ABSTRACT FROM AUTHOR]

An unrecoverable degradation of gate leakage is observed in AlGaN/GaN high electron mobility transistors (HEMTs) under high OFF‐state drain bias stress up to 200 V. Current‐mode deep‐level transient spectroscopy is developed for in situ observation of evolution of traps in the HEMTs before and after stress. It is revealed that two discrete traps, with activation energy of 0.54 and 0.69 eV, have converted into a deeper and broader trap (0.86 eV) after the stress, along with an increased apparent capture cross section (from 1.71 × 10−17–1.11 × 10−15 cm2 to 9.05 × 10−15 cm2). The conversion lowers down the tunneling barrier between metal and the AlGaN barrier, which facilitates trap‐assisted gate leakage in reversed biased AlGaN/GaN HEMTs. Engineering of deep traps in the AlGaN/GaN epilayers is essential for promoting and upgrading of power capability of GaN‐based RF HEMTs. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrated a normally-off AlGaN/GaN HEMT using p-NiO as a gate stack combined with a recess structure. The fabricated HEMT exhibits a positive threshold voltage of 1.73 V, a saturation output current of 524 mA/mm, a small subthreshold swing of 79.7 mV/dec and a maximum transconductance as high as 143 mS/mm. This is the first time to demonstrate the breakdown characteristics of a p-NiO gate HEMT with a high breakdown voltage of 1205 V and a low specific ON-resistance of 2.22 $\text{m}\Omega \cdot $ cm2, yielding a competitive Baliga’s figure-of-merit of 0.65 GW/cm2. The instability evaluation of ${V}_{\text {TH}}$ by step stress and pulse transfer curves shows that the p-NiO gate HEMT has a negligible ${V}_{\text {TH}}$ shift in the entire measured gate bias range, which can be attributed to the counteraction between the electron trapping-induced positive $\text{V}_{\text {TH}}$ shift and hole accumulation induced-negative ${V}_{\text {TH}}$ shift. It is well understood in terms of the carrier transport model based on the large band discontinuity at the interface of the p-NiO/AlGaN type-II heterojunction, which is further verified by transient gate current spectra. [ABSTRACT FROM AUTHOR]

In this paper, AlGaN/GaN high electron mobility transistors (HEMTs) with etched-fin gate structures fabricated to improve device linearity for Ka-band application are reported. Within the proposed study of planar, one-etched-fin, four-etched-fin, and nine-etched-fin devices, which have 50-μm, 25-μm, 10-μm, and 5-μm partial gate widths, respectively, the four-etched-fin gate AlGaN/GaN HEMT devices have demonstrated optimized device linearity with respect to the extrinsic transconductance (Gm) value, the output third order intercept point (OIP3), and the third-order intermodulation output power (IMD3) level. The IMD3 is improved by 7 dB at 30 GHz for the 4 × 50 μm HEMT device. The OIP3 is found to reach a maximum value of 36.43 dBm with the four-etched-fin device, which exhibits high potential for the advancement of wireless power amplifier components for Ka band applications.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate–source current and the gate–drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.

We report a unique OFF-state drain-to-source critical stress voltage above which the dynamic performance of AlGaN/GaN HEMTs is significantly deteriorated. Physical insights are developed through detailed experiments conducted for different design variants, increased substrate bias, varying temperature, varying stress time, and experimenting buffers with lower C-doping. The surface leakage measurements on dedicated test structures and experimentation of devices realized over GaN buffer with different carbon doping reveal that the observed phenomenon is solely caused by traps present in carbon-doped GaN buffer. Surface traps have no role to play as far as they do not modulate the electric field in the GaN buffer (discussed in Part-II). Stress time, substrate temperature, substrate bias, electric-field shape, and depletion regions formed under the gate as well as field plate region were found to play a key role in governing trap-assisted transport and carrier trapping in the GaN buffer. A deeper physical insight to explain the observed phenomena and its dependency on various conditions are developed through detailed measurements, TCAD simulations, electroluminescence, and photoluminescence spectroscopy. With the help of the physical insight gained into the underlying mechanism, a novel surface passivation scheme using a p-type oxide is reported in Part-II, which helps relaxing the field distribution across the access region and buffer, and in turn improves the dynamic performance of the HEMTs. Besides, the Part-II also unifies the mechanism across different gate-stack designs and reveals the interplay between the surface and buffer, which governs the dynamic performance of these devices. [ABSTRACT FROM AUTHOR]

The underlying mechanism responsible for the unique dynamic ON-resistance behavior is unified by demonstrating the presence of critical drain stress voltage, above which dynamic ON-resistance increases significantly, in different gate stacks. Metal–insulator–semiconductor (MIS)- and Schottky-gated HEMTs show similar dependence of critical voltage on various parameters, which establishes that gate-stack design has negligible impact on the observed phenomena. Furthermore, using the physical insights developed, this work proposes a novel surface passivation scheme to improve the dynamic performance of the device. The proposed surface passivation scheme uses p-type Al0.5Ti0.5O (AlTiO), which is deposited over SiNx passivation (or GaN cap), and is shown to be an effective tool in improving the dynamic ON-resistance of the device by modulating the electric field in the GaN buffer. The proposed passivation scheme has avoided the critical voltage to appear for the entire drain stress voltage, stress time, and substrate bias range. Detailed computational analysis in conjunction with electroluminescence (EL) and photoluminescence (PL) studies revealed an electric field redistribution due to the p-type nature of AlTiO deposited over the surface passivation/capping layer, which is responsible for relaxed electric field profile in GaN buffer and observed improvement in dynamic performance. Besides, the new observations have further helped to understand the interplay between surface conditions and GaN buffer, defining its collective role in governing the dynamic performance of GaN HEMTs. Finally, various findings and the proposal in this work have been validated for buffers having higher carbon doping and devices with p-type AlTiO deposited over GaN cap instead of in situ SiNx cap. [ABSTRACT FROM AUTHOR]

The aim of this paper is to model the effects of threading dislocations on both gate and drain currents of AlGaN/GaN high electron mobility transistors (HEMTs). The fraction of filled traps increases with the threading dislocations, while the trapping effects cause a decrease in drain current and an increase in gate leakage current. To model the drain current drop, the two simplified RC subcircuits with diodes are proposed to capture the charge trapping/detrapping characteristics. The trap voltages Vg_trap and Vd_trap generated by RC networks are fed back into the model to capture the effects of traps on drain current. Considering acceptor-decorated dislocations, we present a novel Poole–Frenkel (PF) model to precisely describe the reverse leakage gate current, which plays a dominant role in the gate leakage current. The proposed model, which uses physical parameters only, is implemented in Verilog-A. It is in excellent agreement with the experimental data.

In this paper, Silvaco TCAD software is used to simulate the buffer traps in AlGaN/GaN high electron mobility transistors (HEMTs), and its effects on the breakdown performance and key parameters of the devices are investigated by changing the position and concentration of the acceptor traps in the buffer layer. The results show that with the increase of trap concentration, the traps capture electrons and reduce the off-state leakage current, which can improve breakdown voltage of the devices. At the same time, as the trap concentration increases, the ionized traps make a high additional electric field near the drain edge, leading to the decrease of breakdown voltage. With the combined two effects above, the breakdown voltage almost ultimately saturates. When the source-to-gate (Access-S) region in the GaN buffer layer is doped alone, the minimum and most linear leakage current for the same trap concentrations are obtained, and the additional electric field has a relatively small effect on the electric field peak near the drain as the ionized traps are furthest from drain. All these factors make the breakdown voltage increase more controllably with the Access-S region doping, and it is a more potential way to improve the breakdown performance.

In this letter, a novel approach is presented to overcome issues in AlGaN/GaN high electron mobility transistors (HEMTs), such as metal discontinuity of the gate stemmed from conventional mesa isolation. This usually requires a careful mesa etch process to procure an anisotropic mesa-wall profile. An alternative technique is the use of ion implantation for device isolation instead of conventional mesa for a planar device formation. However, ion implantation is a costly process and not always easily accessible. In this work, the proposed method is to simply extend the mesa below the gate just enough to accommodate the gatefeed, thereby ensuring the entire gate is planar in structure up to the gatefeed. The newly developed device exhibited no compromise to the DC (direct current) and RF (radio frequency) performance. Conversely, it produced a planar gate configuration with an enhanced DC transconductance (approximately 20% increase is observed) and a lower gate leakage while the etch process is considerably simplified. Similarly, the RF transconductance of proposed device (device B) increased by 80% leading to considerable improvements in RF performance.

This article proposes a parallel dual‐metal‐gate structure (PDM) of AlGaN/GaN high‐electron‐mobility transistors (HEMTs) for high‐linearity applications. Cancellation of the third‐order derivative of the Ids–Vgs curve (gm″)is achieved by splitting the device into two subcells in parallel with different gate metals. The two subcells have different threshold voltages. When the same bias voltage Vgs is applied, the operating states of the two subcells are independently controlled by the gate bias voltages. The maximum transconductance (gm,peak) of the conventional single‐metal‐gate (SMG) HEMT, double‐metal‐gate (DMG) HEMT, and PDM‐HEMT is all comparable, whereas gm″ of the proposed structure is 75% lower than that of the SMG HEMT and 47.8% lower than that of the DMG HEMT. The effects of the differences and width ratios of the work function on gm″ are studied and compared, and a suitably designed PDM‐HEMT that can considerably improve linearity without degrading other performance aspects is obtained. This research has significant implications for high‐linearity applications. [ABSTRACT FROM AUTHOR]

In this paper, the full‐wave electromagnetic (FW‐EM) simulation approach for scalable small‐signal modeling of the GaN HEMT device is proposed. The scalable rules are deduced from the extracted parasitic parameters, which is according to a step‐by‐step parameter extraction method. Moreover, the accuracy is enhanced by considering the temperature‐dependent resistance (TDR) Rs and Rd, which are calculated by combining a universal thermal resistance model and the Rs and Rd under the pinch‐off condition. In the end, a set of GaN HEMT with a gate length of 0.25 μm is used for validation, and the experimental results show that good agreements have been achieved between the measured and the simulated scattering (S) parameters. [ABSTRACT FROM AUTHOR]

The breakdown voltage model of Si-substrated AlGaN/GaN HEMTs with gate and drain field plates is proposed in this work. The silicon substrate and GaN buffer are considered as the depletion region in the modeling process. The analytical model shows great simplicity and veracity. It gives physical insights into the breakdown characteristics of the AlGaN/GaN HEMTs. The avalanche breakdown occurs at the field plate's edge in lateral structure or at the interface in vertical structure. According to the analytical model, the relationship between the lateral breakdown and the vertical breakdown is demonstrated in this work. The breakdown location is affected by the variation of the structure parameters, including gate-to-drain distance, buffer thickness and field plates' lengths. With the aid of the analytical model, effective guidance for device optimization to achieve high performance can be obtained.

We present a simple but accurate 1-D methodology of modeling for AlGaN/GaN High Electron Mobility Transistors (HEMTs), and by which means study its Reduced Surface Field (RESURF) effect. By using the Effective Concentration Profile Concept, the proposed methodology accounts the interactions between each layer and electric field crowding induced by gate/drain electrodes simultaneously without introducing any simulation results and correction factors. The proposed model indicates that same as that in silicon-based lateral power devices, the RESURF effect is also present in AlGaN/GaN HEMTs. Thus, the channel layer doping of AlGaN/GaN HEMTs plays a leading role in determining the devices' off-state characteristics. Owing to the veracity and simplicity of the proposed model, in this paper, the devices' breakdown voltage and RESURF criterion are analytically obtained via a 1-D approach for the first time. The good agreements between the analytical model, experimental results, and 2-D simulations verify the validity of the proposed methodology.

Nanocrystalline diamond capping layers have been demonstrated to improve thermal management for AlGaN/GaN HEMTs. To improve the RF devices, the application of the technology, the technological approaches and device characteristics of AlGaN/GaN HEMTs with gate length less than 0.5 μm using nanocrystalline diamond capping layers have been studied systematically. The approach of diamond-before-gate has been adopted to resolve the growth of nanocrystalline diamond capping layers and compatibility with the Schottky gate of GaN HEMTs, and the processes of diamond multi-step etching technique and AlGaN barrier protection are presented to improve the technological challenge of gate metal. The GaN HEMTs with nanocrystalline diamond passivated structure have been successfully prepared; the heat dissipation capability and electrical characteristics have been evaluated. The results show the that thermal resistance of GaN HEMTs with nanocrystalline diamond passivated structure is lower than conventional SiN-GaN HEMTs by 21.4%, and the mechanism of heat transfer for NDC-GaN HEMTs is revealed by simulation method in theory. Meanwhile, the GaN HEMTs with nanocrystalline diamond passivated structure has excellent output, small signal gain and cut-off frequency characteristics, especially the current–voltage, which has a 27.9% improvement than conventional SiN-GaN HEMTs. The nanocrystalline diamond capping layers for GaN HEMTs has significant performance advantages over the conventional SiN passivated structure.

In the current study, the effects of cracks in source field plates (SFPs) on the electrical performance of AlGaN/GaN high electron mobility transistors (HEMTs) are investigated systematically using numerical simulation. In detail, the influence of crack width and junction angle in SFPs on device performance is studied. The results indicate that the SFP structure increases the breakdown voltage of a device, but the occurrence of cracks causes premature breakdown, which is confirmed experimentally by the structural analysis of these devices after breakdown. With an increase in crack width, the electrical performance becomes worse. A beveled SFP architecture is proposed by increasing the angle at the SFP junction to reduce the probability of cracking and enhance the reliability of the device. However, with an increase in bevel angle, the modulation effect of the SFP on the channel electric field is gradually weakened. Therefore, it is necessary to balance the relationship between electrical performance and bevel angle according to the actual demands. This work provides potential support for SFP structural optimization design for AlGaN/GaN HEMTs.

An improved hybrid parameter‐extraction technique is proposed for the small‐signal modeling application in AlGaN/GaN high electron mobility transistors (HEMTs). The capacitance partitioning characteristics of cold pinch‐off GaN device with non‐field‐plate and field‐plate structures are reinvestigated and the scanning range of parasitic capacitances Cpg and Cpd is determined. A systematic optimization approach is proposed to obtain the initial values of Cpg and Cpd. By using the global optimization algorithm, particle swarm optimization, the reliable parasitic parameters can be acquired based on the proposed error function. The validity of the developed hybrid parameter‐extraction method is verified by 2 × 100 μm AlGaN/GaN HEMT with source‐connected FP structure from 0.1 to 40 GHz among the 442 biasing points. [ABSTRACT FROM AUTHOR]

Physical insights into the complex interplay of surface and (GaN) buffer traps governing breakdown characteristics of AlGaN/GaN HEMTs are developed by well-calibrated TCAD simulations. Impact of surface traps in correlation with 1) acceptor traps in case of Fe doping and 2) self-compensating traps (corresponding to C doping) in the GaN buffer on breakdown characteristics of AlGaN/GaN HEMTs is discussed. The explorations include defect-related traps as well as traps induced by intentional buffer doping by carbon/iron. The computational findings corroborate well with the experimentally observed electric field profile for devices with different buffer doping conditions. Developed insights have allowed to discuss the collective impact of surface as well as buffer traps on device design to improve breakdown characteristics. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate that a physics-based compact model can facilitate to analyze the reliability using an example of γ-ray induced instability in AlGaN/GaN HEMTs. First, the typical AlGaN/GaN HEMTs are subjected to the cumulative γ-ray irradiation, exhibiting the drain current (ID) increase. In order to further elucidation, the root cause, the compact model is implemented and calibrated with the pristine case. Then, ID – VG and ID – VD characteristics subjected to the γ-ray irradiation are fitted with the compact model. The extracted μ and Rc are consistent with the results obtained by the Hall measurement and circular transmission line measurement (C-TLM). By comparing the fitted curves with considering: 1) fitted μ (Rc is fixed as the pristine case) and 2) fitted Rc (μ is fixed as the pristine case), the shift of μ is identified as the root cause leading to the ID increase because of the better fitting results. Therefore, with the assistance of the physics-based compact model, the shift of the parameter can be further analyzed to understand the origin of the instability. [ABSTRACT FROM AUTHOR]

To improve the performance of AlGaN/GaN high electron mobility transistors (HEMTs) after exposure to high energy irradiation, 4-nm polycrystalline AlN (poly-AlN) film formed by annealing at 850 °C is proposed to passivate the GaN cap layer. After exposure to 3-MeV proton irradiation with a fluence of $3 \times 10^{14}$ cm−2, the ON-resistances ($R_{\mathrm{\scriptscriptstyle ON}}$) of AlGaN/GaN MIS-HEMTs with SiNx and poly-AlN passivation increase by 28% and 32%, and the dynamic ON-resistances ($R_{d,\mathrm{\scriptscriptstyle ON}}$) degrade by 2000% and 110% with a 30-V OFF-state and a 5-V ON-state drain bias, respectively. The polarization effect of poly-AlN reduces the energy band of the GaN cap layer and compensates for deep-level surface defects, moreover, the growth of AlN by atom layer deposition with low plasma power make the GaN surface smooth, which contributes to the reliability improvement of AlGaN/GaN HEMTs after the proton-irradiation. [ABSTRACT FROM AUTHOR]

The breakdown voltage of GaN/Si high-electron-mobility transistors (HEMTs) for power electronics has shown to be improved by removing the silicon substrate. The drawback to this approach is the increase in the device’s thermal resistance, which limits the power dissipation that the device can achieve before severe degradation. This letter shows the ability to improve the thermal dissipation of these devices by depositing copper (Cu) below aluminum nitride (AlN) filled etched back GaN-on-Si HEMTs. The device’s channel temperature is measured via Raman thermometry. The device’s transient thermal dynamics is investigated via transient thermoreflectance imaging, and the temperature profile across the gate metal is monitored. In addition to the device’s thermal properties, a residual stress analysis of the GaN channel is performed via photoluminescence. A notable decrease in the tensile residual stress is observed with the removal of the substrate and the addition of the AlN and Cu layers. Overall, the backside copper is shown to decrease the gate temperature of the etched backed AlN filled devices while maintaining a high breakdown voltage. [ABSTRACT FROM AUTHOR]

This paper reviews the physical breakdown mechanisms of Si-, SiC- and GaN-based power semiconductor devices. In the off-state in which Si-based Lateral Double-diffused MOS (LDMOS), SiC-based Schottky Barrier Diode (SBD), the PN junction and gate Schottky junction are reverse-biased, avalanche breakdown is responsible for the breakdown. For AlGaN/GaN high electron mobility transistors (HEMTs), due to the absence of a PN junction, there exist four breakdown mechanisms: (i) the high gate-leakage-current components, either through the surface-hopping conduction mechanism or through the vertical Schottky barrier, (ii) the impact-ionization-induced Schottky junction avalanche breakdown, whose positive temperature dependence of the breakdown voltage is a typical signature, (iii) the source–drain leakage current through the GaN buffer, owing to poor confinement and high N-type doping, and (iv) vertical breakdown, which can be particularly pronounced when AlGaN/GaN HEMTs are grown on an Si substrate. Avalanche breakdown and GaN buffer-leakage-current-induced breakdown are deeply investigated. Through Integrated Systems Engineering (ISE) simulation, the effects of the breakdown voltage on different GaN buffer layer concentrations and thicknesses were obtained. Finally, novel AlGaN/GaN HEMTs with a partially etched AlGaN layer have been fabricated. The test curves indicate that avalanche breakdown governs the breakdown when the GaN buffer layer is lightly N-type doped and thinner. The paper provides a reference in designing and achieving AlGaN/GaN HEMTs with high breakdown voltages. [ABSTRACT FROM AUTHOR]

Abstract Here, we study the mechanism of AlGaN/GaN HEMT with the partial silicon doping in the AlGaN layer under reverse bias and propose a two-dimensional analytic model for this device. The local density of two-dimensional electron gas (2DEG) increase at the interface between the AlGaN and GaN buffer due to partial silicon positive charge. And a new electric field peak is introduced by electric field modulation effect, which makes the electric field distribution of the channel surface more uniform and increases the breakdown voltage of the device. An analytical expression for the electric field and potential distribution of the channel is obtained, based on the two-dimensional Poisson's equation with appropriate boundary conditions. With this model, we explain the effects of silicon doping concentration and doping length on channel potential and electric field distribution in detail. By comparing the results obtained by the analytical model with the simulation results of Silvaco TCAD software, the numerical results and simulation results mostly match which verifies the validity of the model and provides a reference to model other AlGaN/GaN HEMTs. Highlights • Analytical models for the electric field and potential of PSD-HEMT is proposed. • The simulation results and model results are well fitted under different device parameters. • The physical mechanism of the electric field modulation effect is explained by analytical expression. • The optimal device structure parameters are proposed by the model. [ABSTRACT FROM AUTHOR]