Search

Correction of the digital designs have emerged as a major bottleneck at Register Transfer Level (RTL) due to the growing complexity of the digital systems and shortening time-to-market. Existing automated correction methods face problems like large number of error root causes, poor scalability, and multiple design errors. To address these problems, we propose an automatic correction methodology based on a lightweight partial high level synthesis (HLS) flow which takes as inputs a golden C specification and a buggy RTL design and outputs the corrected RTL model. Synthesizing the specification using a HLS tool without considering the buggy RTL to obtain the corrected RTL is not the case because manual RTL optimizations done by the designer should be preserved so that the architecture of the corrected RTL design should be as similar as possible to that of the buggy one. The results on industrial large designs show that the proposed methodology achieves 92.3% less new resources and 81.1% less connections compared to synthesizing the golden specification using a HLS tool without considering the architecture of the buggy RTL design. • A lightweight partial high level synthesis mechanism to correct RTL designs. • Preserving manual RTL optimizations done by the designer. • Addressing the large number of error root causes issue. [ABSTRACT FROM AUTHOR]

Hardware Trojan attacks have emerged as a major security issue for hardware at different level of abstractions, which relate to malicious tampering of a hardware during design or fabrication process. In this paper, a new low overhead and high speed design for trust methodology for increasing both full activation and side channel sensitivity of Trojan is proposed. The main idea is that the increase in transition probability of individual nets does not necessarily increase the transition probability of the succeeding nets of the circuit. Accordingly, the rules and conflicts of the propagation of maximum transition probability for individual gates have been presented to ensure that a full transition path is constructed between each low transition probability net and primary inputs of the circuit. The results show that the proposed methodology achieves superior efficiency in Trojan full activation by more than $4 \times $ through logic testing approach besides higher sensitivity averagely around $20 {\times }$ for power-based side channel analysis compared to existing methods. [ABSTRACT FROM AUTHOR]

Good knowledge of internal circuit states are crucial for efficient post-silicon debug. Due to the area, power, routing, and bandwidth limitations trace buffer-based design for debug hardware provides execution traces of a limited number of state elements which are then usually expanded through signal restoration. In this paper, we propose to record combinational execution traces and show that combined with signal restoration better knowledge of internal circuit states are obtained. Our experiment with benchmark circuits show that restoration quality in terms of state restoration ratio is improved up to 48% on average. Extending the solution space by, including combinational gates drastically increases signal selection runtime. Using hybrid signal selection methods, we also provide good tradeoff between restoration quality and runtime. By dynamically updating some metrics in state-of-the-art hybrid selection method, we achieve 65% reduction in runtime with only 2% penalty in solution quality. Using the proposed signal selection algorithms, designers can better explore the circuit states and achieve more efficient post-silicon debug. [ABSTRACT FROM AUTHOR]

In recent years, using distributed fiber-optic sensors based on Brillouin scattering, for monitoring pipelines, tunnels, and other constructional structures have gained huge popularity. However, these sensors have a low signal-to-noise ratio (SNR), which usually increases their measurement error. To alleviate this issue, ensemble averaging is used which improves the SNR but in return increases the measurement time. Reducing the noise by averaging requires hundreds or thousands of scans of the optical fiber; hence averaging is usually responsible for a large percent of the entire system latency. In this paper, we propose a novel method based on artificial neural network for SNR enhancement and measurement acceleration in distributed fiber-optic sensors based on the Brillouin scattering. Our method takes the noisy Brillouin spectrums and improves their SNR by 20 dB, which reduces the measurement time significantly. It also improves the accuracy of the Brillouin frequency shift estimation process and its latency by more than 50% in comparison with the state-of-the-art software and hardware solutions. [ABSTRACT FROM AUTHOR]

Formal methods have been introduced as the efficient approach for Trojan detection using the model checking approach. However, systematic property generation for detecting a wide range of Trojans is the main challenge in these methods. In other words, the efficient property generation to pinpoint projected Trojan precisely in targeted hardware has been a bottleneck in this approach. This paper evaluated the feasibility of the systematic property generation methodology for Trojan detection in Cryptosystems by analyzing the vulnerable points of an implemented design respecting Trojans' covered class. The vulnerability analysis reduces the search space of formal methods and considerably improves the scalability of these methods. We have shown in this research that these properties can be generated systematically and prove that the generated properties can be used in conventional model-checking tools to find hard-to-detect Trojans efficiently. Experimental results show that the proposed method reduces Trojan detection time considerably. Also, the memory required to evaluate circuits is possible for several hundreds of clock cycles. [ABSTRACT FROM AUTHOR]

Engineering Change Order (ECO) at Register Transfer Level (RTL) has been widely investigated by researchers, but at a higher level of abstraction than RTL, it is not properly addressed. Applying ECO using conventional HLS tools may result in a heavily different RTL in comparison with the original one. In order to minimize this difference, we have proposed a new high-level synthesis methodology, which considers the resulting data-path and its difference from the original one during scheduling and binding of the operations. Experimental results show that our proposed methodology makes only 6.9% changes in the connections of the original data-path in contrast to existing HLS tools, which alter 25.16% of the connections on average. Our methodology exploits 66% less spare cells than the existing HLS tools and makes no change in functional units and registers. • Considering metal mask ECO, by restricting changes only to the connections between resources of the original data-path. • Using difference between the new data-path and original as an optimization target during integrated scheduling and binding. • Proposing a heuristic partitioning method to break up the large synthesis problem in order to tackle scalability issue. [ABSTRACT FROM AUTHOR]

As the complexity of digital designs continuously increases, existing methods to ensure their correctness are facing more serious challenges. Although many studies have been provided to enhance the efficiency of debugging methods, they are still suffering from the lack of scalable automatic correction mechanisms. In this paper, we propose a method for correcting multiple design bugs in gate level circuits. To reduce the correction time, an incremental satisfiability-based mechanism is proposed which not only does not require a complete set of test patterns to produce a gate level implementation which does not exhibit erroneous behavior, but also will not reintroduce old bugs after fixing new bugs. The results show that our method can quickly and accurately suggest corrected gates even for large industrial circuits with many bugs. Average improvements in terms of the runtime and memory usage in comparison with existing methods are ${2.8 \times }$ and ${{6.5 \times }}$ , respectively. Also, the results show that our method compared to the state-of-the-art methods needs ${{2.6 \times }}$ less test patterns. [ABSTRACT FROM AUTHOR]

In range analysis (RA), suitable integer bit-widths are assigned to the variables so that no overflow occurs. Although the accuracy in RA rather than error analysis has more impact on hardware cost and efficiency, there are few works that offer new approaches to improve RA. Arithmetic functions, mostly represented by polynomials, are normally suitable for both optimization and verification purposes. In this paper, a safe and more accurate RA of feed-forward fixed-point polynomial data-flow graphs is proposed. The method employs particular features of RA and maps it to a specific class of polynomial optimization problems. The proposed method provides tighter ranges while taking less runtime in comparison with satisfiability-modulo theory-based method. Furthermore, the improved ranges lead to enhance the area and delay efficiency more than 50% and 24%, respectively, when the circuits are implementing the functions in comparison with the state-of-the-art techniques. [ABSTRACT FROM PUBLISHER]

This paper presents a formal technique to verify and debug division circuits on fixed point numbers. The proposed technique is based on a reverse-engineering mechanism of obtaining a high level model of the gate level implementation and also introducing an intermediate representation of the specification that makes equivalence checking between two models possible. The main advantage of this representation is the fact that the specification is dynamically updated according to the information obtained from the implementation. At the end, if two updated models are not equivalent, possible bugs can be localized and then corrected automatically by analyzing the difference, if possible. Experimental results show the robustness of the proposed technique in comparison with other contemporary methods in terms of the run time and also show that two orders of magnitude average speedup is obtained. [ABSTRACT FROM AUTHOR]

Traditionally, FPGA designers make use of CAD tools for evaluating architectures in terms of the area, delay and power. Recently, analytical methods have been proposed to optimize the architectures faster and easier. A complete analytical power, area and delay model have received little attention to date. In addition, previous works use analytical methods to optimize general-purpose FPGA architectures. Using analytical models for optimizing application-specific FPGA architectures are interesting subjects in the reconfigurable computing field. In this way, designers can investigate the optimized architecture for a set of application circuits and the consumers can find their best architecture among a variety of devices which is optimal for their specific work. In this paper, we complete an analytical FPGA performance model by presenting an analytical model to estimate the dynamic and leakage power and by integrating it into the geometric programming framework. This way, we are able to rapidly analyze various FPGA architectures and select the best one in terms of power consumption as well as area and delay. In the next step, we extend the model for optimizing FPGA architectures for a set of applications. A case of the best architecture for two specific circuits has been investigated in this paper. [ABSTRACT FROM AUTHOR]

By increasing the complexity of digital systems, verification and debugging of such systems have become a major problem and economic issue. Although many computer aided design (CAD) solutions have been suggested to enhance efficiency of existing debugging approaches, they are still suffering from lack of providing a small set of potential error locations and also automatic correction mechanisms. On the other hand, the ever-growing usage of digital signal processing (DSP), computer graphics and embedded systems applications that can be modeled as polynomial computations in their datapath designs, necessitate an effective method to deal with their verification, debugging and correction. In this paper, we introduce a formal debugging approach based on static slicing and dynamic ranking methods to derive a reduced ordered set of potential error locations. In addition, to speed up finding true errors in the presence of multiple design errors, error candidates are sorted in decreasing order of their probability of being an error. After that, a mutation-based technique is employed to automatically correct bugs even in the case of multiple bugs. In order to evaluate the effectiveness of our approach, we have applied it to several industrial designs. The experimental results show that the proposed technique enables us to locate and correct even multiple bugs with high confidence in a short run time even for complex designs of up to several thousand lines of RTL code. [ABSTRACT FROM PUBLISHER]

This paper concentrates on high-level data-flow optimization and synthesis techniques for datapath intensive designs such as those in Digital Signal Processing (DSP), computer graphics and embedded systems applications, which are modeled as polynomial computations over Z2^{n_1 } \times Z2^{n_2 } \times \cdots \times Z2^{n_d } to Z2^m . Our main contribution in this paper is proposing an optimization method based on functional decomposition of multivariate polynomial in the form of f(x) = g(x) \;o \;h(x) + f0 = g(h(x)) + f0 to obtain good building blocks, and vanishing polynomials over Z2^m to add/delete redundancy to/from given polynomial functions to extract further common sub-expressions. Experimental results for combinational implementation of the designs have shown an average saving of 38.85 and 18.85 percent in the number of gates and critical path delay, respectively, compared with the state-of-the-art techniques. Regarding the comparison with our previous works, the area and delay are improved by 10.87 and 11.22 percent, respectively. Furthermore, experimental results of sequential implementations have shown an average saving of 39.26 and 34.70 percent in the area and the latency, respectively, compared with the state-of-the-art techniques. [ABSTRACT FROM PUBLISHER]

Verification of arithmetic circuits is essential as they form the main part of many practical designs such as signal processing and multimedia applications. In these applications, the size of the datapath could be very large so that contemporary verification methods would be almost incapable of verifying such circuits in reasonable time and memory usage. This paper addresses formal verification of large integer arithmetic circuits using symbolic computer algebra techniques. In order to efficiently verify gate level arithmetic circuits, we model the circuit and the specification with polynomial system and the verification problem is formulated as membership testing of the given specification polynomial in corresponding ideal of the circuit polynomials. The membership testing needs Groebner basis reduction. In order to overcome the intensive polynomial reduction needed in Groebner basis computation so that we can deal with verifying large arithmetic circuits, the fanout-free regions (cones) of the circuit are extracted and represented as corresponding polynomials automatically. For further improvement, we make use of Gaussian elimination concept to perform specification polynomial reduction w.r.t Groebner basis using a matrix representation of the problem. To evaluate the effectiveness of our verification technique, we have applied it to very large arithmetic circuits with different architectures. The experimental results show that the proposed verification technique is scalable enough so that large arithmetic circuits can efficiently be verified in reasonable run time and memory usage. [ABSTRACT FROM AUTHOR]

By increasing the complexity of system on chip (SoC) designs formal equivalence verification and debugging have become more and more important. Lower level methods such as BDDs and SAT solvers suffer from space and time explosion problems to match sizes of industrial designs in formal equivalence verification and debugging. This paper proposes techniques to verify and debug datapath intensive designs based on a canonical decision diagram called Horner Expansion Diagram (HED). It allows us to check the equivalence between two models in different levels of abstraction, e.g., a Register Transfer Level (RTL) implementation and a non-cycle-accurate specification. In order to reduce the complexity of equivalence checking problem, we tackle the exponential path enumeration problem by automatically identifying internal equivalent conditional expressions as well as suitable merge points. Our debugging technique is based on introducing mutations into the buggy implementation and then observing if the specification is capable of detecting these changes. We make use of a simple heuristic to reduce the number of mutants when dealing with multiple errors. We report the results of deploying our equivalence verification technique on several industrial designs which show 16.8× average memory usage reduction and 8.0× speedup due to merge-point detection. Furthermore, our debugging technique shows 13.7× average memory usage reduction and 4.6× speedup due to using SMT solvers to find equivalent conditions. In addition, the proposed debugging technique can avoid the computation of unnecessary mutants so that the results show 2.9× average reduction of the number of mutants to be processed. [ABSTRACT FROM AUTHOR]

This paper proposes an automatic design flow of datapath-dominated applications which is able to deal with optimization and equivalence checking of multi-output polynomials over Z2. This paper also gives four main contributions: 1) proposing a complete design flow for modular equivalence checking, high level synthesis, and optimization; 2) considering hidden monomials to factorize those polynomials which do not have any common monomials; 3) combining and improving our previous optimization heuristics to eliminate multi-operand common sub-expressions as much as possible; and 4) implementing all algorithms on top of the modular Horner expansion diagram package. Experimental results have shown an average saving of 9.9% and 4.5% in the number of gates and critical path delay, respectively, after applying modular reduction over Z2, while other optimization techniques are not used. Besides, after applying our optimization techniques, experimental comparisons with the state-of-the-art techniques show an average improvement in the area by 19.5% with an average delay decrease of 16.7%. Regarding the comparison with our previous papers, the area and delay are improved by 13.3% and 15.5%, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a high-level test generation method which considers the control part as well as data path of a register transfer level circuit as a set of polynomial functions to generate behavioral test patterns from faulty behavior instead of comparing the faulty and fault-free circuits based on a hybrid Boolean-word canonical representation called Horner expansion diagram. Since this set of polynomial functions express primary outputs and next states with respect to primary inputs and present states, it is not necessary to perform justification/ propagation phase which leads to a minimum number of backtracks. It improves fault coverage and reduces test generation time over logic-level techniques. We assess then the effectiveness of high-level test generation with a simple gate-level automatic test pattern generation algorithm. Experimental results show robustness and reliability of our method compared to other contemporary approaches in terms of fault coverage and CPU time. [ABSTRACT FROM AUTHOR]

This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, XOR extraction, and carry-signal mapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted XORs into half/full-adders to make a very fast debugging algorithm. This approach is robust under multioperand adders, pin-swap techniques, optimizations concerning carry signals or XOR terms, and irregularities, such as commutative and associative laws. Moreover, the XOR extraction in the proposed algorithm is much faster than conventional techniques, as it does not evaluate the whole netlist. The bugs delected in the partial product initialization and the carry-signal mapping can automatically be replaced with proper logics. However, during the XOR extraction phase, the problematic XORs are only reported by the algorithm, and no automatic replacement is performed for such logic gates. To evaluate the effectiveness of our approach, we run it on several arithmetic circuits. [ABSTRACT FROM AUTHOR]