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This paper provides a perspective on progress toward realization of efficient, fully integrated dc–dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc–dc converters of both the inductor-based and SC types. [ABSTRACT FROM AUTHOR]

This paper presents techniques for characterizing wide-band on-chip power supply noise using only two on-chip low-throughput samplers. The properties of supply noise and their associated measurement techniques are reviewed to show how this can be achieved. An initial design of the samplers uses high-resolution VCO-based analog-to-digital converters, and experimental results from a test-chip verify the efficacy of the measurement techniques. To enable simple sampler designs to be used even in aggressively scaled process technologies, measurement systems based on dithered low-resolution samplers are also developed and experimentally characterized. [ABSTRACT FROM AUTHOR]

A 61-MHz Pierce oscillator constructed in 0.35- $\mu \text{m}$ CMOS technology and referenced to a polysilicon surface-micromachined capacitive-gap-transduced wine-glass disk resonator has achieved phase noise marks of −119 dBc/Hz at 1-kHz offset and −139 dBc/Hz at far-from-carrier offsets. When divided down to 13 MHz, this corresponds to −132 dBc/Hz at 1-kHz offset from the carrier and −152 dBc/Hz far-from-carrier, sufficient for mobile phone reference oscillator applications, using a single MEMS resonator, i.e., without the need to array multiple resonators. Key to achieving these marks is a Pierce-based circuit design that harnesses a MEMS-enabled input-to-output shunt capacitance more than $100\times $ smaller than exhibited by macroscopic quartz crystals to enable enough negative resistance to instigate and sustain oscillation while consuming only $78~\mu \text{W}$ of power—a reduction of $\sim 4.5\times $ over previous work. Increasing the bias voltage of the resonator by 1.25 V further reduces power consumption to $43~\mu \text{W}$ at the cost of only a few decibels in far-from-carrier phase noise. This oscillator achieves a 1-kHz-offset figure of merit (FOM) of −231 dB, which is now the best among published chip-scale oscillators to date. A complete linear circuit analysis quantifies the influence of resonator input-to-output shunt capacitance on power consumption and predicts further reductions in power consumption via reduction of electrode-to-resonator transducer gaps and bond pad sizes. The demonstrated phase noise and power consumption posted by this tiny MEMS-based oscillator are attractive as potential enablers for low-power “set-and-forget” autonomous sensor networks and embedded radios. [ABSTRACT FROM AUTHOR]

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy–performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/\2)(Seff/Soff) - \0.56(Son/Soff) - \0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy–delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology. [ABSTRACT FROM AUTHOR]

A single-output, band selecting interposer is designed to combine three identical all-digital CMOS transmitter (Tx) chips. The open-drain CMOS Txs are flip-chip connected to the primary windings of three frequency selecting transformers realized on a single PCB interposer. The secondary windings of the three transformers are connected in series and they share a single output. Across 0.4 to 4 GHz, a peak power higher than 22.9 dBm is achieved collectively by the three sub-Txs with a drain efficiency (DE) better than 25%. The peak powers/DE of the three sub-Txs are 28.6 dBm/50%, 27.4 dBm/49%, and 24.7 dBm/34%, at 0.85, 2.1, and 3 GHz, respectively. This paper further demonstrates that the band selection can be achieved via reconfiguring the CMOS inverse Class-D switching power amplifiers. As demonstrated via continuous wave and 64-quadratic-amplitude modulation, WLAN, and LTE modulation tests, the reconfigurable Tx package exhibits high power and efficiency across all supported bands. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied. [ABSTRACT FROM AUTHOR]

This paper demonstrates a wideband CMOS all-digital polar transmitter with flip-chip connection to three high-density-interconnection PCB interposers. The interposers are designed to extract power from a CMOS open-drain inverse Class-D power amplifier core. For a wide frequency range from 0.7 to 3.5 GHz, continuous-wave output power higher than 25.5 dBm and drain efficiency (DE) above 40% are demonstrated. The low-band package achieves a peak power of 29.2 dBm at 1.1 GHz with DE of 60%, the mid-band package outputs 28.8 dBm at 1.5 GHz with DE of 56%, and the high-band package generates 26 dBm at 3 GHz with DE of 49%. The amplitude modulation (AM) is achieved by digitally modulating the switch conductance of the inverse Class-D core, and the on-chip phase modulation is achieved by digitally weighing the in-phase and quadrature bias currents in the IQ mixer. Detailed modulation tests, involving 64 quadrature amplitude modulation (QAM) and 20-MHz WLAN and LTE signals, exhibit excellent power and efficiency at 0.6, 1.2, 1.8, 2.4, 3, and 3.6 GHz. The associated specifications on spectral masks and error vector magnitudes are satisfied. [ABSTRACT FROM PUBLISHER]

Summary The emerging field of bioelectronic medicine seeks methods for deciphering and modulating electrophysiological activity in the body to attain therapeutic effects at target organs. Current approaches to interfacing with peripheral nerves and muscles rely heavily on wires, creating problems for chronic use, while emerging wireless approaches lack the size scalability necessary to interrogate small-diameter nerves. Furthermore, conventional electrode-based technologies lack the capability to record from nerves with high spatial resolution or to record independently from many discrete sites within a nerve bundle. Here, we demonstrate neural dust, a wireless and scalable ultrasonic backscatter system for powering and communicating with implanted bioelectronics. We show that ultrasound is effective at delivering power to mm-scale devices in tissue; likewise, passive, battery-less communication using backscatter enables high-fidelity transmission of electromyogram (EMG) and electroneurogram (ENG) signals from anesthetized rats. These results highlight the potential for an ultrasound-based neural interface system for advancing future bioelectronics-based therapies. [ABSTRACT FROM AUTHOR]

The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedule using traditional rigid development flows. This article presents an agile hardware development methodology, which the authors adopted for 11 RISC-V microprocessor tape-outs on modern 28-nm and 45-nm CMOS processes in the past five years. The authors discuss how this approach enabled small teams to build energy-efficient, cost-effective, and industry-competitive high-performance microprocessors in a matter of months. Their agile methodology relies on rapid iterative improvement of fabricatable prototypes using hardware generators written in Chisel, a new hardware description language embedded in a modern programming language. The parameterized generators construct highly customized systems based on the free, open, and extensible RISC-V platform. The authors present a case study of one such prototype featuring a RISC-V vector microprocessor integrated with a switched-capacitor DC-DC converter alongside an adaptive clock generator in a 28-nm, fully depleted silicon-on-insulator process. [ABSTRACT FROM AUTHOR]

A major hurdle in brain–machine interfaces (BMI) is the lack of an implantable neural interface system that remains viable for a substantial fraction of the user's lifetime. Recently, sub-mm implantable, wireless electromagnetic (EM) neural interfaces have been demonstrated in an effort to extend system longevity. However, EM systems do not scale down in size well due to the severe inefficiency of coupling radio-waves at those scales within tissue. This paper explores fundamental system design trade-offs as well as size, power, and bandwidth scaling limits of neural recording systems built from low-power electronics coupled with ultrasonic power delivery and backscatter communication. Such systems will require two fundamental technology innovations: (1) 10–100 μm scale, free-floating, independent sensor nodes, or neural dust , that detect and report local extracellular electrophysiological data via ultrasonic backscattering and (2) a sub-cranial ultrasonic interrogator that establishes power and communication links with the neural dust. We provide experimental verification that the predicted scaling effects follow theory; (127 μm) 3 neural dust motes immersed in water 3 cm from the interrogator couple with 0.002064% power transfer efficiency and 0.04246 ppm backscatter, resulting in a maximum received power of ∼0.5 μW with ∼1 nW of change in backscatter power with neural activity. The high efficiency of ultrasonic transmission can enable the scaling of the sensing nodes down to 10s of micrometer. We conclude with a brief discussion of the application of neural dust for both central and peripheral nervous system recordings, and perspectives on future research directions. [ABSTRACT FROM AUTHOR]

We report a mechanically enhanced inkjet-printed microelectromechanical (MEM) relay with a U-bar-shaped cantilever by exploiting the coffee-ring effect. The printed cantilever shape, especially the effective thickness caused by the elevated walls, can be controlled during the drying process by outward convective flow of silver nanoparticles. This enhances mechanical stiffness to efficiently produce a strongly suspended cantilever that is immune to collapse- and curling-related failures. This approach to enhancing cantilever stiffness is unique to printing-based processes using metalnanoparticle inks and is not feasible for conventional photolithography processes. The resulting printed MEM relays show a pull-in voltage of only 6.6 V and an on/off ratio of 108 with extremely low on-state resistance (~14.3 Ω) and off-state leakage that is comparable to those of conventional silicon-based MEM relays. [ABSTRACT FROM AUTHOR]

We report a mechanically enhanced inkjet-printed microelectromechanical (MEM) relay with a U-bar-shaped cantilever by exploiting the coffee-ring effect. The printed cantilever shape, especially the effective thickness caused by the elevated walls, can be controlled during the drying process by outward convective flow of silver nanoparticles. This enhances mechanical stiffness to efficiently produce a strongly suspended cantilever that is immune to collapse- and curling-related failures. This approach to enhancing cantilever stiffness is unique to printing-based processes using metalnanoparticle inks and is not feasible for conventional photolithography processes. The resulting printed MEM relays show a pull-in voltage of only 6.6 V and an on/off ratio of 108 with extremely low on-state resistance (--14.3 Ω) and off-state leakage that is comparable to those of conventional silicon-based MEM relays. [ABSTRACT FROM AUTHOR]

Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage (Vdd) and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy–delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2 \times energy increase can be traded off for a \sim\!\!\1.5\times reduction in relay delay. A contact-gap-to-actuation-gap thickness ratio of 0.7–0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide >\10\times energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to \sim100 MHz. [ABSTRACT FROM AUTHOR]

Various logic functions can be implemented by appropriately biasing a single seesaw relay. The seesaw relay can also be configured as a bistable latch so that a memory cell can be implemented with one relay and one access transistor. Measurements of seesaw relay switching speed are well matched to lumped-parameter modeling results. [ABSTRACT FROM AUTHOR]