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Efficient exact factoring algorithms are limited to read-once (RO) functions, where each variable appears exactly once at the final Boolean expression. However, these algorithms present two important constraints: (1) they do not consider incompletely specified Boolean functions (ISFs), and (2) they are not suitable for binate functions. To overcome the first drawback, an algorithm that finds RO expressions for ISF, whenever possible, is proposed. In respect to the second limitation, we propose a domain transformation that splits existing binate variables into two independent unate variables. Such a domain transformation leads to ISFs, which can be efficiently factored by applying the proposed algorithm. The combination of both contributions gives optimal results for a recently proposed broader class of Boolean functions called read-polarity-once (RPO) functions, where each polarity (positive and negative) of a variable appears at most once in the factored form. Experimental results carried out over ISCAS’85 benchmark circuits have shown that RPO functions are significantly more frequent than RO functions.

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier lowering. Experimental results are on good agreement with HSPICE simulations, showing significant accuracy improvement compared to published related work. The delay model error has an average value of 3%, and the worst case error is smaller than 10%.

Combinational equivalence checking (CEC) has been widely applied to ensure design correctness after logic synthesis and technology-dependent optimization in digital integrated circuit design. CEC runtime is often critical for large designs, even when advanced techniques are employed. Three complementary ways for enabling parallelism in CEC are proposed, addressing different design and verification scenarios. The experimental results have demonstrated the speedups up to $63\times $ when comparing the proposed approach to a single-threaded implementation of a similar CEC engine. A practical impact of such a speedup, for instance, is the runtime reduction from 19 h to only 18 min when checking equivalence of AND-inverter graphs comprising more than 20 million nodes. Therefore, the proposed solution presents great potential for improving current electronic design automation environments.

Editor’s note : The benchmarking of hardware and its comparison to a golden model is an interesting approach for developers and scientists to align their own results to optimal solutions. The article describes an approach and solution to use exact circuits to evaluate own developments, which is crucial in many application domains. Benchmarks are highly important for the scientific community to evaluate their research.-- Michael Hubner, Brandenburg University of Technology

In utero hematopoietic cell transplantation (IUHCT) has the potential to cure congenital hematologic disorders including sickle cell disease. However, the window of opportunity for IUHCT closes with the acquisition of T-cell immunity, beginning at approximately 14 weeks gestation, posing significant technical challenges and excluding from treatment fetuses evaluated after the first trimester. Here we report that regulatory T cells can promote alloengraftment and preserve allograft tolerance after the acquisition of T-cell immunity in a mouse model of late-gestation IUHCT. We show that allografts enriched with regulatory T cells harvested from either IUHCT-tolerant or naive mice engraft at 20 days post coitum (DPC) with equal frequency to unenriched allografts transplanted at 14 DPC. Long-term, multilineage donor cell chimerism was achieved in the absence of graft-versus-host disease or mortality. Decreased alloreactivity among recipient T cells was observed consistent with donor-specific tolerance. These findings suggest that donor graft enrichment with regulatory T cells could be used to successfully perform IUHCT later in gestation.

In general, existing logic synthesis methods for majority logic are limited to 3-input gates (maj-3). However, since majority gates with larger fan-in have been proposed for different emerging nanotechnologies, it has become important to consider such gates in the synthesis process. This paper proposes a novel majority logic synthesis flow where the gates can have an arbitrary number of inputs. The proposed approach is based on the relationship between majority and threshold logic functions. The proposed methods obtain an average reduction of 10% on the number of nodes when compared to a previous work that uses both maj-3 and maj-5 gates. When compared to the previous maj-3 synthesis, the average reduction on number of nodes is 14%.