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Bistability in the current–voltage characteristics of semiconductor superlattices and quantum cascade laser structures has the potential for wide-ranging applications, particularly in sensing systems. However, the interdependency of applied bias and current injection in conventional two-terminal structures has led to complications in analysis and rendered the bistability phenomenon difficult to implement in practical applications. Here, we report a new kind of electronic bistability coupled to optical switching in a resonant tunneling bipolar superlattice transistor. This bistability manifests as sharp discontinuities in the collector current with extremely small variations of the applied voltage, which arise from unstable tunneling transmission across the hetero-barrier between the two-dimensional electron gas (2DEG) at the edge of the transistor base and the collector superlattice structure. The electronic transitions between high and low quantum mechanical transmissions are demonstrated to be caused by self-consistent variations of the internal electric field at the heterointerface between the 2DEG and the superlattice. They are also present in the base current of the three-terminal device and result in sharp switching of near-infrared spontaneous light emission output from an interband radiative recombination process with a peak emission wavelength of 1.58 μ m. A comprehensive quantum mechanical theoretical model accounting for the self-consistent bistable tunneling transmission is in quantitative agreement with the experimental data. The measured peak transconductance sensitivity value of 6000 mS can be used in the highly sensitive detector and non-linear device applications. [ABSTRACT FROM AUTHOR]

The intrinsic carrier density of 4H-SiC at temperatures ranging from 294 to 595 K was derived by analyzing a collector current in an npn-type SiC bipolar junction transistor, the structure of which was designed based on a device simulation. The obtained intrinsic carrier density was in good agreement with the value calculated from the bandgap and effective densities of states taking multiple and non-parabolic SiC bands into account. The coincidence of the intrinsic carrier density obtained by these two different approaches indicates the usefulness of the proposed method and the validity of the evaluated value of intrinsic carrier density. The temperature dependence of the bandgap was also estimated from the deduced intrinsic carrier density and compared with an empirical formula. The derived bandgap agreed well with the empirical formula showing bandgap shrinkage at high temperatures. The errors in evaluating the intrinsic carrier density and the bandgap caused by the estimation of the hole density and electron mobility in the base layer are also discussed for the proposed method. [ABSTRACT FROM AUTHOR]

Due to the erratic switching phenomenon of the Si avalanche bipolar junction transistor (ABJT) in the Marx bank circuit (MBC), an explanation of the leakage current trigger mode in the overvoltage state with a lack of displacement current is proposed. There are random switching properties (i.e., switching or non-switching) in the ABJT with emitter–base shorted, triggered by a voltage ramp to the overvoltage state temporarily with dV/dt rate close to 0 V/ns. The experimental conditions and characteristics of erratic behaviors are summarized. The optical visualization of the current channel in an erratic switching state is obtained, and the corresponding physical model of the leakage current trigger mode is established. It shows that the switching event occurs with the change in the position of the conductive channel. The process of emitter electron injection is caused by the leakage current in the overvoltage state instead of the displacement current. Meanwhile, the intensity of this trigger mode is weak, and the instability of the leakage current may cause the failure of switching. The study of erratic switching is of great significance for the working reliability of MBCs and failure analysis of ABJTs. The proposed explanation is validated by the agreement between the simulation results and the experimental observations. [ABSTRACT FROM AUTHOR]

This research aims to build unique zero voltage transition (ZVT) nonisolated bidirectional DC-DC converters for hybrid electric vehicle battery storage. First, a high-voltage gain bidirectional converter (BDC) is examined. This converter can soft-switch insulated gate bipolar transistors (IGBTs). The primary insulated-gate bipolar transistors (IGBTs) are operated under zero-current conditions throughout the turn-on to turn-off commutation phase to reduce switching losses and increase efficiency. A soft-switched cell with a resonant inductor, capacitor, and additional IGBTs achieves zero-current turn-off. A new converter uses insulated-gate bipolar transistors with zero-voltage transition operation. Soft-switched cells improve the hard-switched bridgeless DC-DC converter (BDC). Resonant inductors, capacitors, and auxiliary switching devices make up the softswitched cell. Soft-switched cells enable zero voltage turn-on of primary insulated-gate bipolar transistors. This converter charges the battery in buck mode and boosts it to provide the necessary output voltage. This study examined a 70 V/300 V power system's high-gain bidirectional converter (BDC) design simulation. The converter was tested at 50 kHz with 800 W output power. The high-gain soft-switched BDC has 96.5% boost and 97% buck efficiency. Operating principles, design analysis, and simulation assessments are included in this study. [ABSTRACT FROM AUTHOR]

Stacking faults in silicon carbide have been widely studied due to their negative impact on the application of silicon carbide in the power electronics industry. In this work, with the assistance of forward biasing, we observe several triangular shaped structures emerging near the indenter imprint in two separate 4H–SiC bipolar junction transistor samples that were deformed by nanoindentation. Based on the study of electroluminescence spectra on one of the samples, the emission peak at 420 nm indicates the formation of single Shockley stacking faults inside deformed transistors. We conclude that the use of indentation can provide a method to study recombination induced stacking faults in silicon carbide junction devices by intentionally introducing dislocations at selected areas of interest. [ABSTRACT FROM AUTHOR]

Summary: A current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV. [ABSTRACT FROM AUTHOR]

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Neutron and γ-ray irradiation damages to transistors are found to be non-additive, and this is denoted as the irradiation synergistic effect (ISE). Its mechanism is not well-understood. The recent defect-based model [Song and Wei, ACS Appl. Electron. Mater. 2, 3783 (2020)] for silicon bipolar junction transistors (BJTs) achieves quantitative agreement with experiments, but its assumptions on the defect reactions are unverified. Going beyond the model requires directly representing the effect of γ-ray irradiation in first-principles calculations, which was not feasible previously. In this work, we examine the defect-based model of the ISE by developing a multiscale method for the simulation of the γ-ray irradiation, where the γ-ray-induced electronic excitations are treated explicitly in excited-state first-principles calculations. We find the calculations agree with experiments, and the effect of the γ-ray-induced excitation is significantly different from the effects of defect charge state and temperature. We propose a diffusion-based qualitative explanation of the mechanism of positive/negative ISE in NPN/PNP BJTs in the end. [ABSTRACT FROM AUTHOR]

In this work, a novel high current capability gallium nitride (GaN) tri-gate power device with an integrated parasitic bipolar junction transistor (BJT) is proposed to enhance its static electrical characteristics. The device's electrical characteristics are thoroughly studied and analyzed using 3D technology computer-aided design simulation tools. The two-dimensional electron gas channel is effectively pinched off in the off-state due to the depletion region induced by side-gate metals and parasitic BJT, resulting in a positive threshold voltage (V TH) and enhanced mode (E-mode) operation. The parasitic BJT provides an additional conductive channel in the on-state, significantly improving the output current capability. Compared with the conventional tri-gate (C-Trigate) device, the proposed high current capability GaN trigate (HC-Trigate) device boosts saturation output current by nearly a factor of three under identical conditions, reaching 1,761 mA mm−1. The 3D simulation shows the proposed GaN HC-Trigate power device features a positive V TH of 1.1 V, a low specific on-resistance (R on,sp) of 0.18 mΩ*cm2 at breakdown voltage of 760 V, and the Baliga's figure of merit of 3.21 GW cm−2. Furthermore, the GaN HC-Trigate power device exhibits superior thermal performance and switching characteristics, indicating its great potential for power electronics applications. [ABSTRACT FROM AUTHOR]

A coupling model is established on piezoelectric semiconductor bipolar junction transistors (PS-BJT) subjected to mechanical loadings by abandoning depletion layer approximation and low injection assumption. Effect of base region on device performance and interaction between emitter/base junction (E/B) and base/collector junction (B/C) are investigated. It is found that too small a base width will cause B/C to extract electrons directly from emitter region, implying that an electron passageway will be excited to link from collector- to emitter-region by striding over base-region (abbreviated as "EP-CE" hereafter). We particularly clarify that the current produced by electrons flowing across EP-CE is independent of electron-hole recombination in E/B, which means that this current has not yet been bestowed on the information of base current. "Information of base current" refers to dispatching information of base current on the electrons in emitter region. Thus, a current from EP-EC cannot be reckoned in the amplification effect of base current. Our investigations show that base width should not be designed too small to avoid EP-CE, which has not been revealed before. As regards to tuning PS-BJT performance by mechanical loadings, we revealed the mechanism as follows: 1) raising electron-hole recombination rate inside E/B to reduce resistivity such that more electrons can be driven from emitter- to base-region; 2) elevating electron conductivity in base-region for easier pass of electrons; 3) promoting attractive ability of B/C on electrons such that more electrons cross the interface. Numerical results show that transmission characteristics can be greatly increased as expected by mechanical tuning. [ABSTRACT FROM AUTHOR]

This paper presents a novel multiple-input single-output current-mode shadow filter and oscillator using current-controlled current conveyors (CCCIIs). The CCCII current gains are used to set the filter's quality factor and natural frequency. The filter is resistorless with grounded capacitors, making it more suitable for integration. The filter offers low-pass, high-pass, band-pass, band-stop and all-pass transfer functions in a single topology by appropriately applying the input signals. To validate the functionality of the new topology, the proposed circuit is simulated by SPICE using bipolar transistors arrays AT&T ALA400-CBIC-R. [ABSTRACT FROM AUTHOR]

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application. [ABSTRACT FROM AUTHOR]

Under fatigue load, insulated gate bipolar transistor (IGBT) experience structural damage and performance degradation, imparting the reliability of power electronic systems. To address this, the relationship between solder layer fatigue crack length and thermal resistance is derived based on heat transfer theory, firstly. The Darveaux model is used to characterize the evolution law of solder layer cracks in IGBT, and a new IGBT performance degradation model along with a method for estimating its undetermined coefficients is proposed. Then, considering the non-stationary characteristics of actual working conditions, a variable amplitude fatigue load model for IGBT is established using the response surface methodology. The rain flow counting method and linear cumulative damage citation are then employed to assess the extent of IGBT performance degradation. Finally, using a type of IGBT product as an example, power cycling thesis are conducted, and performance degradation modeling and analysis are carried out based on experimental data, verifying the effectiveness of the models and algorithms. [ABSTRACT FROM AUTHOR]

The LM2990-integrated circuit family was among the first low-dropout voltage regulators to use a coupling diode to reduce a quiescent current. In certain conditions, the coupling diode, connected between the output terminal and the driver transistor collector contact, activates to supply the serial power transistor base current from the load. Nonetheless, an indirect characterization of the serial NPN transistor was affected, making it difficult to estimate its forward emitted current gain and a base current as a function of the absorbed total ionizing dose. The original SPICE simulation model had some limitations with generating the faithful simulation of radiation effects in samples supplied with a non-ideal voltage source. Therefore, a novel four-step computer simulation method was developed to specify bias and load conditions when the coupling diode reaction would not negatively affect the characterization of the serial power transistor. The previously reported method for estimating the serial transistor base current could be successfully used for dropout voltages that slightly exceed three equivalent diode voltage drops (that is, 2.4V) at the base-emitter junctions of the output amplifier transistors. [ABSTRACT FROM AUTHOR]

This paper proposes a new DC–DC bipolar resonance converter that combines a dual‐active‐bridge and a multi‐port resonance Buck‐Boost converter. This structure uses a resonance network between the input and output ports, which has the following advantages: it creates a constant current supply in the open‐loop mode; it keeps the current phase of the output ports constant under different loads; and it allows reversing the power from any output port by adjusting the phase shift of its switches, if the converter is connected to a DC microgrid. In this way, power can be exchanged among each of the output ports and input ports. The advantages of this converter are bidirectional power exchange, power exchange between output ports, soft switching, high efficiency, integration of transformer parasitic elements, and the modular capability to connect multiple resources at the input. Furthermore, the proposed structure of the bipolar converter has been implemented for verification purposes, and its results are presented in three modes: open loop, voltage control, and current control. Additionally, the results of different modes of power sharing and their bidirectionally are shown. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated stacked architecture to address the challenges of 6G application using CMOS analog pre-distortion and tunable neutralization techniques. By using this method for the stacked power amplifier design, a baseband and passband impedance transformation is achieved, that combined with the stacked power amplifier architecture allows for high efficiency in deep back off, with a reduced load modulation for high bandwidth. This project designs an efficient Stacked Power Amplifier (PA) for 6G. The power amplifier is implemented in 180nm CMOS technology using Cadence and ADS tool. The usage of a diode pre-distorter for analog pre-distortion is investigated for the stacked power amplifier design. It is shown that the linearity of the stacked power amplifier has been significantly improved compared to a bipolar transistor at almost no additional layout size. This research work presents design of a Ka band power amplifier for sixth generation (6G) mobile communication in CMOS design. The stacked power amplifier consists of two different stages of architecture. With 5-volt supply, the stacked power amplifier achieves a small-signal gain of 16 dB, saturated output power (Psat) of 18 dBm, and achieves the maximum power added efficiency of 34.79%. The amplifier has been designed in 180-nm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents an innovative technique, Advanced Predictor of Electrical Parameters, based on machine learning methods to predict the degradation of electronic components under the effects of radiation. The term degradation refers to the way in which electrical parameters of the electronic components vary with the irradiation dose. This method consists of two sequential steps defined as 'recognition of degradation patterns in the database' and 'degradation prediction of new samples without any kind of irradiation'. The technique can be used under two different approaches called 'pure data driven' and 'model based'. In this paper, the use of Advanced Predictor of Electrical Parameters is shown for bipolar transistors, but the methodology is sufficiently general to be applied to any other component. [ABSTRACT FROM AUTHOR]

With the rapid development of the Internet of Things (IoTs), wearable sensors are playing an increasingly important role in daily monitoring of personal health and wellness. The signal-to-noise-ratio has become the most critical performance factor to consider. To enhance it, on the one hand, good sensing materials/devices have been employed; on the other hand, signal amplification and noise reduction circuits have been used. However, most of these devices and circuits work in an active sampling mode, requiring frequent data acquisition and hence, entailing high-power consumption. In this scenario, a flexible and wearable event-triggered sensor with embedded signal amplification without an external power supply is of great interest. Here, we report a flexible two-terminal piezotronic n-p-n bipolar junction transistor (PBJT) that acts as an autonomous and highly sensitive, current- and/or voltage-mediated pressure sensor. The PBJT is formed by two back-to-back piezotronic diodes which are defined as emitter-base and collector-base diodes. Upon force exertion on the emitter side, as a result of the piezoelectric effect, the emitter-base diode is forward biased while the collector-base diode is reverse biased. Due to the inherent BJT amplification effect, the PBJT achieves record-high sensitivities of 139.7 kPa-1 (current-based) and 88.66 kPa-1 (voltage-based) in sensing mode. The PBJT also has a fast response time of <110 ms under exertion of dynamic stimuli ranging from a flying butterfly to a gentle finger touch. Therefore, the PBJT advances the state of the art not only in terms of sensitivity but also in regard to being self-driven and autonomous, making it promising for pressure sensing and other IoT applications. [ABSTRACT FROM AUTHOR]

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times. [ABSTRACT FROM AUTHOR]

Two-dimensional layered materials, characterized by their atomically thin thicknesses and surfaces that are free of dangling bonds, hold great promise for fabricating ultrathin, lightweight, and flexible bipolar junction transistors (BJTs). In this paper, a van der Waals (vdW) BJT was fabricated by vertically stacking MoS2, WSe2, and MoS2 flakes in sequence. The AC characteristics of the vdW BJT were studied for the first time, in which a maximum common emitter voltage gain of around 3.5 was observed. By investigating the time domain characteristics of the device under various operating frequencies, the frequency response of the device was summarized, which experimentally proved that the MoS2/WSe2/MoS2 BJT has voltage amplification capability in the 0–200 Hz region. In addition, the phase response of the device was also investigated. A phase inversion was observed in the low-frequency range. As the operating frequency increases, the relative phase between the input and output signals gradually shifts until it is in phase at frequencies exceeding 2.3 kHz. This work demonstrates the signal amplification applications of the vdW BJTs for neuromorphic computing and wearable healthcare devices. [ABSTRACT FROM AUTHOR]

The degradation properties of Indium phosphide hetero-junction bipolar transistors (InP HBTs) under proton irradiation are studied and modelled using a compact model for pre-irradiation, post-irradiation, and post-annealing. The variation rates of the model parameters, such as the base–emitter saturation current (ISE) and ideality factor in the ideal region (NE) in the forward Gummel characteristics, the zero-biased capacitance (Cje) and the grading factor (Mjer) in the BE junction capacitance, and the transit time parameter in the base region (Tfb), are analysed to delve into the degradation mechanism induced by proton irradiation. The displacement damage, induced by proton irradiation in the space charge region of the base–emitter junction and in the quasi-neutral bulk base region, is found to be responsible for the decrease in current gain and cut-off frequency. After annealing, the variation rates of the parameters decrease significantly compared to post-irradiation. This suggests that the recombination of unstable defects leads to a slight recovery in the degradation characteristics of InP HBTs after a period of annealing. [ABSTRACT FROM AUTHOR]

A bipolar junction transistor (BJT) and its operation are fundamental concepts for the understanding of power electronics (industrial electronics), transistor-transistor logic (TTL), electronic switching, and signal amplification in modern electronics. Previous research showed that non-major engineering, computer, electronic, and electrical engineering students could not understand the basic concepts involved in a BJT. This paper describes the development of a two-tier diagnostic test, the test's administration, limitations, the participants' detailed context, and findings from a study that explores Myanmar and Thai second-year undergraduate students' understanding of BJT working principles and applications. The results revealed that many students in both countries had the same alternative conceptions about collector current in each operation mode of the BJT. Some alternative conceptions differ from the previous research, such as a) the collector current does not depend on the base current in cut-off mode, and b) changing the collector current does not depend on the base current in active mode, but it depends on the collector supply voltage. These research findings provide valuable information and instruments for teachers to insight, prevent, and correct the alternative conceptions proposed by students. [ABSTRACT FROM AUTHOR]

In order to determine the junction temperature of semiconductor devices operating at different power supply and cooling conditions, their thermal parameters are needed. This article describes an original measurement set-up enabling the determination of thermal parameters of power semiconductor devices. In contrast to other set-ups described in the literature, this set-up makes it possible to measure thermal parameters which characterize the efficiency of the removal generated due to a self-heating phenomenon, as well as the parameters characterizing mutual thermal couplings. The presented set-up makes use of an indirect electrical method to determine the junction temperature of diodes, bipolar and unipolar transistors and IGBTs. The methods used to measure the self and transfer transient thermal impedances of these devices and the construction of the set-up are described. The influence of selected factors on the accuracy of the measurements is analyzed. Examples of the measurement results of thermal parameters (self and transfer transient thermal impedances) of power semiconductor devices operating at different cooling conditions are presented. The obtained research results are discussed. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) materials have attracted great attention in the past few years and offer new opportunities for the development of high-performance and multifunctional bipolar junction transistors (BJTs). Here, a van der Waals BJT based on vertically stacked n+-MoS2/WSe2/MoS2 was demonstrated. The electrical performance of the device was investigated under common-base and common-emitter configurations, which show relatively large current gains of α ≈ 0.98 and β ≈ 225. In addition, the breakdown characteristics of the vertically stacked n+-MoS2/WSe2/MoS2 BJT were investigated. An open-emitter base-collector breakdown voltage (BVCBO) of 52.9 V and an open-base collector-emitter breakdown voltage (BVCEO) of 40.3 V were observed under a room-temperature condition. With the increase in the operating temperature, both BVCBO and BVCEO increased. This study demonstrates a promising way to obtain 2D-material-based BJT with high current gains and provides a deep insight into the breakdown characteristics of the device, which may promote the applications of van der Waals BJTs in the fields of integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents a bandgap reference (BGR) with high-order temperature-segmented compensation. The compensation signal is generated using the voltage difference between two bipolar junction transistor (BJT) emitter bases, each of which individually loads a proportional-to-absolute temperature (PTAT) current and a zero-to-absolute temperature (ZTAT) current. The proposed BGR achieves a low-temperature coefficient (TC) over a wide temperature range. Simulations using the 0.18 μm Bipolar-CMOS-DMOS process show a typical TC of 2.25 ppm/°C from −40 °C to 125 °C. With an active area of 0.07986 mm2, it consumes 36 μW power under an operating voltage of 1 V. The integrated output noise from 0.1 Hz to 10 Hz is 81.1 μV. [ABSTRACT FROM AUTHOR]

Today voltage source inverters (VSIs) operate with high switching frequencies (let us assume higher than 50 kHz) owing to the fast Si (Silicon) or SiC (Silicon Carbide) switching transistors. However, there are some applications, e.g., with slower switches (e.g., IGBT—Isolated Gate Bipolar Transistor) or when lower dynamic power losses are required when the switching frequency is low (let us assume about 10 kHz). The resonant frequency of the output filter is usually below 1 kHz. The measurements of Bode plots of the measurement traces of various microprocessor-controlled VSIs show that in this frequency range, the characteristics of these channels can be simply approximated through two or three switching periods delay. For the high switching frequency, it is not noticeable, but for the low frequency it can cause some oscillations in the output voltage. One of the solutions can be to use the predictor of the measured state variables based on the full-state Luenberger observer or the linear Kalman filter. Both solutions will be simulated in MATLAB/Simulink and the chosen one will be tested in the experimental VSI. The research aims to omit delays in the measurement channels for the low switching frequency by using the predictions for the measured state variables and finally increasing the gains of the controller to decrease the output voltage distortions. [ABSTRACT FROM AUTHOR]

A Reverse Conduction Insulated Gate Bipolar Transistor (RC-IGBT) featuring an Active Trench Barrier (ATB) based on Super-Junction (SJ) technology is proposed and investigated. The double-trench gates are designed at the N-pillar and P-pillar of the SJ drift. Consequently, a p-type ATB located between the two trench gates is formed. The ATB working mechanism is controlled and modulated by the Gate Voltage (VGE) of the double-trench gates. In the forward conduction state, the ATB channel is depleted and automatically pinched off by the positive VGE. Thus, the barrier potential of the ATB is remarkably improved. Additionally, holes accumulate underneath the ATB and maintain high conductivity modulation of the SJ drift region. Thus, the low on-state voltage drop (VON) is obtained. In the reverse conduction state, the ATB pinch-off effect automatically fades away with the grounded VGE. In addition, the ATB, P-pillar, and N + act as the anode, drift, and cathode of the Free-Wheeling Diode (FWD), respectively. Electrons are blocked and accumulated by the trench gates. Thus, the hole injection is enhanced and the reverse conduction voltage (VR) is reduced. In the turn-off state, excessive holes can be effectively extracted by the extra ATB channel, and the turn-off loss (EOFF) is remarkably decreased. As a result, the trade-off relationship between VON and EOFF can be significantly improved, which achieves the best comprehensive property when compared with the conventional RC-IGBT and SJ-IGBT. [ABSTRACT FROM AUTHOR]

A model is proposed to explain the low-dose-rate effects when exposed to ionizing radiation in bipolar structures, taking into account the effects of the subthreshold defect formation in highly doped silicon layers. Variants for the degradation of the base current in a bipolar transistor are considered, taking into account the simultaneous action of surface radiation and displacement effects in the near-surface base region. The conditions for the enhanced low-dose-rate sensitivity (ELDRS) in bipolar structures are shown. The presented results of the analysis allow us to explain most of the observed experimental results. [ABSTRACT FROM AUTHOR]

Modern society is the development stage of informationization and intelligence, and display is the key factor to realize information exchange and intelligence. Among the many current displays, Micro light‐emitting diode (µLED) display is used as a disruptive next‐generation display. Based on the same GaN material and process platform, we propose the vertical integrated device, where Indium Gallium Nitride/Gallium Nitride (InGaN/GaN) based µLED and GaN bipolar junction transistors (BJT) monolithically integrated vertically on a single GaN chip. The ultraviolet optoelectronic characteristics of µLED on BJT (LET) devices were simulated by using Silvaco TCAD software. By optimizing the size and concentration of the epitaxy layer, the optimized integrated device is obtained with high current gain and strong response to UV light. The LET can be used as both receiver and emitter, which is regulated by changing the light input power or base voltage. This device can be driven by the base voltage and UV light alone, which is a multifunctional integrated device for light emitting, detecting, sensing, driving and regulating. [ABSTRACT FROM AUTHOR]

Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain β values >1100, ft>500 GHz, fmax>1300 GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of ∼1.3 ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the β value for WED-based devices when subjected to temperatures exceeding 340 K. In contrast, BED-based devices demonstrate a comparatively smaller variation in β at temperatures above 340 K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.

In this study, the ringing phenomenon of gallium nitride‐field effect transistor (GaN‐FET) and silicon‐insulated gate bipolar transistor (Si‐IGBT) inverter excitations in a ring sample was thoroughly measured and analyzed by using a high‐quality oscilloscope with a very high sampling rate of 5 giga‐samples per second (GS/s). Owing to the rapid switching of the GaN‐FET power devices in several nanoseconds and the ringing frequencies in the MHz range, the use of the high sampling rate of 5 GS/s is necessary and useful for accurate measurement. The experimental findings and analysis reveal the following three key points: (i) there are two possible types of high‐frequency resonance phenomena, that is, the first one caused by semiconductor devices and circuits and the other generated by the resonance with loads in use. (ii) The ringing phenomenon because of the resonance under the load is considered to be due to the rising time of pulses that are caused by the rapid switching of the semiconductor devices. (iii) The ability to measure and the two types of ringing phenomena depends on the intensity of the white noise of the measuring instrument [ABSTRACT FROM AUTHOR]

Electric ships have been developed in recent years to reduce greenhouse gas emissions. In this system, inverters are the key equipment for the permanent-magnet synchronous motor (PMSM) drive system. The cascaded insulated-gated bipolar transistor (IGBT)-based H-bridge inverter is one of the most attractive multilevel topologies for modern electric ship applications. Usually, the fault-tolerant control strategy is designed to keep the ship in operation for a certain period. However, the fault-tolerant control strategy with hardware redundancy is expensive and slow in response. In addition, after fault-tolerant control, the ship's PMSM may experience shock and overheating, and IGBT life is reduced due to uneven switching frequency distribution. Therefore, a stratified reconfiguration carrier disposition Sinusoidal Pulse Width Modulation (SPWM) fault-tolerant control strategy is proposed. The proposed strategy can achieve fault tolerance without any extra hardware. A reconfiguration carrier is applied to improve the fundamental amplitude of inverter output voltage to maintain the operation of the ship's PMSM. In addition, the available states of faulty H-bridge are fully used to contribute to the output. These can improve the life of IGBTs by reducing and balancing the power loss of each H-bridge. The principles of the proposed strategy are described in detail in this study. Taking a cascaded H-bridge seven-level inverter as an example, simulation and experimental results verify that the proposed strategy, in general, has a potential future application on electric ships. [ABSTRACT FROM AUTHOR]

As a core component of power conversion systems, insulated gate bipolar transistor (IGBT) modules continually suffer from severe thermal damage caused by temperature swings and shear stress, resulting in fatigue failure. Bond wires falling off is one of the failure modes of IGBT modules. Given that the number of fallen-off bond wires is a significant parameter to evaluate the health status of the IGBT modules, this paper proposes an online identification model to recognize the number of fallen-off bond wires during normal operation. Firstly, a database containing datum V c e , o n − T j − I C (collector–emitter on-state voltage V c e , o n , chip junction temperature T j , collector current I C ) planes with different fallen-off bond wires is built based on an offline aging test. Secondly, a Foster network model and a special circuit are designed to measure the junction temperature T j and the collector–emitter on-state voltage V c e , o n , respectively. Thirdly, the feature points of the IGBT module represented by V c e , o n , T j , and I C are given to the database to recognize the number of fallen-off bond wires according to the position of the feature points in the datum plane. The experimental results show that the proposed method can determine the fallen-off bond wires under the operation condition. [ABSTRACT FROM AUTHOR]

Summary: Bipolar junction transistors (BJTs) are widely used in various electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for BJTs is crucial for EMC analysis of these systems, such as high‐frequency circuits. In this paper, a BJT EMC model that satisfies both functionality and EMC analysis requirements was established based on physical characteristic measurement. First, comprehensive and systematic methods for measurement and extracting SPICE parameters based on physical BJTs are presented, including a proposed curve‐fitting calculation method for extracting barrier capacitance parameters. Second, an analysis of the impact of major BJT electrical characteristics parameters was conducted, leading to the identification of important model parameters affecting BJT functionality and EMC. Finally, the primary BJT model was optimized using the simplex method, and a method for EMC analysis and verification of the BJT model was presented. The experimental and simulation results are in good agreement, and the established model meets the accuracy requirements for both EMC and functionality. Therefore, the proposed method is feasible and suitable for the EMC modeling of BJTs. [ABSTRACT FROM AUTHOR]

A set of transfer and output current–voltage characteristics of a bipolar transistor with a short-period superlattice in the emitter region are calculated. It is shown that the presence of a superlattice in the transistor structure leads to the formation of a negative differential conductivity region, which makes it possible to implement not only amplification but also the generation and multiplication of high-frequency oscillations. [ABSTRACT FROM AUTHOR]

The high voltage–high humidity–high temperature reverse bias (HV-H3TRB) test was utilized to evaluate the reliability of silicon carbide insulated gate bipolar transistors (SiC IGBTs). Moisture invasion often induces termination/passivation and metal corrosion. Therefore, the HV-H3TRB test is generally used to assess termination / passivation robustness. However, under the HV-H3TRB test conditions, gate quality degradation may occur. In this study, the dominant degradation mechanism of SiC IGBTs was investigated. The changes of the most sensitive static characteristics (e.g., threshold voltage, breakdown voltage, and leakage current) were recorded. The threshold voltage decreased and leakage current increased substantially after > 1000 h of HV-H3TRB tests under 85 ℃/85% RH climate conditions. Capacitance–voltage (C–V) curve measurements indicated that the mobile ions at the SiC/SiO2 interface or in the gate oxide likely caused the threshold-voltage instability in the SiC IGBTs after the HV-H3TRB tests. This instability can be recovered by applying a negative gate bias. Subsequent failure analysis confirmed no corrosion of metals or termination/passivation in the device, which indicates the robustness of the passivation (consisting of phosphor-silicate glass and Si3N4). Therefore, the gate quality appears to be a significant reliability risk for SiC IGBTs under high humidity, high temperature, and high voltage conditions. [ABSTRACT FROM AUTHOR]

Hot electron transistors (HETs) represent an exciting new device for integration into semiconductor technology, holding the promise of high‐frequency electronics beyond the limits of SiGe bipolar hetero transistors. With the exploration of 2D materials such as graphene and new device architectures, hot electron transistors have the potential to revolutionize the landscape of modern electronics. This study highlights a novel hot electron transistor structure with a record output current density of 800 A cm−2 and a high current gain α, fabricated using a scalable fabrication approach. The hot electron transistor structure comprises 2D hexagonal boron nitride and graphene layers wet transferred to a germanium substrate. The combination of these materials results in exceptional performance, particularly in terms of the highly saturated output current density. The scalable fabrication scheme used to produce the hot electron transistor opens up opportunities for large‐scale manufacturing. This breakthrough in hot electron transistor technology holds promise for advanced electronic applications, offering high current capabilities in a practical and manufacturable device. [ABSTRACT FROM AUTHOR]

The importance of spinal reflexes is connected to the rehabilitation processes in neural prostheses and to the neuromuscular junction. In order to model neuron networks as electronic circuits, a simulation environment like LTSpice XVII or PSpice can be used to create a complete electronic description. There are four types of neurons employed in spinal reflexes: α-motoneurons, sensitive neurons, excitatory interneurons, and inhibitory interneurons. Many proposals have been made regarding methods that can be used for assimilating neurons using electronic circuits. In this paper, only a single internal model of a neuron is considered enough to simulate all four types of neurons implicated in the control loops. The main contribution of this paper is to propose the modeling of neurons using some electronic circuits designed either with a bipolar transistor or with CMOS transistors for the input and output of circuits stages. In this way, it is possible to mimic the neural pulses' circulation along the loops of the spinal reflexes and to prove the accuracy of the simulation results with respect to the biological signals collected from the bibliographic materials. [ABSTRACT FROM AUTHOR]

As a core component of photovoltaic power generation systems, insulated gate bipolar transistor (IGBT) modules continually suffer from severe temperature swings due to complex operation conditions and various environmental conditions, resulting in fatigue failure. The junction temperature prediction guarantees that the IGBT module operates within the safety threshold. The thermal equivalent circuit model is a common approach to predicting junction temperature. However, the model parameters are easily affected by the solder aging. An accurate temperature prediction by the model is impossible during service. This paper proposes an improved thermal equivalent circuit model that can remove the effect of solder aging. Firstly, the solder aging process is monitored in real-time based on the case temperatures. Secondly, the model parameters are corrected by the thermal impedance from chip to baseplate based on the linear thermal characteristic. The simulation and experimental results show that the proposed model can reduce the temperature prediction error by more than 90% under the same aging condition. The proposed method only depends on the case temperatures to correct the model parameters, which is more economical. In addition, the experimental and simulation analysis in this work can help students of power electronics courses have an in-depth knowledge of power devices' mechanical structure, heat dissipation principles, temperature distribution, junction temperature monitoring, and so on. [ABSTRACT FROM AUTHOR]

This paper introduces a new design of silicon nanowire (Si NW) phototransistor (PT) arrays conceived explicitly for improved CMOS image sensor performance, and comprehensive numerical investigations clarify the characteristics of the proposed devices. Each unit within this array architecture features a top-layer vertical Si NW optimized for the maximal absorption of incoming light across the visible spectrum. This absorbed light generates carriers, efficiently injected into the emitter–base junction of an underlying npn bipolar junction transistor (BJT). This process induces proficient amplification of the output collector current. By meticulously adjusting the diameters of the NWs, the PTs are tailored to exhibit distinct absorption characteristics, thus delineating the visible spectrum's blue, green, and red regions. This specialization ensures enriched color fidelity, a sought-after trait in imaging devices. Notably, the synergetic combination of the Si NW and the BJT augments the electrical response under illumination, boasting a quantum efficiency exceeding 10. In addition, by refining parameters like the height of the NW and gradient doping depth, the proposed PTs deliver enhanced color purity and amplified output currents. [ABSTRACT FROM AUTHOR]

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (Id) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to Id degradation including increased off-state current (Ioff) and decreased on-state current (Ion). The increased Ioff further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy. [ABSTRACT FROM AUTHOR]

This paper presents the application of unscented Kalman filter (UKF) for output voltage estimation of the Darlington amplifier (DA). Implementation of UKF requires the state-space model of DA circuit, which has been obtained using Kirchhoff's voltage law (KVL), Kirchhoff's current law (KCL) and the Gummel-Poon model of the bipolar junction transistor (BJT). This work uses Kronecker product for vector multiplication. The mathematical representation of nonlinear system in terms of Kronecker product helps to reduce the computational burden involved in the vector multiplication. The proposed method has the advantage that it can be used for the nonlinear region and large amplitude input signal. As the maximal precision of estimation requires modelling in terms of circuit elements and device parameters, the proposed method is able to provide an accurate estimation. We compared the UKF estimation results with the extended Kalman filter (EKF) and iterated extended Kalman filter (IEKF). The UKF presents smaller mean square error (MSE) as compared to EKF and IEKF as UKF is accurate to the third order for any nonlinearity. In addition, IEKF presents smaller MSE as compared to EKF because the linearisation error is taken into account by IEKF. [ABSTRACT FROM AUTHOR]

The properties of a bipolar NPN transistor when exposed to unmodulated incoherent radiation created by a white LED are studied. The static and dynamic characteristics of the transistor are measured at various exposure intensities. It is shown that the change in the characteristics of the transistor under the optical effect is due to the increased lifetime of nonequilibrium charge carriers and the photovoltaic effect in PN transitions. For these reasons, the gain increases, the switching threshold decreases, and the transistor's speed increases. The results obtained are applicable both to the creation of high-speed transistors and integrated circuits of a fundamentally new type. [ABSTRACT FROM AUTHOR]

This study investigates the degradation of the silicon NPN transistor's emitter-base junction, specifically the 2N2219A model, under both forward and reverse polarization. We examine the current–voltage characteristics under the influence of 1 MeV proton irradiation at various fluencies, which are 5.3 × 10 8 , 5.3 × 10 10 , 5 × 10 11 , 5 × 10 12 , and 5 × 10 13 protons/cm², all conducted at 307 K. The experimental findings elucidate a pronounced dependency of diode parameters, including the reverse saturation current, series resistance, and the non-idealist factor, on the incident proton flow. This observation underscores that proton-induced degradation is primarily driven by displacement damage, while recorded degradation is predominantly attributed to the generation of defects and interfacial traps within the transistor resulting from exposure to high-energy radiation. Our findings indicate that the effects of irradiation align more closely with the compensation phenomenon in doping rather than its reinforcement. [ABSTRACT FROM AUTHOR]

This paper proposes a modern approach to a DC/DC converter based on silicon carbide metal–oxide–semiconductor field-effect transistors (SiC-MOSFET). In particular, SiC-based MOSFETs are designed and implemented as Class-E DC/DC converter. The converter is developed as part of a solar power tower (SPT) heliostat unit to supply DC motors under different operation loads. Simulations are presented to demonstrate the effectiveness of the drive system under various scenarios using MATLAB/Simulink. A prototype experimental setup has been built and tested for the proposed converter. The proposed system for SPT converter reduces switching losses that reflect on drive system efficiency without affecting working drive performance. An identical silicon isolated-gate bipolar junction transistor (Si-IGBT)-based converter is designed and implemented to compare the proposed converter based on SiC-MOSFET. The outcomes demonstrated that the proposed converter is more capable and efficient under high temperatures saving 12% power losses at high operating frequencies. Further, the proposed system's switching frequency is higher than the traditional Si-IGBT converter, leading to a greater reduction of power losses and improved efficiency. [ABSTRACT FROM AUTHOR]

In this paper, the reliability of InP/InGaAs DHBTs under high reverse base–collector bias stress is analyzed by experiments and simulation. The DC characteristics and S parameters of the devices under different stress times were measured, and the key parameters with high field stress were also extracted to fully understand and analyze the high-field degradation mechanism of devices. The measurements indicate that the high-field stress leads to an increase in base current, an increase in base–collector (B–C) and base–emitter (B–E) junction leakage current, and a decrease in current gain, and different degrees of degradation of key parameters over stress time. The analysis reveals that the degradation caused by reverse high-field stress mainly occurs in the B–C junction, access resistance degradation, and passivation layer. The physical origins of these failure mechanisms have been studied based on TCAD simulation, and a physical model is proposed to explain the experimental results. [ABSTRACT FROM AUTHOR]

The multi-chip parallel insulated gate bipolar transistor (IGBT) is the core device in large-capacity power electronic equipment, but its operational reliability is of considerable concern to industry. The application of IGBT online degradation state analysis technology can be beneficial to the improvement of system reliability. The failure mechanism of IGBT devices is discussed in this paper, and a technique for analyzing the degradation state of IGBT based on apparent junction temperature is proposed. First, the distortion consistency of the voltage rise time in various failures is discussed, and the junction temperature dependence of the voltage rise time is then demonstrated. Subsequently, an apparent junction temperature model based on the voltage rise time is established (the fitting accuracy is as high as 94.3%). From the high-frequency model in the switching process of the device, an online extraction technology of key parameters (e.g., voltage rise time) is developed. Finally, an experimental platform for IGBT degradation state estimation is established, and the feasibility of IGBT degradation state estimation based on apparent junction temperature is proved, especially the degradation of bonding-wire and the gate-oxide-layer. The experimental results show that the proposed IGBT degradation state estimation technique based on apparent junction temperature is a reliable online estimation method with non-contact, high accuracy, and comprehensiveness. [ABSTRACT FROM AUTHOR]

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This paper works on the modelling of solar PV with series parallel connection of the strings for the composite climate location and the detailed study has been done on the gate signal of the chopper used for boosting with three different conditions. As the climate conditions are very important factor for the installation of the project to fulfill the captive requirements, a study has also been done with the help of climate consultant software so that the radiations capacity and potential to develop the energy is with in its maximum output capacity. In the next phase an inverter has also been connected for the conversion into single phase AC output for the testing of the model for the usage in the load or grid. Various methods for the control of the booster has been analyzed and considered. Simulation is done on a Matlab software and the result is analyzed. [ABSTRACT FROM AUTHOR]

Accurate models of power electronic converters can greatly enhance the accuracy of hardware-in-the-loop (HIL) simulators. This can result in faster and more cost-effective design cycles in industrial applications. This paper presents a detailed hardware model of the IGBT and power diode at the device level suggested for emulating power electronic converters on a field programmable gate array (FPGA). The static visualization of the IGBT component involves an arrangement of equivalent models for both the MOSFET and bipolar transistor in a cascading configuration. The dynamic aspect is represented by inter-electrode nonlinear capacitances. In an effort to expedite the development process while still producing reliable results, the algorithm for the simulation system was built utilizing FPGA-based rapid prototyping via the HDL Coder in MATLAB software (R2019b). Essentially, the HDL Coder transforms the Simulink blocks of these devices within MATLAB into a hardware description language (HDL) suitable for implementation on an FPGA. To evaluate the suggested IGBT hardware model and the nonlinear circuit simulation technique, a chopper circuit is replicated, and an FPGA-in-the-loop simulation is carried out to compare the efficacy and accuracy of the model with both offline simulation results and real-time simulation results using MATLAB Simulink software and the Altera FPGA Cyclone IV GX development board. [ABSTRACT FROM AUTHOR]