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An improved analytical model for flicker noise (1/ $f$ noise) in MOSFETs is presented. Current models do not capture the effect of high-trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45-nm low-power CMOS technology node.

Nanoscale CMOS devices display very high peak transit frequency Ft of several hundreds of GHz. This feature can be exploited for reducing power consumption by shifting the operating point towards moderate or eventually weak inversion where the Ft still reaches tens of GHz, high enough for many modern RF applications. This necessitates the use of compact models that are accurate even at such low current densities. The recently standardized charge-based bulk MOSFET compact model BSIM6 has been developed with the aim to provide an accurate description of advanced CMOS processes, including low levels of inversion and RF operation. This paper compares BSIM6 against measurements of a commercial state-of-the-art 40 nm CMOS process, mainly focusing on very low bias conditions, at RF operation. The results validate the accuracy and suitability of BSIM6 for very low-power RF IC design.

The recently proposed BSIM6 bulk MOSFET compact model is set to replace the hitherto widely used BSIM3 and BSIM4 models as the de-facto industrial standard. Unlike its predecessors which were threshold voltage based, the BSIM6 core is charge based and thus physically continuous at all levels of inversion from linear operation to saturation. Hence, it lends itself conveniently for the use of a design methodology suited for low-power analog circuit design based on the inversion coefficient (IC) that has been extensively used in conjugation with the EIN model and allows to make simple calculations of, for example, transconductance efficiency, gain bandwidth product, etc. This methodology helps to make a near-optimal selection of transistor dimensions and operating points even in moderate and weak inversion regions. This paper will discuss the IC based design methodology and its application to the next generation BSIM6 compact MOSFET model. (C) 2013 Elsevier Ltd. All rights reserved.

Ce papier présente une approche simple et précise pour concevoir et optimiser les oscillateurs LC en utilisant le Coefficient d'Inversion (IC). Pour une amplitude et une fréquence d'oscillation données, nous pouvons déterminer toutes les variables du design afin d'obtenir le meilleur compromis entre consommation en courant et bruit de phase. Cette méthodologie est démontrée au travers de la conception d’un oscillateur de Pierce à 2,4 GHz. Elle a été vérifiée avec le modèle compact BSIM6 ainsi que les paramètres d’une technologie CMOS 40 nm.

Ce papier présente une approche simple et précise pour concevoir et optimiser les oscillateurs LC en utilisant le Coefficient d’Inversion (IC). Pour une amplitude et une fréquence d’oscillation données, nous pouvons déterminer toutes les variables du design afin d’obtenir le meilleur compromis entre consommation en courant et bruit de phase. Cette méthodologie est démontrée au travers de la conception d’un oscillateur de Pierce à 2,4 GHz. Elle a été vérifiée avec le modèle compact BSIM6 ainsi que les paramètres d’une technologie CMOS 40 nm.

BSIM6: Charge based MOSFET model BSIM6 is the next BSIM Bulk MOSFET model Charge based core derived from Poisson's solution Physical effects (SCE, CLM etc.) taken from BSIM4 Parameter names matched to BSIM4 parameters Gummel Symmetry (symmetric @ VDS=0)

The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless body area networks and the Internet of Things (IoT), to gain more and more ground. However, these RF low-power applications set stringent constraints on the power consumption, which complicate even more the already difficult task of the RF IC design. This can be addressed by exploiting the phenomenal RF performance offered by the state-of-the-art nanoscale CMOS technologies, with impressive peak transit frequency at the order of hundreds of GHz, and sub-1 dB minimum noise figure. More specifically, most of the RF applications operate at the low GHz range, so the cut-off frequency surplus, achieved typically in strong-inversion (SI), can be traded-off with a lower power consumption by shifting the operating point to moderate- (MI) or weak-inversion (WI), while keeping the RF performance within the desired specifications. There is an extensive work by the semiconductor community on characterization and modeling the MOS transistor at RF. Nonetheless, most of such studies focus either on the high-performance SI or on rather mature processes with respect to the contemporary state-of-the-art. In this thesis, an extensive and multi-faceted work on detailed characterization and accurate modeling of nanoscale MOSFETs for low-power operation, focusing therefore on subthreshold operation, is presented and discussed. The analysis is always performed under the perspective of the ultra-low power RF IC design. After all, the reliability of the RF IC simulation tools in this high-end range of frequencies and at very low current densities, which constitute the two extreme conditions in terms of operation of the transistor, strongly depends on the accuracy of the model used. The dissertation follows a dual course. First, a simple, yet thorough, small-signal RF model is elaborated in order, to describe analytically the RF performance of nanoscale MOSFETs from SI down to the deep WI region, including its noise behavior. Further, the analytical expressions are used in order to form a step-by-step parameter extraction methodology. Especially, for the extraction of the RF noise model parameters, an innovative step-by-step procedure, which is applied directly on measurements, is developed. Then, a state-of-the-art physics-based compact model (BSIM6) is used. Within this part of the work, a set of novel advancements and contributions are introduced in order for the model to be able to capture the complexity of the behavior of modern advanced CMOS technologies. The results show excellent agreement regarding all different aspects, across all modes of operation (CV, DC, RF performance), even at very low bias conditions. The evaluation of both the modeling approaches is done in detail and uses design oriented tools and metrics, such as the Gm/ID, the Y-parameters, the four RF noise parameters and a wide range of figures-of-merit (FoMs). Finally, a discussion around inversion coefficient (IC) design methodology is carried out, where several FoMs based on IC are modeled with the use of very simple analytical expressions requiring only few parameters. Measurements of advanced 40 nm and 28 nm CMOS technologies are used throughout the thesis to validate all the different modeling approaches.

This paper presents a fast and accurate way to design and optimize LC oscillators using the inversion coefficient (IC). This methodology consists of four steps: linear analysis, nonlinear analysis, phase noise analysis, and optimization using a figure of merit. For given amplitude of oscillation and frequency, we are able to determine all the design variables in order to get the best trade-off between current consumption and phase noise. This methodology is demonstrated through the design of Pierce and cross-coupled oscillators and has been verified with BSIM6 metal oxide semiconductor field effect transistor compact model using the parameters of a commercial advanced 40 nm complementary metal oxide semiconductor process.

The downscaling of CMOS processes has led to devices with an impressive RF performance. Advanced nanoscale RF MOSFETs present very high transit frequency, which can be traded off with lower power consumption, by shifting the operating point towards the weak inversion (WI) regime. This paper explores whether the simple RF schematics and models used in strong inversion remain valid in moderate or even down to deep WI regions for nanoscale devices. A simple RF equivalent circuit is proposed, leading to first-order analytical expressions, which are able to describe the RF small-signal behavior of nanoscale MOSFET, including noise, across all inversion levels. Using these expressions it is possible to extract the values of all the RF components and noise model parameters directly from measurements. The analytical models are compared to RF measurements of a commercial state-of-the-art 40-nm CMOS process and to the advanced BSIM6 compact bulk MOSFET model, showing very good accuracy.

The state-of-the-art scaled down CMOS processes have led to devices with extremely high Ft reaching several hundreds of GHz. This high F t can be traded with power consumption by moving the operating point towards weak inversion with Ft reaching tens of GHz, high enough for many modern RF applications. The new charge-based bulk compact MOSFET model BSIM6 was developed with the objective to provide an accurate description of the modern nanoscale CMOS technologies including weak and moderate inversion regions. This paper, compares BSIM6 against RF measurements made on an advanced 40 nm CMOS process, particularly focusing on very low bias conditions. The results validate the model's accuracy and demonstrate its suitability for ultra-low power RF IC design. © 2013 Department of Microelectronics and Computer Science, Technical University of Lodz.