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In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

The Low Frequency Noise (LFN) in MOSFETs is critical to Signal-to-Noise Ratio (SNR) demanding circuits. Buried Channel (BC) MOSFETs are commonly used as the source-follower transistors for CCDs and CMOS image sensors (CIS) for lower LFN. It is essential to understand the BC MOSFETs noise mechanism based on trap parameters with different transistor biasing conditions. In this paper, we have designed and fabricated deep BC MOSFETs in a CIS-compatible process with 5 V rating. The ${1}/{f^{\gamma }}$ LFN is found due to non-uniform space and energy distributed oxide traps. To comprehensively explain the BC MOSFETs noise spectrum, we developed a LFN model based on the Shockley–Read–Hall (SRH) theory with WKB tunneling approximation. This is the first time that the ${ 1}/{f^{\gamma }}$ LFN spectrum of BC MOSFET has been numerically analyzed and modeled. The Random Telegraph Signal (RTS) amplitudes of each oxide traps are extracted efficiently with an Impedance Field Method (IFM). Our new model counts the noise contribution from each discretized oxide trap in oxide mesh grids. Experiments verify that the new model matches well the noise power spectrum from 10 to 10k Hz with various gate biasing conditions from accumulation to weak inversion.

A single-event-enabled compact model for bulk FinFET technologies has been developed and integrated with a process design kit (PDK) and an industry standard electronic design automation tool flow. The compact model incorporates transistor bias dependence and 3-D ion-incidence geometry awareness into the calculation of the single-event-generated current waveform. The model has been developed for performance from nominal supply circuit operation down to near-threshold voltage applications. The 3-D technology computer-aided design simulations have been used to calibrate the compact model transient current and voltage waveforms for single, hard-biased, devices and full 3-D logic gate response, e.g., inverter, NAND, and NOR. Single-event transient pulsewidth measurements, from heavy-ion testing over an angle of incidence and bias, on a technology characterization vehicle test chip fabricated at the 14-/16-nm bulk FinFET technology generation, have been used to validate the model response. The bulk FinFET single-event-enabled compact model, integrated with the PDK, enables a single-event analysis of circuit topologies for application in radiation environments while maintaining the standard integrated circuit design flow.

This chapter examines in detail the current, existing key design rules and procedures used to design and analyze the performance characteristics (efficiency, power added efficiency, gain, etc.) of radio frequency (RF) power amplifiers. The discussion starts with the concept of type (linear, nonlinear) and class (A, B, C, AB, D, E, F, G, and H) of an RF amplifier. Then the design equations of each class are enumerated, followed by a detailed discussion of performance metrics, calculation, and estimation of RF power amplifiers. Then the electronics industry standard load and source techniques are explained, focusing on how and why these two schemes are so important to successfully design and implement an RF power amplifier.

This paper presents the design and measurement of a fully integrated Ka-band power amplifier (PA) in 0.13-µm SiGe BiCMOS process. The PA is designed with two-stage differential cascode structure. Based on the transformer parallel power combining topology, high output power is achieved while maintaining high efficiency. Furthermore, by designing the appropriate transistor bias voltage, the gain curve is upturned and a higher output 1-dB compression point (OP 1dB ) is obtained. Finally, the proposed PA achieves the measured saturated output power (Psat) of 22.9 dBm with 21% peak power added efficiency (PAE), and 22.5 dBm OP 1dB. The small-signal gain is 24.9 dB, and 3dB bandwidth is 32–39 GHz. The core chip size without pads is 0.4 mm2.

Biasing is an essential feature of any electronic circuit. The traditional method of biasing involves applying a proper DC to fix the operating point and thereafter ensure its stability. In this paper, we have proposed a new concept of transistor biasing. Instead of a fixed quiescent point which is normally established by giving DC input to the transistor for the purpose of biasing, we have proposed an oscillating quiescent point by giving square wave biasing input, so that the quiescent point would be oscillating between the two ends of the load line. During the positive half cycle of the input signal the quiescent point would be at the bottom of the load line near the cutoff region, while during negative half cycle of the input signal, the quiescent point would be at the top of the load line near the saturation region, thereby giving full cycle operation for the signal excursion in the active region. The linear range of amplification is better exploited to give higher amplification with negligible distortion and high efficiency.

A new biasing scheme is proposed for transistors used in power-amplifier applications. In the proposed biasing scheme, a constant current source is used as the power supply for the transistor’s output terminal. A whole new family of amplifier classes can be defined using this biasing scheme. Analytical equations are obtained and verified for current and voltage waveforms of a current-biased transistor for both resistive and tuned load impedances. Using the proposed current biasing scheme, the transistor presents completely different behaviors compared with the conventional voltage biasing scheme. These properties can be utilized for new design concepts and can provide new possibilities in the future designs and applications. Some of the differences between current-biased and voltage-biased amplifiers are discussed. One of the different behaviors shown by the current-biased transistor amplifiers is the reversed load modulation. Using this property of the current-biased amplifiers, a reversed modulation dual branch (RMDB) amplifier structure is proposed for ultra-wideband high efficiency at power back-off. Due to the reversed load modulation of current-biased transistors, a multibranch amplifier can be implemented to obtain high efficiency at power back-off without the need for an impedance inverter at the output of the current-biased amplifier. By using the proposed amplifier structure, a wideband RMDB amplifier was fabricated and tested exhibiting higher than 37% efficiency for long-term evolution (LTE) signals in 0.8–2.2-GHz bandwidth, which is equivalent to 93% fractional bandwidth.

An $E$ -band (71–86-GHz) bidirectional transceiver is presented in this paper. The time-division duplex architecture avoids transmit (TX)/receive (RX) switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a wideband PA/LNA circuit, which alleviates the parasitic loading of each circuit through a wideband power combiner. The bidirectional transceiver circuit is implemented in 90-nm SiGe BiCMOS process. In TX mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In RX mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz. The whole RF frontend chip consumes 350.2- and 137.7-mW dc power in TX and RX modes, respectively, including all the RF, IF, and local oscillator amplifiers. The overall chip size is $1.5~\text {mm}\times 0.9$ mm including pads.

The performance of portable ultrasound systems is affected by the excessive heat generated by amplifiers, thereby reducing the sensitivity and resolution of the transducer devices used in ultrasound systems. Therefore, the amplifier needs to generate low amounts of heat to stabilize portable ultrasound systems. To properly control the amplifier, the related bias circuit must provide proper DC bias voltages for long time periods in ultrasound systems. To this end, a stacked transistor bias circuit was proposed to achieve a relatively constant amplifier performance irrespective of temperature variance without any cooling systems as the portable ultrasound system structure is limited. To prove the proposed concept, the performance of the gain and DC current consumption at different experimental times was measured and compared to a developed class-B amplifier with different bias circuits. The amplifier with the stacked transistor bias circuit outperformed with regard to the gain and DC current variance versus time (&minus, 0.72 dB and 0.065 A, respectively) compared to the amplifier with a typical resistor divider bias circuit (&minus, 5.27 dB and 0.237 A, respectively) after a certain time (5 min). Consequently, the proposed stacked transistor bias circuit is a useful electronic device for portable ultrasound systems with limited structure sizes because of its relatively low gain and DC current variance with respect to time.

In this brief, we propose a novel bipolar junction transistor-based I-MOS, called the bipolar I-MOS, to reduce the operating voltage of the I-MOS using the transistor gain action. Using 2-D simulations, we demonstrate that the proposed bipolar I-MOS exhibits a low operating voltage ( $\sim 2.8$ V), which is $\sim 60$ % lower than that of the corresponding p-i-n I-MOS, and also a steep subthreshold slope of 6.25 mV/decade. In the bipolar I-MOS, since the avalanche-generated carriers do not pass through the channel region under the gate, it is expected to have a higher reliability compared with the p-i-n I-MOS. Therefore, the bipolar I-MOS could be a promising candidate for near ideal switching applications.

A bidirectional low-noise amplifier (LNA) is presented in this letter. By using transistor bias control and low-loss coplanar waveguide structures with defected ground shield as both interconnect traces and distributed passives, the proposed two-port bidirectional amplifier achieves a measured performance close to the stand-alone LNA from 54 to 65 GHz. The design is fabricated in a 0.18- $\mu \text{m}$ SiGe BiCMOS process consuming a maximum 10.6-mA current from a 1.8-V supply voltage and occupies a 0.85-mm2 core die area.

A method and algorithm to determine the pinching voltage of current in powerful bipolar radiofrequency and microwave transistors are described, based on using the dependence of a variable component of voltage on the emitter junction of the transistor on the collector voltage without the use of the “hot spot” mode. The errors in determining the voltage of pinching are given, and the results of testing the method using serial devices are presented.

This book, Electronic Devices and Circuit Application, is the first of four books of a larger work, Fundamentals of Electronics. It is comprised of four chapters describing the basic operation of each of the four fundamental building blocks of modern electronics: operational amplifiers, semiconductor diodes, bipolar junction transistors, and field effect transistors. Attention is focused on the reader obtaining a clear understanding of each of the devices when it is operated in equilibrium. Ideas fundamental to the study of electronic circuits are also developed in the book at a basic level to lessen the possibility of misunderstandings at a higher level. The difference between linear and non-linear operation is explored through the use of a variety of circuit examples including amplifiers constructed with operational amplifiers as the fundamental component and elementary digital logic gates constructed with various transistor types. Fundamentals of Electronics has been designed primarily for use in an upper division course in electronics for electrical engineering students. Typically such a course spans a full academic years consisting of two semesters or three quarters. As such, Electronic Devices and Circuit Applications, and the following two books, Amplifiers: Analysis and Design and Active Filters and Amplifier Frequency Response, form an appropriate body of material for such a course. Secondary applications include the use in a one-semester electronics course for engineers or as a reference for practicing engineers.

For application in radar and communication systems operating in the frequency range around 250 GHz, a power amplifier (PA) millimeter-wave monolithic integrated circuit (MMIC) has been developed. The amplifier makes use of a novel coupler approach allowing for in-phase and equal-magnitude distribution of an incoming signal to four parallel output ports. This is possible due to a subtle use of grounded coplanar waveguide and air-bridge microstrip transmission lines, providing different propagation constants. With a size of quarter-wavelength, the coupler is very compact and is the key to the presented PA topology. The amplifier exploits the virtual open occurring due to the identical signals for transistor biasing and matching. The amplifier topology is applied to develop an amplifier MMIC. When biased for maximum gain, it shows a 17-GHz 3-dB bandwidth around its center frequency at 248 GHz with a maximum gain of 32.8 dB. When biased for maximum output power, it provides an output power of 10 and 8.5 dBm at 250 and 270 GHz, respectively. At 250 GHz, it demonstrates a state-of-the-art power density of 125 mW/mm. Due to the amplifier topology, the MMIC is very compact $({\hbox{1.25}}\times {\hbox{0.75}}~{\hbox{mm}}^{2})$ .

This article describes the detailed development of a large-signal transistor model for a microwave power heterojunction bipolar transistor (HBT). Based on the neurospacemapping (Neuro-SM) technique, this model uses neural networks to map a coarse model space represented by the existing model simulations onto the fine model space represented by device measurements. This article tied for first place in the Microwave Transistor Modeling Student Design Competition at the 2014 IEEE International Microwave Symposium (IMS2014) held in Tampa, Florida.

Recently published reports suggest that symmetric lateral bipolar transistors on semiconductor-on-insulator (SOI) is CMOS compatible in fabrication process, and can be much denser than CMOS due to their much larger (5-10× larger) drive-current capability. When used in traditional bipolar circuits, SOI bipolar offers much lower power dissipation and/or much higher maximum speed. With both NPN and PNP devices of comparable characteristics, SOI lateral bipolar suggests the possibility of complementary bipolar (CBipolar) circuits in configurations analogous to CMOS. In this paper, the performance versus power dissipation of CBipolar circuits is examined using analytic equations. It is shown that for CBipolar to be superior to CMOS in both performance and power dissipation, narrow-gap-base heterojunction structures, such as Si emitter with Ge base or Si emitter with SiGe base, are required.

This paper presents the design, optimization, and characterization of a square-law power detector for heterodyne millimeter-wave radiometers implemented using 0.13 μm SiGe HBTs. A 3-dB bandwidth of 19–34 GHz (56% fractional bandwidth) is obtained through the use of inductively degenerated SiGe HBTs with large emitter lengths. The detector achieves a minimum noise-equivalent power (NEP) of 0.49 pW/VHz at 24 GHz with a peak responsivity of 17.1 kV/W. Through careful transistor biasing and judicious use of resistors, the detector achieves a measured 1/f noise corner frequency of 24 Hz when biased for optimal NEP. To the best of our knowledge, this detector achieves the widest fractional bandwidth and best 1/f noise performance of all tuned transistor-based square-law detectors for high-frequency radiometers to date.

Non-Foster networks are those whose reactance has a negative slope with frequency, and can thus overcome bandwidth limitations of many passive systems using their unique impedance and phase properties. The design parameters of a negative impedance convertor circuit (circuit configuration, transistor bias) used to generate non-Foster impedances will depend on the load impedance at the output of the non-Foster circuit, the frequencies of operation and requirements pertaining to a specific application (such as low noise or high linearity). Insights into the design, simulation, implementation and stability analysis of non-Foster circuits will be presented through measured results of a non-Foster matched cylindrical slot antenna. Simulation techniques that can accurately predict measurements will also be detailed. Further, noise and linearity measurements that match simulations will be shown for the same non-Foster matched antenna. A discussion of the trade-offs between bandwidth, loss, stability, noise and linearity of a non-Foster circuit will be helpful in optimizing non-Foster circuits for specific applications.

In an integrated circuit, transistors are used in standard configurations which occur repeatedly. In order to facilitate circuit analysis and synthesis for students, the concept of ‘transistor role’ has been introduced and a fundamental set of bipolar and MOS transistor roles was defined. This paper presents the LTspice implementation of the Bipolar and MOS Transistor Roles Building Block (BB) Library, with the most common transistor roles. Utilizing this BB Library, we then demonstrate the LTspice implementation of three representative analog integrated circuits: the LM741 Op Amp, the Open Loop CMOS Comparator MC14575 and a composite cascode high gain CMOS Op Amp. Simulation results prove that the transistor roles BB library works as expected, while facilitating circuit analysis, thus, allowing students to synthesize and simulate complex analog circuits more easily.

This chapter reviews rectifier diodes, light emitting diodes, Zener diodes and explains simple circuits incorporating them. The chapter also includes a complete review of bipolar transistors, circuit behavior and the conditions that lead to the bipolar transistor to operate in cut-off, active and saturation regions.

In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23 dB with respect to the use of conventional biasing. A THD value better than −35 dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5 µm CMOS technology, are able to operate with a supply voltage of 1.2 V and a quiescent power consumption of only 36 µW, using a silicon area 2 .

CMOS circuit design is based on two fundamental pillars: Understanding how MOS transistors operate, so a designer can innovate new circuit topologies and functions or know how to adjust the geometry and bias of transistors in existing circuits to meet performance goals; and understanding how accurate the MOS transistor models used in circuit simulators are, to know where the results of the detailed simulations used to verify circuit performance can or cannot be trusted.

Practical aspects of design of converters based on compound bipolar transistors are analyzed. The passage of a small reactive current through a compound bipolar transistor is analyzed using the example of a voltage inverter. A frequency converter with input protection is designed and loaded with an asynchronous motor at the output.

This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW.

The performance potential and scaling characteristics of thin-base SOI symmetric lateral bipolar transistors were examined using 1-D analytic equations for the currents and capacitances. The device can operate at collector current densities >100 mA/μm2, and it scales similarly to CMOS in terms of density. The physical base width is scalable to less than 20 nm. Multiple devices of different specifications can be integrated on a chip. A sample design is shown to have fT > 200 GHz, fmax >1 THz, VA > 4V, and a self gain of 60. A balanced design is shown to have 350-GHz fT and 700-GHz fmax, VA of 2.4 V, and a self gain of 20. These results are superior to those reported for 32 nm SOI CMOS. The results suggest a need to rethink bipolar circuit design. They also suggest opportunities for novel bipolar and BiCMOS circuits. The devices in high-speed Si-base bipolar circuits operate at about 1.0 V. The path toward 0.5 V bipolar circuits is to use semiconductors with smaller bandgap, such as Ge.

Design of analog integrated circuits is discussed in this paper. The emphasis is on the biasing design of ICs using Fixator-norator pairs. Fixators are used to keep the driver transistors biased at the desirable operating points while the pairing norators are used to allocate and specify the bias-supporting components. A bias-supporting component is shown to be one of the two categories: 1) a DC voltage source or a DC current source/sink or 2) a power-conducting component. A power-conducting component is typically a resistor in lumped circuits but an active load or current mirror in an analog IC. Three types of active loads are introduced and their design is also discussed in this paper. Two examples, one in bipolar and one in CMOS technology, demonstrate the analog IC design procedure.

The design of an ultra-low voltage CMOS wideband LNA topology operating under a 0.6 V power supply with high gain and high IP2 is presented in this paper. The circuit performance is targeted towards use in direct conversion receivers, where a high IP2 is required. The LNA operates in sub-1 GHz applications reaching frequencies as low as 50 MHz, as it is required by IEEE 802.22 standard. The topology proposed here is based on the resistive-feedback inverter with a cascaded auxiliary amplifier to implement noise canceling. This cascaded amplifier is composed by a common-source (CS) amplifier and a very linear buffer at the output of the cascade. The high IP2 is obtained by a proper transistor biasing and by combining diodes with the load of the amplifiers with the highest non-linearity. This topology also works as a balun to comply with single-ended input from antennas and differential mixers as output loads. The post-layout simulations included bondwire inductances and pad capacitances parasitics. The results show a bandwidth of 50 MHz–1 GHz, voltage gain > 18 dB, NF < 3.8 dB, Sn < −13 dB and maximum IP2 of 38 dBm. The LNA power consumption is just 6.7 mW, excluding pad buffers.

This chapter presents how the real frequency technique (RFT) is used in the design of multistage distributed amplifiers. The equalizers are made of transmission lines. The chapter introduces a new variable and formalism better suited for the distributed medium. The modified RFT is able to optimize and synthesize the transmission lines. The chapter provides a method for optimizing the multistage amplifier noise figure. It gives a technique to solve the problem of too high or too low characteristic impedance requirements for the microstrip realizations. The chapter provides a possible transistor bias circuit and shows how it can be used during the optimization process to provide more accurate results. It concludes with realizations of a 1.15-1.5??GHz, a 2-8??GHz, and a 5.925-6.425??GHz distributed amplifiers. For the distributed amplifiers of the chapter, the error function consists of the transducer gain, the voltage standing wave ratio (VSWR), and the noise figure.

On the basis of the two-section model of a high-power bipolar transistor, it is shown that the slope of dependence of the small-signal feedback coefficient on the collector voltage in the presence of defects in the transistor is proportional to the defect size. The setup for the automated monitoring of the current-distribution nonuniformity in the transistor device structure from the indicated dependence with using the combination of linearly increasing and small harmonic variations in the collector voltage is described. The experimental dependences confirming the results of the theoretical analysis are presented.

Metal-oxide-semiconductor field effect transistor (MOSFET) intrinsic gain degradation caused by channel length modulation (CLM) effect is examined. A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4 (BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced, which only needs a few technology parameters. With this transistor intrinsic gain model, complementary metal-oxide-semiconductor (CMOS) operational amplifier (op amp) DC gain could be predicted. A two-stage folded cascode op amp is used as an example in this work. Non-minimum length device is used to improve the op amp DC gain. An improvement of 20 dB is proved when using doubled channel length design. Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain. After these, a full op amp DC gain scaling roadmap is proposed, from 130 nm technology node to 32 nm technology node. Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB. Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology. The prediction based on our simplified gain model agrees with SPICE simulation results.

This paper proposed a new high-order curvature compensation technique for a new bandgap voltage reference structure using the temperature characteristics of current gain β and emitter bandgap narrowing factor ΔE G of a lateral NPN bipolar transistor. The new structure can produce two voltage references, which are 1.209 and 2.418 V, respectively. The simulation results show that the temperature coefficients of the two output voltage are 0.52 ppm/°C, the PSRR is more than 60 dB for frequencies at 10 kHz, and the circuit dissipates 0.18 mW with 5-V supply.

This work rediscovers the attractiveness of feedback biasing when applied to circuits designed in nanoscale CMOS technologies. It is shown that very compact amplifiers can be obtained by utilizing a type of biasing that imposes minimal area overhead. We discuss how the undesired features of the nanoscale CMOS technologies actually help in the revival of this simple biasing method in newer technology generations. The measurement results of prototyped common-source (CS) amplifiers utilizing feedback biasing for application in medical ultrasound imaging systems are presented in this brief. The proposed feedback biasing is also suitable for amplifying signals from high-impedance sources that pose challenges on maintaining high input impedance for the voltage amplifiers while maintaining a very low input capacitance value. Measurements show that the proposed amplifier achieves a voltage gain of 28 dB, an output noise power spectral density of 0.11 (muV)2 Hz at center-frequency, and a total harmonic distortion of -30 dB, with the full-scale output at 30 MHz, while drawing 120 muA from a 1-V power supply. The amplifiers were fabricated in 90-nm CMOS technology and measured to be just 20 mum times10 mum.

We study theoretically the magnetic bipolar transistor, and compare its performance with common bipolar transistor. We present not only the simulation results for the characteristic curves, but also other relevant parameters related with its performance, such as: the current amplification factor, the open-loop gain, the hybrid parameters and the cutoff frequency. We noted that the spin–charge coupling introduces new phenomena that enrich the functionality characteristics of the magnetic bipolar transistor. Among other things, it has an adjustable band structure, which may be modified during the device operation; it exhibits the already known spin-voltaic effect. On the other hand, we observed that it is necessary a large g -factor to analyze the influence of the field B over the transistor. Nevertheless, we consider the magnetic bipolar transistor as a promising device for spintronic applications.

A new 4H-SiC Bipolar Junction Transistor with Suppressed Surface Recombination structure: SSR-BJT has been proposed to improve the common emitter current gain which is one of the main issues for 4H-SiC BJTs. A Lightly Doped N-type layer (LDN-layer) between the emitter and base layers, and a High Resistive P-type region (HRP-region) formed between the emitter mesa edge and the base contact region were employed in the SSR-BJT. A fabricated SSR-BJT showed a maximum current gain of 134 at room temperature with a specific on-resistance of 3.2 mΩcm2 and a blocking voltage VCEO of 950 V. The SSR-BJT kept a current gain of 60 at 250°C with a specific on-resistance of 8 mΩcm2. To our knowledge, these current gains are the highest among 4H-SiC BJTs with a blocking voltage VCEO more than about 1000 V which have been ever reported.

This paper will introduce a new isolated version of the compensated base drive for high-power bipolar transistor switches. A unique pulse transformer is used to drive a high-power bipolar transistor by means of a compensated Darlington pair. This Darlington pair consists of an insulated gate bipolar driving transistor (IGBT) and a high-current single bipolar transistor. In high-efficient, high-power bridge applications of high-current switches, the saturation voltage should be ultra-low, which implies a high-power bipolar transistor in deep saturation. This isolated base-drive circuit is described and evaluated in these applications.

A new topology to design low-phase-noise low-power quadrature voltage-controlled-oscillator (QVCO) is proposed. The proposed topology is based on using a dynamic transistor biasing scheme in a typical voltage-controlled-oscillator (VCO). This method modifies the equivalent impulse-sensitivity-function (ISF) of oscillator to reduce the oscillator sensitivity to noise sources and as a result reducing the oscillator phase noise. A 1.8GHz, 1.8v designed QVCO with 0.18u CMOS technology based on the proposed topology shows a phase noise of -134dBc/Hz at 1MHz offset frequency from the carrier.

We report the first demonstration of thin-base symmetric lateral NPN bipolar transistors built on 8-inch SiGe-on-insulator (SiGe-OI) wafers with CMOS-like process. Such devices achieve the same collector current as the SOI bipolar transistor at ∼130 mV lower V BE from effective bandgap lowering, translating into lower voltage operation and power dissipation. Various techniques of Emitter engineering were studied and a novel partial HBT device structure was demonstrated with 3x reduction of hole injection into the emitter.

In this chapter, the transistors have been grouped into two major categories viz. Bipolar junction transistors (BJTs) and Field effect transistors (FETs). They have been further classified into p-n-p and n-p-n types; MESFET, MISFET, MODFET, MOSFET, n-channel, p-channel types etc. The details of BJTs such as their construction, fundamentals of operation, meaning and symbols of n-p-n and p-n-p are given. Forward and reverse biasing, transistor currents, circuit configurations and their characteristics are described. Comparison between CB, CE and CC configurations is presented. Amplification with different configurations of BJTs, their characteristics and uses, and phase reversal are discussed. Specifications of transistors and their terminal identifications are given. Meanings of cascade amplifier, Debye screening length, and Kirk effect are explained. Minute insight into the various topics are given through solved numerical and theoretical examples. Review questions, numerical problems and objective type questions are also given with their answers.

Current status is presented for the development and experimental verifcation of 0.18 μm high voltage CMOS integrated circuits with pad-based ESD protection made with the use of lateral bipolar transistor. Developed I/O pads provide 2000 V ESD protection.

Magnetic Bipolar Transistor is a promising novel device that provides electrical as well as magnetic control in order to exert desired output. In this paper relative performance of Magnetic Bipolar Transistor and its equivalent representation by Ebers-Moll model has been theoretically studied in terms of their common emitter current gain. We simulated the device to extract its behavior under varying applied field. A range of magnetic field is suggested within which the model follows the actual device characteristics. An analytical relation between common emitter current gain of Magnetic Bipolar Transistor and applied magnetic field is established. Finally a modification in the existing EbersMoll model is proposed to ensure better compatibility with actual characteristics.

A metal–oxide–semiconductor field-effect transistor (MOSFET) (or insulated-gate bipolar transistor (IGBT)) is controlled by the application of a voltage between its gate and its source (or emitter): for voltages between zero and a few volts, the transistor is turned off, then once a threshold voltage ( V GSth or V GEth ) is reached, the transistor allows current to pass, at first in a linear mode, and then tending toward a state of saturation. To ensure this happens, a voltage significantly higher than V GSth (or V GEth ) must be applied in order to guarantee the saturation: in practice, a voltage between 10 and 15 V is sufficient for this purpose. As the gate is physically equivalent to a capacitor frame, the transistor behaves in the same way from a control perspective.

A design for reliability methodology has been developed for electronics for low-temperature applications. A hot carrier aging (HCA) lifetime projection model is proposed to take into account the HCA impact on technology, analysis of parametric degradation versus critical circuit path degradation, transistor bias profile, transistor substrate current profile, and operating temperature profile. The most applicable transistor size can be determined in order to meet the reliability requirements of the electronics operating under low temperatures. This methodology and approach can also be applied to other transistor-level failure and/or degradation mechanisms for applications with varying temperature ranges

In this paper, the performance of high-voltage (10kV) 4H-SiC n- and p-channel IGBTs and n-channel MOS-Gated Bipolar Transistor (MGT) are investigated and compared using 2- dimensional numerical simulations. We have found that the MGT in SiC is not suitable for applications at high blocking voltages and the p-channel IGBT is a better choice because of a much higher conductivity modulation in the drift region.

Conventional treatment of amplifiers emphasizes relationships between specifications and circuit parameters and gives only marginal importance to relationships among the specification themselves. With a view that an understanding of tradeoffs among specifications is very important from the design perspective, a representation of amplifier results is presented that explicitly highlights these relationships. Results are presented for some commonly used bipolar and metal-oxide-semiconductor field-effect transistor (MOSFET) amplifier topologies.

Like many bumps on the electrotechnological landscape, the Gummel-Poon bipolar transistor model has remained in existence for both historical and technical reasons. An extended version of the model was incorporated into SPICE, which eventually became the dominant software tool for electronic circuit design. The Gummel-Poon base-resistence model began as an attempt to make a physically correct description of base resistance yet created more problems than it solved.