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The unprecedented high-speed switching of wide bandgap power devices may change the partial discharge (PD) behaviors of power modules, busbars, and loads. However, very little research has been published on PD behaviors under square-wave pulses with ultrafast dv/dt . To address this problem, this article studies the PD behaviors of direct bonded copper samples with different trench distances and chamfer radii under single and repetitive square pulses with ultrafast dv/dt . The results show that for the single-pulse excitation partial discharge inception voltage (PDIV) decreases with increasing rise time if the pulsewidth is shorter than 300 μs, and PDIV decreases with increasing pulsewidth. For repetitive pulse excitation, PDIV increases linearly with trench distance if the chamfer radius is larger than 0.5 mm, while it follows a concave curve if the chamfer radius is less than 0.5 mm. On the other hand, for a fixed trench distance, the PDIV changes quadratically with the chamfer radius increasing from 0 (right angle) to 0.7 mm. Based on the experimental results, a PD model with bubble expansion theory is to explain the PD mechanism under ultrafast dv/dt excitation, and an empirical equation for PDIV prediction is also derived.

This paper presents a self-sustained circuit building block (CBB) that utilizes 10-kV silicon carbide (SiC) devices as the main switches. The CBB achieves a self-sustained operation by powering the gate drives of its main switches with the energy from its dc bus capacitor. The CBB can serve as one of the submodules in a multilevel converter for high-voltage applications. This paper focuses on the design of the 10-kV SiC device’s gate drive and its associated auxiliary power supply (APS). The gate drive and its APS are the major technical challenges in the CBB development. The gate drive in the CBB features a common mode transient immunity (CMTI) over 200 kV/ $\mu \text{s}$ and fast protection functions. Its APS is based on an active voltage divider concept and achieves 7-kV input voltage with a simple circuit structure and control scheme. The operational principles and design guidelines of the gate drive and its APS are presented in detail. Test results of the CBB in a double-pulse test setup with a 7-kV dc bus voltage are presented to validate the design. Reliable operation of the CBB is demonstrated under dv/dt up to 100 kV/ $\mu \text{s}$ .

A unique three-step short-circuit protection method is proposed for the 650-V enhancement mode (E-mode) gallium nitride high-electron mobility transistor (GaN HEMT). This method can quickly detect the short-circuit event, reduce gate voltage to enhance the device short-circuit capability, and turn off the device under fault after confirmation. Experimental results prove that with this method, the short-circuit fault detection time for E-mode GaN HEMT is shortened from 2 μ s to several tens of nanoseconds, and the device can be successfully protected from fatal failure under high dc bus voltage without mistriggering.

Presented in this paper is an optimization method to improve the dynamic performance of high-voltage super-cascode power switches (SCPSs) by implementing silicon carbide (SiC) junction field-effect transistor (JFET). The basic operating principle of SCPS is explained at the beginning of the paper. Equivalent circuit models are outlined next, with equations describing the voltage distribution among each SiC JFET during switching transients. Based on the sensitivity analysis, a component optimization method for balancing the SCPS internal voltage is proposed, which effectively eliminates the overvoltage. This significantly reduces the switching loss and the chance of diode avalanche. Compared with the nonoptimized case, the turn-on loss of the SCPS is reduced to 8.85%, and the turn-off loss reduces to 48.4%.

With the increasing power rating of wide bandgap (WBG) devices in parallel, the system reliability encounters unprecedented challenges. Artificial intelligence (AI) methods could be introduced to monitor device health conditions and realize intelligent control for each device. In this paper, an intelligent health monitoring system is designed for the future AI implementation for paralleled devices with a fast dv/dt output. The detailed system circuitry and layout are discussed. The proposed system consists of monitoring and control functions. For the monitoring function, a measurement board is designed to capture the device temperature, turn on and turn off drain-to-source voltage, drain-to-source current. For the control function, a gate drive board is shown with the ability to select various gate voltage and gate resistance based on the control signals. Experimental verifications are provided at the end.

Modular multilevel converters (MMC) are popular for high-voltage, high-power electric energy conversion. To improve the reliability of MMCs, fault diagnosis and tolerant control have been studied by many researchers. Fault reconfiguration, one important step of the fault tolerant control, has become a challenge, especially under high-voltage operation. Arm current overshoot occurs during the reconfiguration if the MMC does not provide redundant submodules (SMs). Existing publications focus on the fault detection and localization. This work investigates the reconfiguration and proposes a suppression control strategy for the overcurrent. The strategy does not require redundant SMs. The proposed method is simulated in Matlab/Simulink and validated by experiments based on a three-phase MMC using an RL load.

Despite the several advantages, SiC MOSFETs suffer from issues such as low current carrying capacity, device degradation, etc. In this study, we explore the applications of Artificial Intelligence algorithms in optimizing the operation of SiC MOSFETs. We introduce the different notions of learning algorithms and provide a summary on their applications. In particular, we discuss earlier applications of AI algorithms in studying the properties of SiC MOSFETs, and highlight some challenges associated with parallel operation of SiC MOSFETs.

In this paper, a dv/dt filter is designed for the modular multilevel converters (MMCs) based variable frequency motor drives. This concept utilizes the inherent arm inductors of the MMC as a part of the output low-pass filter, thus eliminating the need for an add-on inductor. Particularly, a mathematical model is proposed to optimize the filter loss and volume for a given dv/dt requirements. It turns out that with SiC-MOSFET-based high switching frequency operation, the dv/dt filter improves the output power quality and alleviates the voltage stress in motor drive applications. For applications with various requirements on filter volume and loss, weighted-sum optimal solutions are presented. Simulation results based on a seven-level MMC are provided to validate the theoretical analysis.

The existing concept of aviation turboelectric distributed propulsion for passenger aircraft relies on direct current (DC) for power transmission and distribution. The mass and efficiency performance of DC-based propulsion systems becomes challenging as the system power rating increases. This work proposes a turboelectric distributed propulsion based on brushless doubly-fed machines, which will minimize the power conversion, enhance the mechanical reliability, and strengthen the fault-tolerance capability. This paper presents the background of the proposed turboelectric distributed propulsion along with the system modeling, control algorithm development, and preliminary simulation results of a full flight profile.

This paper seeks to study the contributing factors to current mismatch among parallelled SiC power modules, including the gate driver circuits, and the impedance of the bus barsm, the load connection and the load impedance. Compared with using silicon power devices, the effect of impedance asymmetry and inductive coupling is more pronounced with SiC power modules due to significantly lower on-resistance, lower load inductance and higher steady state di/dt. It is also revealed that nanosecond-level mismatch in the gate driver circuits can lead to significant dynamic current mismatch. Hardware tests and detailed simulations are carried out to explore these effects, and finally achieving 2.41% mismatch in dynamic switching energy and minimal mismatch in the steady state current sharing.

This paper compares the long-channel and short-channel 3300-V, 5-A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) manufactured by GeneSiC regarding static characteristics and short-circuit (SC) sustaining capability. Their saturation currents were measured up to 2200-V drain bias at different gate voltages. The SC withstand times of two types of devices were measured at 2200-V drain voltage and 1S-V gate voltage. Their SC test results were compared with 1200-V SiC MOSFETs from four different manufactures, which suggested that SiC MOSFETs with longer channel length should have longer sustaining times in a SC event. In addition, the device dynamic characteristic was evaluated. A comprehensive simulation program with integrated circuit emphasis (SPICE) model was developed based on the device test results.

With a growing number of silicon carbide (SiC) devices used in the modular multilevel converter (MMC) based medium voltage motor drive systems, the reflected wave phenomenon (RWP) under high dv/dt needs to be studied. In this paper, the voltage reflection in the MMC based motor drives is analyzed with a focus on the impact of the leakage inductance of the arm inductors. A seven-level MMC built with 1.7 kV SiC MOSFETs is modeled and simulated. The simulation results show that the leakage inductance of the arm inductors helps reduce the dv/dt at the MMC output but increases the voltage stress on the arm inductor windings and the load. A simple method is proposed to mitigate dv/dt and voltage overshoots applied to the machine windings. Presented simulation and experimental results validate the proposed method.

A high-reliability auxiliary power supply (APS) for gate drive circuits is crucial to utilization of emerging medium voltage (MV ≥ 10 kV) Silicon Carbide (SiC) devices in high voltage applications. This paper proposes an active voltage divider based APS with lower arm voltage regulation. The proposed APS circuit is targeting the application of MV SiC devices in modular multilevel converters (MMCs). It can harvest energy from a MV (≥ 7 kV) dc bus to provide an isolated low voltage output to gate drive circuits of MV SiC devices. Compared to existing APS solutions, it can achieve a high input voltage (≥ 7 kV) with simple circuit structure and control scheme. In this paper, the working principle of the proposed APS is presented and a circuit design example is shown. A circuit prototype with 7 kV input and 15 V/10 W output has been built and tested to verify the effectiveness of the proposed solution.

Medium-voltage motor systems with adjustable- speed drives are employed in a wide range of applications. The adoption of medium-voltage Silicon Carbide (SiC) devices in motor drives can improve motor system’s efficiency, power density, and dynamic response. But the high switching dv/dt (short rise time) produced by SiC devices increases the stress on the motor winding insulation and leads to partial discharges. This paper studies the partial discharge in the medium-voltage motor winding subjected to two-level PWM waveforms produced by medium-voltage SiC devices. Partial discharge inception voltages (PDIVs) and repetitive partial discharge inception voltages (RPDIVs) of the motor winding at various rise time, switching frequencies and modulation index are tested. Statements on PD behaviors are analyzed based on the test results.

The unprecedented high speed switching of Wide Bandgap (WBG) power devices may change the partial discharge (PD) mechanism inside power modules. However, very few research have been published on PD research methods and PD behaviors under ultra-high dv/dt excitation voltages. To address these problems, a three-step PD study method is proposed in order to comprehensively study PD mechanism inside power module with ultra-high dv/dt excitation voltages. The three-step study consists of PD tests under single pulse, repetitive pulses, and Sinusoidal Pulse Width Modulation (SPWM) pulses. The preliminary results of single pulse tests show influences of the rise time and the pulse width on PD behaviors in power modules. Based on test data, a PD model based on the bubble expansion theory is provided to explain results. The results presented in this paper can provide a better understanding of PD mechanism in power modules under high dv/dt excitations.

This paper focuses on the short circuit (SC) tests of four commercial TO-247 packaged silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with voltage ratings of 900 V and 1200 V at room temperature. The test results of the SiC devices are compared with that of super junction silicon (Si) MOSFETs which underwent identical test procedures. The current saturation characteristics were tested at over 50% of their rated voltages with 1-µs turn-on pulses. The test results show that the SiC MOSFETs can sustain much higher power density during short circuit conditions relative to their Si counterparts. However, there are several challenges in sustaining a 10-µs SC time without significant degradation or failure with the drain-to-source voltage set at half of the rated voltage and the gate set to the full rated voltage.

The use of wide-bandgap (WBG) semiconductor device is increasing due to its capability to operate at much higher voltage, frequency and temperature compared with traditional semiconductor device. WBG semiconductor device is capable to generate voltages with ultra-high dv/dt (ultra-short rise time), which would alter the voltage stress in various electrical apparatus, e.g., inverter-controlled motors, and consequently change partial discharge (PD) behavior. Combine this with the fact that PD detection in inverter-controlled motor winding, even with slow-rising voltages, is intrinsically complicated, the study of PD behavior under ultra-fast squarewave voltages is much needed. In this paper, experimental observations and results for twisted pair samples stressed by an impulse generator with the ability of generating ultra-fast square-wave voltage are presented. Statements and hypotheses on PD behaviors and mechanism under ultra-fast dv/dt squarewave excitations are also put forward based on the test results.

Partial discharge (PD) is more likely to happen in the power module due to the increasing switching speed of new generation semiconductors. However, little research has been done to study the PD behaviors under very fast dv/dt (above $50 \mathrm{kV}/\mu\mathrm{s}$ ) repetitive square-wave voltages. To address this problem, PD behaviors of designed direct bonded copper (DBC) samples with different trench distances and chamfer radiuses under fast dv/dt ( $130 \mathrm{kV}/\mu\mathrm{s}$ ) repetitive square voltages are studied. The results show that, for different trench distances, the partial discharge inception voltage (PDIV) increases linearly with increasing trench distances when the chamfer radius is larger than 0.5 mm, while PDIV shows a hump curve when the chamfer radius is less than 0.5 mm. The apparent charge becomes 23 nC with a large dispersion when the trench distance is 0.5 mm. For different chamfer radiuses, PDIV presents a U-shape shape curve with increasing radiuses from the zero (right angle) to 0.7 mm. The apparent charge is about 325 pC with a large dispersion when the chamfer radius is zero. The detailed experiment results and discussions are presented in this paper.

Unexpected premature insulation breakdown has been reported for many electric machines driven by variable speed drives (VSDs). A major cause is the reflected voltage overshoots at the machine winding caused by the pulse voltage excitation, leading to severe stress on the insulation system. At The Ohio State University (OSU), we have started a series of efforts to understand the degradation and breakdown of the insulation systems in electric machines driven by VSDs. This paper reports our activities on partial discharge (PD) detection and characterization for random-wound low voltage and form-wound medium voltage coils excited by PWM voltages. A PD detection platform has been established consisting of three main systems: the testing samples and setups, the pulsed voltage generation system, and the PD detection system. One silicon (Si) based and two silicon-carbide (SiC) based pulsed voltage generators were employed to produce voltage excitations with a magnitude up to 10 kV and a $dV/dt$ up to $\mathbf{70\ kV}/\mu\mathbf{s}$ . The PD detection system, moreover, installed nine sensors catering to five different physical manifestations during PD: electrical current, electromagnetic wave, optical light emission, acoustic ultrasound emission and chemical ozone emission. The detection effectiveness of each type of sensor is presented and compared using twisted pairs of magnet wire samples. The demonstrated results hope to provide a better understanding of the effect of VSDs on the behaviors of PDs in electric machine winding insulation systems, and also some insight for the selection and evaluation of PD detectors for various VSD applications.

The Enhancement-mode (E-mode) Gallium Nitride High-Electron Mobility Transistor (GaN HEMT) has several hundred nanosecond level short circuit withstand time, much shorter than that of the silicon (Si) devices. Reliable ultra-fast protection solutions for the GaN HEMTs are in great demand. In this paper, a three-step GaN HEMT short circuit protection solution is proposed, including ultra-fast detection, active gate clamping and de-saturation circuit confirmation. First, the GaN HEMT short circuit capability under various gate voltages has been explained. Based on the safe protection boundary, the three- step protection solution is proposed. Experimental results prove that with the proposed protection method, the short circuit fault can be detected within 36 ns, and the short circuit energy is reduced with the ultra-fast detection and gate voltage clamping. Eventually, the GaN HEMT can be successfully protected from fatal failure up-to 400 V dc bus.

A potential overvoltage issue during turn-on transient of the silicon carbide (SiC) junction gate field-effect transistor (JFET) based high voltage super-cascode power switch (SCPS) is first identified. The overvoltage issue caused by the JFET slow sequential turn-on is investigated, and the corresponding mitigation method is proposed. Based on this, an optimization method is proposed to improve JFET voltage balancing during off-state as well as eliminating the overvoltage during turn-on transient in the high voltage SiC super-cascode structure. The analysis is verified with experimental results. The overvoltage on the top JFET is eliminated and the total turn-on time is reduced from 518 ns to 82 ns. In the end, the influence of the voltage balancing capacitor tolerance on the voltage distribution is discussed.

Medium voltage (MV) Silicon Carbide (SiC) power devices have become available as engineering samples. Recent studies show that they outperform their Silicon (Si) counterparts regarding voltage blocking capability, specific on-state resistance, switching speed and maximum allowable junction temperature. It is projected that MV SiC power devices will bring revolutionary changes in medium and high voltage applications such as traction drives for locomotives, industrial motor drives, utility power transmission systems, etc. This paper presents a summary of recent advances in MV SiC power devices, including MOSFETs, IGBTs, GTOs and super-cascode devices. Technical challenges of their applications such as device packaging, gate drive design and gate drive auxiliary power supply design are discussed. Testing results of three state-of-the-art MV SiC devices, including a 4 kV, 5 A discrete SiC MOSFET, a 4.5 kV, 40 A SiC super-cascode device and a 10 kV, 40 A SiC MOSFET power module, are presented as examples.

With the development of voltage Silicon Carbide (SiC) devices, motor windings and power inverters tend to encounter pulse width modulation (PWM) pulses with higher dv/dt. However, existing pulse generators for partial discharge testing cannot generate ultrahigh dv/dt with nanosecond rising time to emulate the rising edge of the PWM from SiC based converters. To address this problem, a new PWM-type pulse generator with ultra-high dv/dt output is designed. The generator can generate bipolar outputs at ± 1.2kV with a slew rate of $\pm 50kV/\mu s$ and unit polar output waveform at 1.2 kV with a slew rate of 250 kV$/\mu s$. The width and frequency of the bipolar PWM-type pulses can be accurately controlled. The overall volume of the generator is only 55 $in^{3}$. The detailed description of the circuit, its operation modes and the method to adjust and optimize the output voltage’s dv/dt are presented in this paper.

The Enhancement-mode (E-mode) Gallium Nitride High-Electron Mobility Transistor (GaN HEMT) has proven excellent electrical performance in various applications. Meantime, multiple comprehensive studies on the short circuit behavior show that GaN HEMTs has much shorter short circuit withstand time compared to conventional silicon (Si) devices. In this paper, the GaN HEMT short circuit capability is first introduced. Based on the testing results, the voltage dip on the phase-leg dc voltage under short circuit condition is proposed to be the short circuit detection signal, and the corresponding detection circuit and ultra-fast short circuit protection method is depicted. Finally, experimental results prove that with the proposed protection method, soft turn-off can be initiated within 200 ns and the short circuit current can be terminated in 281 ns.

A method for voltage balancing capacitor selection of high voltage silicon carbide (SiC) Junction Gate Field Effect Transistor (JEFTs) based super-cascode power switch (SCPS) is presented in this paper. The proposed method can effectively reduce the device switching loss as well as thermal stress on critical components caused by repetitive avalanche. The basic operation principle of SCPS is shown at the beginning of the paper with critical modes. Then, equations to describe the voltage distribution among all the SiC JEFTs have been derived. Based on the derived equations, a sizing method of the SCPS voltage balancing capacitors is proposed to accelerate the device switching speed and minimize the avalanche time of its internal diodes. Compared with no voltage balancing capacitor case, the turn-on loss of the SCPS with sized capacitors has been reduced to 9.7%. The turn-off loss has been reduced to 48.4%.

The emerging medium voltage (MV ≥ 10 kV) Silicon Carbide (SiC) devices are promising device candidates for high voltage applications, such as high voltage direct current transmission (HVDC) systems and flexible alternating current transmission systems (FACTS), where multilevel converters are often employed. Two main prerequisites for successful implementation of MV SiC devices in these high voltage applications are 1) a gate drive circuit with high common mode transient immunity (CMTI) and fast protection functions and 2) a high-reliability auxiliary power supply (APS) circuit for the gate drive circuit that can satisfy the insulation requirement. This paper presents the development of a gate drive system, targeting the utilization of 10 kV SiC devices in multilevel converters for high voltage applications. The developed gate drive system includes a gate drive circuit and an APS circuit. The APS circuit is based on the active voltage divider concept and it can harvest energy from a MV (≥ 7 kV) dc bus to provide an isolated low voltage output to gate drive circuits with simple circuit structure and control scheme. The developed gate drive circuit features high CMTI (> 200 kV/μs) and comprehensive protection functions, including overcurrent protection, isolated gate drive failure protection, active miller clamping, under-voltage lockout, soft turn-off, and fault reporting. The working principles and design considerations for the gate drive and APS circuits are presented in this paper. To validate the circuit design, the gate drive system was tested in a 10 kV SiC device based double pulse tester with 7 kV dc voltage.

In this paper, an improved adaptive method for dc arc faults detection is proposed based on current envelope and Hurst exponents. The method is developed to be used in dc electrical distribution systems (EDS) including PV systems, DC micro-grids, and 48 V mild hybrid electric vehicles. The proposed method is shown to be effective in arc detection and immune to switching harmonics, high di/dt transients, sudden load changes, and noisy load profiles. A test setup is built and several hundred dc arcs were generated under different operation conditions including air gap, current, and various electrode thicknesses.

Silicon Carbide (SiC) power devices with super-cascode structure provide a cost-effective solution for high performance medium voltage power switches. However, these SiC super-cascode devices are still in the early development stage, and limited information on the device characteristics is available. This paper presents the characterization and evaluation of a 4.5 kV, 40 A SiC super-cascode device which consists of five 1.2 kV SiC normally-on JFETs and one 20 V Silicon (Si) MOSFET in series connection. Extensive static and dynamic characterization tests were performed on the device at various test conditions. The device static characteristics, including leakage current, gate threshold voltage, I-V characteristics, and C-V characteristics, were recorded at different temperatures. The device dynamic evaluation was done using a double pulse test (DPT) circuit with an inductive load. The DPT dc bus voltage was up to 3 kV and the load current was varied from 5 A to 40 A. The device switching speed and switching energy loss at different load currents were measured. The device test results showcase its potential in medium and high voltage applications.

Dc arc faults may result in serious damage to both stationary and mobile dc power systems. This paper presents a new detection method for dc arcs using Hurst exponents. Compared to other methods such as the Fast Fourier Transform (FFT) and the Wavelet Transform, the proposed method is adaptive and is more immune to power electronics switching harmonics. A test setup to generate dc arcs is built and the Hurst exponent algorithm is applied. The algorithm is studied under different load conditions and noisy environments. The Hurst exponent method is shown to be effective in detecting dc arcs within hundreds of milliseconds and bot miss-triggered by step load changes, switching harmonics, and load profiles.

Power Electronic converters and electric motor drives have found increased application in automobiles, ships and microgrids. These devices when driving loads in a regulated fashion act as Constant Power Loads (CPLs). CPLs can be power converters, each regulating input current to maintain a constant output power. These converters can cause destabilizing effects on the grid due to their nonlinear behavior. This paper studies the effect of CPLs on DC Microgrids and analyzes their stability. It also demonstrates a method to dynamically stabilize these loads locally by converting them into a smart resistor using high bandwidth power converters and energy storage units. The bandwidth offered by this circuit enables the DC Microgrid to locally control any instabilities on the grid. The proposed method decentralizes the control effort making the microgrid more intelligent and reliable. Analysis is verified using simulation tools and validated using a hardware test setup.

This paper presents a comparison study of three isolated DC/DC circuit topologies, LLC resonant circuit, phase shift bridge circuit and phase shift quasi switched capacitor (QSC) circuit. The device stress of three circuits is compared using total switching device power (SDP) which can be used as an indicator of circuit efficiency, device cooling requirement, device packaging requirement and cost of the power electronics converter. Transformer is the main passive component in the circuit that affects significantly the converter power density. The transformer area products (AP) of three circuits are thus calculated and compared. Device loss oriented circuit design is carried out on the three circuit topologies for 1 kW, 400 V to 48 V telecomm power supply application using commercially available GaN devices. Basing on the circuit design results, the device loss of three circuits is calculated and compared at various switching frequencies and load conditions. In the end, a 1 kW, 0.5 MHz, 400–48 V GaN device based phase shift QSC converter prototype is built and tested to verify the analysis and showcase the circuit performance.

The medium power rating two-level three phase voltage source inverter is among the most popular power conversion systems. The typical switching frequency of the commercial medium power rating inverter, however, is limited to tens of kHz. By increasing the switching frequency and using emerging gallium-nitride devices, the size of the overall system can be greatly reduced. This paper begins by reviewing all commercially available GaN power transistors and their package technologies. The GS66516T device from GaN Systems is selected due to its suitable ratings and superior package performance. Then, a half-bridge structure is designed for this device to achieve low parasitic inductance and strong cooling capability at the same time. The dynamic characterization results of this 650V/60A Enhancement-mode GaN transistor are extracted with the proposed half-bridge structure. A gate drive circuit with comprehensive protection function is integrated. Based on the proposed phase-leg structure, a 10 kW three phase inverter prototype is built and the experimental waveform is shown at the end.