121 results on '"Bushnell, Michael L."'
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2. Logic Verification
3. Fault Effects
4. Redundancy Identification
5. Experimental Results
6. Justification in Finite State Space
7. Sequential Circuit Test Generation
8. Justification Equivalence
9. Introduction
10. Conclusion
11. A new classification of path-delay fault testability in terms of stuck-at faults
12. False-Path Removal Using Delay Fault Simulation
13. Test Generation for Mixed-Signal Devices Using Signal Flow Graphs
14. Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
15. Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests
16. A Functional Decomposition Method for Redundancy Identification and Test Generation
17. Sequential circuit test generation using dynamic justification equivalence
18. A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults
19. The path-status graph with application to delay fault simulation
20. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
21. Energy minimization and design for testability
22. On variable clock methods for path delay testing of sequential circuits
23. Improving a nonenumerative method to estimate path delay fault coverage
24. Fault coverage estimation by test vestor sampling
25. Conclusion
26. Justification Equivalence
27. Introduction
28. Logic Verification
29. Efficient Branch and Bound Search with Application to Computer-Aided Design
30. Redundancy Identification
31. The Sest Algorithm
32. Sequential Circuit Test Generation
33. Justification in Finite State Space
34. Experimental Results
35. Fault Effects
36. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits
37. Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults
38. Graphical $I_{\rm DDQ}$ Signatures Reduce Defect Level and Yield Loss
39. Power Grid Analysis of Dynamic Power Cutoff Technology
40. SPARTAN: a spectral and information theoretic approach to partial-scan
41. Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors
42. Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST
43. Analog Circuit Testing Using Auto Regressive Moving Average Models
44. A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits
45. Transistor Sizing of Logic Gates to Maximize Input Delay Variability
46. A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.
47. An efficient path delay fault coverage estimator
48. Design for testability for path delay faults in sequential circuits
49. A solvable class of quadratic 0–1 programming
50. An efficient path delay fault coverage estimator.
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