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Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (∼830 mm2) to two reticle size (∼1700 mm2). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5th generation CoWoS-S (CoWoS-S5) based on a Si interposer as large as three full reticle size (∼2500 mm2) by a novel 2-way lithography stitching approach. This will accommodate a multiple of logic chips at a total area of 1200 mm2 (with chiplets) together with eight HBM stacks. Besides the dimensional increase of the Si interposer, new features are incorporated to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include an integrated deep trench capacitor (iCap) for enhanced power integrity, 5 layers of sub-micron Cu interconnect with reduced sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.

One of the prominent challenges for widespread adoption of silicon photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications. As a result, there is a diversity of SiPh integrated solutions proposed or demonstrated, but none is considered as a common solution. In this paper, we will first survey industry proposed photonic engine structures in monolithic and heterogeneous integration on their strengths and weaknesses. We will then propose a compact and universal PE structure - COUPE (COmpact Universal Photonic Engine) that could consolidate different requirements onto the same integration platform. COUPE has the electrical IC – photonic IC integration with the electrical interface designed to minimize the EIC-PIC coupling loss. Compared with industry proposed PE technology, COUPE can provide low insertion loss for both grating coupler (GC) and edge coupler (EC). For either GC or EC, the COUPE is a solid structure without cavities or mechanically weak parts, thus enabling low insertion loss without contamination or mechanical concerns. COUPE also has the flexibility to be integrated easily with host ASIC to form a co-package structure. The COUPE integration scheme can meet the most demanding system requirements and pave the way for SiPh-based wafer level system integration (WLSI) for high performance computing applications.

This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.

SOX6 belongs to a family of 20 SRY-related HMG-box-containing (SOX) genes that encode transcription factors controlling cell fate and differentiation in many developmental and adult processes. For SOX6, these processes include, but are not limited to, neurogenesis and skeletogenesis. Variants in half of the SOX genes have been shown to cause severe developmental and adult syndromes, referred to as SOXopathies. We here provide evidence that SOX6 variants also cause a SOXopathy. Using clinical and genetic data, we identify 19 individuals harboring various types of SOX6 alterations and exhibiting developmental delay and/or intellectual disability; the individuals are from 17 unrelated families. Additional, inconstant features include attention-deficit/hyperactivity disorder (ADHD), autism, mild facial dysmorphism, craniosynostosis, and multiple osteochondromas. All variants are heterozygous. Fourteen are de novo, one is inherited from a mosaic father, and four offspring from two families have a paternally inherited variant. Intragenic microdeletions, balanced structural rearrangements, frameshifts, and nonsense variants are predicted to inactivate the SOX6 variant allele. Four missense variants occur in residues and protein regions highly conserved evolutionarily. These variants are not detected in the gnomAD control cohort, and the amino acid substitutions are predicted to be damaging. Two of these variants are located in the HMG domain and abolish SOX6 transcriptional activity in vitro. No clear genotype-phenotype correlations are found. Taken together, these findings concur that SOX6 haploinsufficiency leads to a neurodevelopmental SOXopathy that often includes ADHD and abnormal skeletal and other features.

A low-temperature System-on-Integrated- Chip (LT-SoIC) technology has been successfully applied to multi-layer 3D memory cube integration, which enables high bandwidth, low power and small footprint memory for future HPC applications. In addition, using the technology, each memory layer can be thinned to required thickness to maintain total height while supporting more layer counts.Two LT-SoIC processes were presented. One is through-via reveal last and the other one is through-via reveal first. The through-via revealing of each stacked die is one of the most critical process steps. Various conditions of planarization on chip backside after the through-via revealing were studied to mitigate the corner or edge rounding issue, as it may cause poor bonding. By improving the back-side revealing process, we can achieve good bonding for multi-layer stacking, including DRAM stacking with 4-Hi/ 8-Hi/ 12-Hi, and SRAM stacking with 4-Hi, using the LT-SoIC technology.The bonding quality of the LT-SoIC is measured using I-V curve and shear stress equipment. Linear I-V curve was obtained to show it is an Ohmic contact and the bonding strength of >2.5J/m2 was measured to show good bonding force. The through-via chain resistances for 4-Hi SRAM and 4/8/12-Hi DRAM and the breakdown voltage for 8/12- Hi DRAM were measured, too. Reliable results were obtained to indicate the integrity of the through-via chains. After that, the bandwidth density and power consumption between typical 3D memory and the SoIC memory were compared. High bandwidth density and low power consumption are obtained in the SoIC memory. Clear advantages of the SoIC CoW stacking technology are realized for multi-layer memory stacking at low temperature.

A low temperature system-on-integrated-chip (SoIC) bonding and stacking technology is proposed and implemented for 3-D memory integration, such as 3-D static random access memory (SRAM) or dynamic random access memory (DRAM) cube. It extends not only 2-D pin count to 12000/mm2 but also overcomes the obstacle of the stacking height. 4-Hi, 8-Hi, and 12-Hi stacks, each with 1 base die and 4, 8, and 12 dies, respectively, are realized and demonstrated in this article. The daisy chains in the 4-Hi/8-Hi/12-Hi structures incorporating over 10 000 through silicon vias (TSVs) and bonds are tested with liner ${I}-{V}$ curves, which indicates the good bonding and stacking quality. The electrical link from base controller to top DRAM for 12-Hi and 16-Hi high bandwidth memory (HBM) structure is built up to study the bandwidth (BW) and power efficiency. Compared to $\mu $ bump technology, the BW for the 12-Hi and 16-Hi structures using SoIC bonding shows the improvement of 18% and 20%, respectively, under same pin pitch and the power efficiency has the improvement of 8% and 15%. For thermal performance, the 12-Hi and 16-Hi SoIC-bond structure is 7% and 8% better than those using $\mu $ bump technology, respectively. With this innovative SoIC bonding and stacking technology, the bond pitch is scalable to sub-micrometer and the die thickness is manageable to be thinner, which are prospected for the application of higher BW 3-D memory with tera byte (TB)/s per stack.

A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of the CoWoS provides the capacitance density of 300 nF/mm2 and low leakage current of

International audience; BACKGROUND: Patients who have had a stroke with unknown time of onset have been previously excluded from thrombolysis. We aimed to establish whether intravenous alteplase is safe and effective in such patients when salvageable tissue has been identified with imaging biomarkers. METHODS: We did a systematic review and meta-analysis of individual patient data for trials published before Sept 21, 2020. Randomised trials of intravenous alteplase versus standard of care or placebo in adults with stroke with unknown time of onset with perfusion-diffusion MRI, perfusion CT, or MRI with diffusion weighted imaging-fluid attenuated inversion recovery (DWI-FLAIR) mismatch were eligible. The primary outcome was favourable functional outcome (score of 0-1 on the modified Rankin Scale [mRS]) at 90 days indicating no disability using an unconditional mixed-effect logistic-regression model fitted to estimate the treatment effect. Secondary outcomes were mRS shift towards a better functional outcome and independent outcome (mRS 0-2) at 90 days. Safety outcomes included death, severe disability or death (mRS score 4-6), and symptomatic intracranial haemorrhage. This study is registered with PROSPERO, CRD42020166903. FINDINGS: Of 249 identified abstracts, four trials met our eligibility criteria for inclusion: WAKE-UP, EXTEND, THAWS, and ECASS-4. The four trials provided individual patient data for 843 individuals, of whom 429 (51%) were assigned to alteplase and 414 (49%) to placebo or standard care. A favourable outcome occurred in 199 (47%) of 420 patients with alteplase and in 160 (39%) of 409 patients among controls (adjusted odds ratio [OR] 1·49 [95% CI 1·10-2·03]; p=0·011), with low heterogeneity across studies (I(2)=27%). Alteplase was associated with a significant shift towards better functional outcome (adjusted common OR 1·38 [95% CI 1·05-1·80]; p=0·019), and a higher odds of independent outcome (adjusted OR 1·50 [1·06-2·12]; p=0·022). In the alteplase group, 90 (21%) patients were severely disabled or died (mRS score 4-6), compared with 102 (25%) patients in the control group (adjusted OR 0·76 [0·52-1·11]; p=0·15). 27 (6%) patients died in the alteplase group and 14 (3%) patients died among controls (adjusted OR 2·06 [1·03-4·09]; p=0·040). The prevalence of symptomatic intracranial haemorrhage was higher in the alteplase group than among controls (11 [3%] vs two [\textless1%], adjusted OR 5·58 [1·22-25·50]; p=0·024). INTERPRETATION: In patients who have had a stroke with unknown time of onset with a DWI-FLAIR or perfusion mismatch, intravenous alteplase resulted in better functional outcome at 90 days than placebo or standard care. A net benefit was observed for all functional outcomes despite an increased risk of symptomatic intracranial haemorrhage. Although there were more deaths with alteplase than placebo, there were fewer cases of severe disability or death. FUNDING: None.

A high performance 3D dipole antenna with metal thickness >100 μm for wide bandwidth and lateral radiation is realized on InFO package. 25 % wide fractional bandwidth, from 60 to 77 GHz, has been obtained. The beamforming capability of the antenna array system with 6 dBi gain is measured in a 40 nm CMOS RFIC co-designed system.

To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high-K (HK) based deep trench capacitors (DTC) have been integrated the first time in the silicon interposer with through silicon via (TSV) and fine-pitch interconnects for chip-on-wafer-on-substrate (CoWoS) integration. A specific capacitance density (C s ) of up to 340 nF/mm2 is achieved over a large capacitor array, providing a total capacitance (C t ) of up to 68 μF per interposer die. The HK dielectric has intrinsic time-dependent dielectric breakdown (TDDB) lifetime of > 1,000 years at an operation voltage (V cc ) of 1.35V, and a normalized leakage current (I LK ) density LK & V bd tailing) were observed. The high capacitance, low leakage, large area and reliability-proven Si-interposer integrated DTC, or iCap, provides superior PI performance and therefore greatly enhances the merit of using CoWoS for the next-generation heterogeneous wafer level system integration (WLSI).

Efficient trading under wholesale market competition reduces an electric grid’s energy costs for meeting time- and location-dependent demands. We analyse energy trading efficiency by estimating three newly developed sets of energy price difference regressions interconnected by their common root of energy price level regressions. Using a sample of ~ 0.6 million hourly observations for 01/01/2014 to 10/31/2020, our estimation documents energy trading efficiency of the 10 local resource zones across 15 American states administered by the Midcontinent Independent System Operator (MISO). We find MISO’s zonal energy markets integrated across space (zone j vs. zone k for j ≠ k) and time (day-ahead market vs. real-time market). However, these markets exhibit inter-day energy prices differences that move with the fundamental drivers (e.g., day-ahead forecasts for natural gas price and zonal wind generation) of day-ahead energy prices and their forecast errors. Inter-zonal day-ahead energy price differences move with the fundamental drivers and their zonal variations. Inter-zonal real-time energy price differences increase with inter-zonal day-ahead energy price differences and depend on zonal variations of the fundamental drivers’ forecast errors. Our empirics yield two important policy implications. First, enhancing inter-day trading efficiency requires accuracy improvements in (a) day-ahead forecasts for natural gas price, zonal load levels, and zonal wind generation, and (b) day-ahead scheduling of zonal nuclear and must-run generation. Second, improving inter-zonal trading efficiency requires mitigating inter-zonal transmission congestion via transmission capacity expansion, generation investment and demand reduction in a load pocket, and virtual bidding for inter-zonal energy price differences.

Producción Científica, Junction stability and donor deactivation in silicon at high doping limit has been a long-standing issue in advanced semiconductor devices. Recently, heavily doped epitaxial Si:P layer with phosphorus concentrations as high as 3 × 1021 at./cm3 has been employed in nanowire field-effect transistor (FET) devices for sub-3 nm technology node as low resistance source-drain and channel stressor. In such highly doped Si:P, the actual dopant activation is much less than nominal phosphorus concentration due to inactive phosphorus atoms arising from dopant-vacancy defects (PnV) clustering phenomenon. Even with state-of-the-art high temperature millisecond annealing, this epitaxial film is thermally unstable upon subsequent thermal treatments. To overcome this limitation, we demonstrate a selective dopant activation scheme which results from the dipole moments of inactive PnV structures within the crystal lattice and their direct energy coupling with the external electric field. It's found that superior stability in dopant activation can be achieved through microwave annealing when a specific temperature and field conditions are met using a triple-parallel-susceptor setup in the microwave cavity. Based on experimental results and ab-initio calculation, we proposed a model, whereas the microwave-PnV interactions result in a specific distribution of dopant defect dominated by thermally stable P4V clusters through elimination of unstable low order PnV, leading to the suppression of donor deactivation and achieving thermally stable junction., Ministerio de Ciencia, Innovación y Universidades (Project MOST-109-2628-M-008-004-MY3)

In this article, we problematize the concept of "culture" in genetic counseling. With globalization and increased mobility of both genetic professionals and clients, there is an increased acknowledgement of the impact of "culture" on a counseling process. There is, however, little agreement on what "culture" is. The essentialist understanding that has long been dominant in the medical literature views culture as a set of shared beliefs, attitudes and practices among a group of people. Such an approach does not account for the individual differences and the dynamic nature of genetic counseling encounters. Following Zayts and Schnurr (2017), we use the distinction between two orders of culture: culture1 that refers to the static, generalized understanding of culture that is external to the specific context, and culture2 , an analytic concept that denotes dynamic enactments of culture, emerging in the interaction. We use empirical data from genetic counseling sessions to illustrate these different facets of culture and to consider how and why speakers draw on them. The clinical implications of the study include highlighting the importance of cultural awareness among counselors, including cultural self-awareness, and demonstrating how authentic interactional data could be used to enhance cultural training in genetic counseling.

To accelerate GaN adoption, beyond-JEDEC system-level reliability should be done to prove the robustness of GaN in applications. In this paper, a new hard switching test vehicle (half-bridge RC load) was proposed & demonstrated to achieve system-like stress, flexibility of acceleration test, low system power consumption with large sample size, easy setup & control which can meet system-level reliability requirement.

Stroke thrombolysis with alteplase is currently recommended 0-4·5 h after stroke onset. We aimed to determine whether perfusion imaging can identify patients with salvageable brain tissue with symptoms 4·5 h or more from stroke onset or with symptoms on waking who might benefit from thrombolysis.In this systematic review and meta-analysis of individual patient data, we searched PubMed for randomised trials published in English between Jan 1, 2006, and March 1, 2019. We also reviewed the reference list of a previous systematic review of thrombolysis and searched ClinicalTrials.gov for interventional studies of ischaemic stroke. Studies of alteplase versus placebo in patients (aged ≥18 years) with ischaemic stroke treated more than 4·5 h after onset, or with wake-up stroke, who were imaged with perfusion-diffusion MRI or CT perfusion were eligible for inclusion. The primary outcome was excellent functional outcome (modified Rankin Scale [mRS] score 0-1) at 3 months, adjusted for baseline age and clinical severity. Safety outcomes were death and symptomatic intracerebral haemorrhage. We calculated odds ratios, adjusted for baseline age and National Institutes of Health Stroke Scale score, using mixed-effects logistic regression models. This study is registered with PROSPERO, number CRD42019128036.We identified three trials that met eligibility criteria: EXTEND, ECASS4-EXTEND, and EPITHET. Of the 414 patients included in the three trials, 213 (51%) were assigned to receive alteplase and 201 (49%) were assigned to receive placebo. Overall, 211 patients in the alteplase group and 199 patients in the placebo group had mRS assessment data at 3 months and thus were included in the analysis of the primary outcome. 76 (36%) of 211 patients in the alteplase group and 58 (29%) of 199 patients in the placebo group had achieved excellent functional outcome at 3 months (adjusted odds ratio [OR] 1·86, 95% CI 1·15-2·99, p=0·011). Symptomatic intracerebral haemorrhage was more common in the alteplase group than the placebo group (ten [5%] of 213 patients vs one [1%] of 201 patients in the placebo group; adjusted OR 9·7, 95% CI 1·23-76·55, p=0·031). 29 (14%) of 213 patients in the alteplase group and 18 (9%) of 201 patients in the placebo group died (adjusted OR 1·55, 0·81-2·96, p=0·66).Patients with ischaemic stroke 4·5-9 h from stroke onset or wake-up stroke with salvageable brain tissue who were treated with alteplase achieved better functional outcomes than did patients given placebo. The rate of symptomatic intracerebral haemorrhage was higher with alteplase, but this increase did not negate the overall net benefit of thrombolysis.None.

This paper evaluates chromium aluminum silicon nitride (CrAlSiN) hard films fabricated using reactive magnetron co-sputter with adjusted deposition parameters. The hard films were prepared on glass and tungsten carbide tools at a substrate temperature of 350 °C. The targets were Cr, W and Si, with 40 sccm Ar as the plasma gas and 40 sccm N 2 as the reactive gas. An orthogonal array, the signal-to-noise ratio and analysis of variance are used to analyze the effect of the deposition parameters. Using the Taguchi method for design of a robust experiment, the interactions between factors are also investigated. The main deposition parameters, such as Cr direct current (DC) power (reverse time 5 μs), Al DC power (reverse time 5 μs), Si radio frequency (RF) power, and bias the substrates with RF power, were optimized, with regard to the microstructure, morphology, mechanical and tribological properties of CrAlSiN films. The results of this study show that the substrate bias has the most significant effect on hardness. The experimental results also show that the Taguchi method allows a suitable solution to the problem, with the minimum number of trials compared to a full factorial design. With the optimized CrAlSiN hard films deposition conditions, the hardness, Young's modulus and friction coefficient were 31.26 Gpa, 258.58 Gpa and 0.50, respectively. Further, this study also investigates the properties of machining MAR-M247 nickel-based superalloy, testing differently coated tools in dry conditions.

This paper examines wholesale price behavior of energy and ancillary services (AS) in the day-ahead market (DAM) and real-time market (RTM) of the Midcontinent Independent System Operator (MISO), the second largest regional transmission organization in the U.S. Using hourly data for the period of 12/19/2013 to 12/30/2017, it estimates a system of 16 electricity price regressions that recognizes the interdependence of MISO’s electricity products. Its key findings are: (1) MISO’s regional DAM energy prices increase with the day-ahead forecasts of natural gas price and MISO’s regional loads, PJM’s DAM energy price at its MISO interface, and MISO’s DAM AS requirements; (2) MISO’s regional DAM energy prices decline with DAM schedules for nuclear and wind generation; (3) MISO’s regional RTM energy prices increase with, but diverge from, MISO’s regional DAM energy prices; (4) MISO’s system-average DAM AS prices increase with MISO’s system-average DAM energy price and procured amounts of AS; and (5) MISO’s system-average RTM AS prices increase with MISO’s system-average RTM energy price and system-average DAM AS prices. These findings imply that MISO can reduce its DAM and RTM prices for energy and AS by accelerating wind generation development, expanding demand-side-management, and easing inter-regional transmission congestion.

This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.

A novel 3D InFO inductor is developed to integrate with TSMC 16nm FinFET devices for high efficiency integrated voltage regulator (IVR) design. The 3D InFO inductor is designed using thick through-InFO-via (TIV) copper, where the form factor is 1.4 × 2.2 × 0.15 mm3. It performs 2.14 nH inductance at 140 MHz and 3.2 mΩ resistance at DC. The resistance of power delivery network (PDN) between inductor and load is 1.1 mu. The InFO technology provides the low resistance 3D inductor and PDN concurrently for the IVR system design to achieve a peak power efficiency of 93%.

For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.

In this paper, important parameters of the p-buried layer of a high-voltage reduced surface field p-n diode are analyzed and discussed in terms of effects on device performance, including breakdown voltage and specific turn-on resistance, Ron,sp. Guidelines for optimizing the vertical position, lateral location, and doping concentration of the p-buried layer are suggested. The experimental results demonstrate that the p-n diode with the proposed p-buried layer optimization design can improve breakdown voltage by 30.7% but only increases 2.7% in specific on-resistance Ron,sp.

For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of

Radial basis functions (RBFs) have proved to be very flexible in representing functions. Based on the idea of the analog equation method and radial basis functions, in this paper, ill-posed Cauchy problems of elliptic partial differential equations (PDEs) with variable coefficients are considered for the first time using the method of approximate particular solutions (MAPS). We show that, using the Tikhonov regularization, the MAPS results an effective and accurate numerical algorithm for elliptic PDEs and irregular solution domains. Comparing the proposed MAPS with Kansa's method, numerical results show that the proposed MAPS is effective, accurate and stable to solve the ill-posed Cauchy problems.

The precise transcriptional regulation of gene expression is essential for vertebrate development, but the role of posttranscriptional regulatory mechanisms is less clear. Cytoplasmic RNA granules (RGs) function in the posttranscriptional control of gene expression, but the extent of RG involvement in organogenesis is unknown. We describe two human cases of pediatric cataract with loss-of-function mutations in TDRD7 and demonstrate that Tdrd7 nullizygosity in mouse causes cataracts, as well as glaucoma and an arrest in spermatogenesis. TDRD7 is a Tudor domain RNA binding protein that is expressed in lens fiber cells in distinct TDRD7-RGs that interact with STAU1-ribonucleoproteins (RNPs). TDRD7 coimmunoprecipitates with specific lens messenger RNAs (mRNAs) and is required for the posttranscriptional control of mRNAs that are critical to normal lens development and to RG function. These findings demonstrate a role for RGs in vertebrate organogenesis.

In this paper we propose to apply the golden section search algorithm to determining a good shape parameter of multiquadrics (MQ) for the solution of partial differential equations. We use two radial basis function based meshless collocation methods, the method of approximate particular solutions (MAPS) and Kansa's method, to solve partial differential equations. Due to the severely ill-conditioned matrix system using MQ, we also consider the truncated singular value decomposition method (TSVD) to regularize the smoothness of the error versus shape parameter curve so that a reasonably good shape parameter can be identified. We also analyze cost and accuracy for using LU decomposition and TSVD. Numerical results show that the proposed golden section search method is effective and provides a reasonable shape parameter along with acceptable accuracy of the solution.

In this paper we apply the newly developed method of particular solutions (MPS) and one-stage method of fundamental solutions (MFS-MPS) for solving fourth-order partial differential equations. We also compare the numerical results of these two methods to the popular Kansa's method. Numerical results in the 2D and the 3D show that the MFS-MPS outperformed the MPS and Kansa's method. However, the MPS and Kansa's method are easier in terms of implementation.

This study presents the numerical and experimental demonstrations for the enhancement of light extraction efficiency in nitride-based light-emitting diodes (LEDs) with textured sidewall and micro-sized pillar waveguides (TSMPW) and nano-textured sidewall and nano-pillars (NTSNP) around the mesa. Using hydrothermal ZnO nanorods as the etching hard mask, the authors successfully formed vertical GaN nano-pillars on the mesa-etched regions. It was found that electrical characteristics observed from the proposed LEDs were near the same as the control samples without the pillars. Output power enhancement of LED with TSMPW was about 11% compared with conventional LEDs, and the output power enhancement of LED was greater than 45% upon replacement of TSMPW with the NTSNP structure. The light extraction efficiency enhancement factors of the LEDs with TSMPW and NTSNP structures simulated by finite-difference time-domain analysis were 16.6% and 23%, respectively.

In this study, the numerical and experimental demonstrations for the enhancement of light-extraction efficiency in nitride-based LEDs with randomly inverted pyramid sidewalls (IPSs) by chemical etching of the chip edge are presented. With 20 mA injection current, it was found that forward voltages were 3.69 and 3.75 V while output powers were 7.07 and 8.95 mW for the conventional LED and inverted pyramid sidewall LED, respectively. The larger LED output power is attributed to the increased light-extraction efficiency by IPSs.

In this study, an organoclay, ALA–MMT, was prepared by the ionic exchange reaction of montmorillonite (MMT) with 12-aminododecanoic acid (ALA). ALA–MMT was then used as a filler to prepare a series of composite polymer electrolytes based on polyacrylonitrile (PAN) and LiClO4. The effect of the addition of ALA–MMT on the properties of the composite polymer electrolytes (CPEs) was investigated by XRD, FT-IR, DSC, tensile strength, AC impedance, and cyclic voltammetry measurements. It was found that the ALA–MMT particles were well dispersed in the CPEs. Owing to the incorporation of ALA–MMT, a higher fraction of the free anions was obtained, indicating that the lithium salt dissolved in the PAN matrix more effectively for the CPE than in the PAN/LiClO4 polymer electrolyte. Moreover, the glass-transition temperature was reduced, benefiting the ion transport. The best ionic conductivity at room temperature was obtained from the CPE with 7 wt% of the modified clay and 0.6 M LiClO4 per PAN repeat unit (CPE-7) and was more than seven times higher than that from the corresponding PAN/LiClO4 polymer electrolyte (CPE-0). The mechanical property and the cation transference number, t+, of CPE-7 are largely increased compared to that of CPE-0. Besides, the CPEs were electrochemically stabilized up to 4.75 V and the corresponding cell exhibited excellent electrochemical stability and cyclability over the potential range between 0 V and 4.0 V vs. Li/Li+.

In this paper, early-stage hot-electron generation is shown to inject electrons into the shallow trench isolation (STI) edge above the drift region that causes the linear-region drain current to increase abruptly in the first moment of the stress for P-LDMOS transistors. After this early-stage carrier trapping, the transistor exhibits normal hot-carrier degradation during the following stress period. To further study this phenomenon, the geometry and the doping profile of the drift region near the STI edge and the polysilicon gate doping area are changed to investigate the initial IDLIN increase. Two-dimensional device simulator is used to analyze the experimental results. It is proven that the amount of current increase strongly depends on the distance from the maximum impact ionization generation rate point to the STI.

Three high-purity TiO2 (anatase) powders (TPF6, TBF4, and Tconventional) were prepared by the sol–gel method with/without ionic liquid as template and calcinations at 450 °C. These powders were, then, characterized to investigate their differences in morphological properties. Electrochemical performances of the H2/O2 PEMFCs employing the Nafion composite membranes with these three TiO2 powders as fillers were studied over 80–120 °C under 50% and 95% relative humidity (RH). The result showed that the order of the fillers effect on the performance at 80 and 90 °C was the same as that of the TiO2 filler's specific surface area (i.e. TPF6 > Tconventional > TBF4 > P25, a commercially available nonporous TiO2 powder). However, the order between Tconventional and TBF4 was reversed at 110 and 120 °C under 50% RH. This indicates that the size and the amount of mesopores, which better confined the water molecules, were significant contributing factors to the performances at the higher temperatures. The best power density obtained under 50% RH at 120 °C and a voltage of 0.4 V was from the PEMFC with the TPF6-containing Nafion composite membrane. It was about 5.7 times higher than the value obtained from that with the recast Nafion membrane.

In large-area field emission display applications where high stress point glass substrate is used for vacuum-sealed packaging and low cost considerations, the CNTs synthesis temperature lower than the stress point of ∼570 °C is required. In the thermal CVD processes, the catalyst passivation due to the slow carbon diffusion rate limiting and the consequent amorphous carbon formation on the catalyst surface was considered to be the main reason hampering carbon nanotube growth at low temperatures. The amount of amorphous carbon decreases apparently with the decrease of the process pressure for the low-temperature growth of CNTs. In this paper, we report a successful synthesis of vertically aligned-MWNTs on Ni/Cr coated glass (PD200) substrate at 550 and 500 °C by low pressure (8 Torr) thermal CVD with reasonably good field emission characteristics of approximate milliampere per square centimeter emission current density.

Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin capability of 450mV is achieved with variability reduction for the first time. Metal capacitance reduction by ∼9% is realized with advanced interconnect scheme to enable dynamic power saving.

The first publication on fabrication of a 300 mm size, 50 μm ultra-thin glass interposer is presented. According to measured data and modeling analysis, merits of on-glass inductors and transmission lines outperform those of on-silicon in Q-factor, power dissipation, and power/signal integrity. Glass interposer is a promising building block technology for future hybrid mixed signal heterogeneous chip integration solution.

For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technology provides 2X logic density and >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To our knowledge, this is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node. Low leakage (SVt) FinFET transistors achieve excellent short channel control with DIBL of

The electron emission characteristics of planar field emission arrays (FEAs), containing diamondlike carbon (DLC) films as emitters, were investigated. Precoating an Au layer on Si prior to the deposition of DLC films further improves the emission properties of FEAs. A high emission current capacity as 0.5 mA/cm2 has been achieved, which corresponds to a large emission current density as 44 mA/cm2 for DLC films in the emitting dots. However, preannealing the Au-coating at 500°C (30 min) is necessary to improve the characteristics of film-to-substrate interface and the DLC films' electron field emission properties.

Because of its compactness and high efficiency, the image furnace using ellipsoid mirrors to focus infrared heating from lamps has widely been used in floating-zone (FZ) crystal growth. However, little research has been reported on modeling energy distribution in such a system. In this paper, a simple model considering direct and indirect radiation from the lamps is presented. This model is consistent with the point-source model as the lamp size is diminished. The effects of lamp size, shape, orientation, and defocusing are discussed. The model is further integrated with a three-dimensional thermal-capillary model. Therefore, the temperature distribution and the zone shape of the sample during FZ growth in the furnace can be estimated. Temperature measurements of a graphite rod in a mirror furnace were also conducted to validate the global model.

We describe 19 unrelated individuals with submicroscopic deletions involving 10p15.3 characterized by chromosomal microarray (CMA). Interestingly, to our knowledge, only two individuals with isolated, submicroscopic 10p15.3 deletion have been reported to date; however, only limited clinical information is available for these probands and the deleted region has not been molecularly mapped. Comprehensive clinical history was obtained for 12 of the 19 individuals described in this study. Common features among these 12 individuals include: cognitive/behavioral/developmental differences (11/11), speech delay/language disorder (10/10), motor delay (10/10), craniofacial dysmorphism (9/12), hypotonia (7/11,), brain anomalies (4/6) and seizures (3/7). Parental studies were performed for nine of the 19 individuals; the 10p15.3 deletion was de novo in seven of the probands, not maternally inherited in one proband and inherited from an apparently affected mother in one proband. Molecular mapping of the 19 individuals reported in this study has identified two genes, ZMYND11 (OMIM# 608668) and DIP2C (OMIM# 611380) (UCSC Genome Browser), mapping within 10p15.3 which are most commonly deleted. Although no single gene has been identified which is deleted in all 19 individuals studied, the deleted region in all but one individual includes ZMYND11 and the deleted region in all but one other individual includes DIP2C. There is not a clearly identifiable phenotypic difference between these two individuals and the size of the deleted region does not generally predict clinical features. Little is currently known about these genes complicating a direct genotype/phenotype correlation at this time. These data however, suggest that ZMYND11 and/or DIP2C haploinsufficiency contributes to the clinical features associated with 10p15 deletions in probands described in this study.

Effects of mass transport, corrosion products and biofilm formation on corrosion kinetics of five copper alloys, four stainless steels and titanium grade 2 exposed to natural and artificial seawater were determined. Corrosion current density (icorr), anodic (ba) and cathodic (bc) Tafel slopes were determined from analysis of polarization curves recorded in the vicinity of the corrosion potential (Ecorr) under controlled mass transport conditions as a function of exposure time. Rotating cylinder electrode experiments demonstrated that Ecorr and corrosion rate for stainless steels and titanium were independent of mass transport. For copper alloys icorr depended linearly on rotation speed r0.7, while Ecorr was independent of mass transport. These results indicate that both cathodic and anodic reactions for stainless steels and titanium are under charge transfer control, whereas these reactions are under mass transport control for copper alloys. Corrosion rates of copper alloys were also obtained using linear polarization and weight loss. Corrosion rates obtained with the two methods agreed for exposures in artificial seawater. In natural seawater, corrosion rates determined with linear polarization underestimated corrosion rates from weight loss data by a factor of two or more. Environmental and traditional scanning electron microscopy coupled with energy-dispersive X-ray analyses were used to document surface topography, bacterial colonization and form of corrosion after removal of corrosion products. De-alloying of all copper alloys occurred in natural seawater. Intergranular corrosion was observed for 70Cu-30Ni alloy under elliptical deposits of embedded diatoms. De-alloying and intergranular corrosion did not occur in artificial seawater. Sulfides produced by bacteria may have accelerated attack of nickel in grain boundaries of 70Cu-30Ni alloy.