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A frequency-domain model is developed to analyze isolated interconnects of multilayer graphene-nanoribbon (MLGNR) and mixed carbon-nanotube bundle (MCB) driven by CMOS gates. The model derived is founded on an equivalent-single-conductor model of MLGNR and MCB that takes thermal considerations into account (i.e. TD-ESC). The model includes the derivation of transfer function of interconnect to estimate its delay and bandwidth performance. The attained results, reveals that among the neutral MLGNR (N-MLGNR), intercalation doped MLGNR (ID-MLGNR) intercalated with FeCl 3 , MCB and Cu interconnects, FeCl 3 ID-MLGNR achieves the best bandwidth efficiency. At a global interconnect length of 1 mm, FeCl 3 ID-MLGNR outperforms N-MLGNR, MCB, and Cu in terms of bandwidth with an improved bandwidth value of 12.2 GHz, 7 GHz, and 61.4 GHz, respectively. Further, employing the proposed CMOS-gate-driven model, for FeCl 3 ID-MLGNR, bandwidth is improved by nearly 7.52 × at global length (∼1 mm) in relation to the linear resistance model. Additionally, TD-ESC dependency of the proposed model reveals that FeCl 3 ID-MLGNR becomes more stable as interconnect resistance increases. • CMOS-driven interconnects of multilayer graphene-nanoribbon(MLGNR) and mixed CNT bundle(MCB) analysed in frequency-domain. • A temperature-dependent equivalent-single-conductor (TD-ESC) approach estimates interconnect performance accurately. • The derived transfer function for interconnects allows for the estimation of delay and bandwidth performance. • At global interconnect domain, FeCl3 intercalation-doped MLGNR (ID-MLGNR) outperforms neutral-MLGNR (N-MLGNR), MCB and Cu. [ABSTRACT FROM AUTHOR]

This paper presents an efficient wavelet based numerical method for analyzing functional and dynamic crosstalk of CMOS driven coupled copper (Cu) interconnects known as Multi-Resolution Time Domain (MRTD),wherein, the CMOS drivers are modeled using nth-power law model. The performance of the proposed MRTD method is evaluated through recursive simulations in HSPICE environment and compared with the conventional Finite Difference Time Domain (FDTD) method at 32-nm technology node for global interconnects of length 1mm, where the computations of the proposed model and conventional FDTD are carried out using MATLAB. For different number of test cases, the proposed MRTD method gives an average error of 0.14 % and 1.9 % for peak crosstalk noise and peak noise timing, respectively, with respect to HSPICE results. Also, the dynamic crosstalk noise on victim line of the proposed MRTD method are in close agreement with those of HSPICE. The results show the dominance of the proposed MRTD method over the conventional FDT method regarding accuracy. The proposed MRTD method is also extended for three-mutuallycoupled interconnect lines for crosstalk analysis, with an average error less than 1 % when compared to that of more than 3 % using the conventional FDTD method. Moreover, for the transient analysis, the MRTD method is more time efficient than HSPICE.

This paper explicates the design and implementation of a switch capacitor DC–DC converter system for Radio Frequency (RF) energy harvesting applications for an input voltage in the sub-150 mV range, using 180-nm CMOS triple-well BCD technology. The proposed system incorporates a charge pump architecture that employs an improvised Dynamic Gate Biasing (DGB), Forward and Reverse Body Bias technique (FRBB), along with a time axis symmetrical clocking scheme implemented using an advanced bootstrapped CMOS driver to enhance the overall drive capability of the system at low input voltages. Post-layout extracted simulations demonstrate that the proposed system achieves higher overall efficiency, delivering a peak Power Conversion Efficiency (PCE) of 85.8% at 125 mV input voltage, outperforming other state-of-the-art architectures in similar voltage ranges. Moreover, the proposed system exhibits reliable operation even at input voltages as low as 85 mV, while maintaining good overall efficiency. • Architecture with Dynamic Gate Biasing (DGB), Forward and Reverse Body Bias (FRBB) • Post-layout simulations show proposed system achieves 85.8% PCE at 125 mV input • Proposed system reliable operation with good overall efficiency at 85 mV input voltage [ABSTRACT FROM AUTHOR]

This paper proposes a body-biased bootstrapped CMOS driver for subthreshold applications. The proposed driver has been implemented with the same number of transistors as conventional bootstrapped CMOS driver. The performance of the subthreshold bootstrapped CMOS driver has been compared with the conventional bootstrapped CMOS driver. Our results show that the proposed body-biased subthreshold bootstrapped CMOS driver has 37% reduction in delay and 39% reduction in power dissipation compared to conventional bootstrapped CMOS driver. The proposed driver is more suitable to drive large loads compared to the conventional driver and operates better at subthreshold region. [ABSTRACT FROM AUTHOR]

We developed an aerosol-jet printing technique to realize an optical transmitter assembly of a microring modulator and a high-speed CMOS driver in which the bonding wires are replaced by aerosol-jet printed silver interconnects. First, the technology is characterized by printing coplanar waveguides (CPWs) test structures on glass and epoxy in order to fully investigate the electro-magnetic behavior of the aerosol-jet printed interconnects. The printed CPWs on glass and epoxy showed a low attenuation of 0.57 and 0.76 dB/mm at 50 GHz, respectively. Then, the aerosol-jet printed interconnects were benchmarked with conventional bonding wires while separately interconnecting the ring modulator without the CMOS driver. The measured reflection coefficient ($S_{11}$) of the aerosol-jet printed interconnects showed an increase in a resonance frequency of 20 GHz compared with Al bonding wires. Furthermore, the optical transmitter was successfully demonstrated at 60 Gb/s and the measured optical eye diagrams were clearly open even after 2 km of standard single-mode fiber. An extinction ratio of 4.63 dB was achieved while applying a drive voltage of 1 $\text{V}_{\mathrm{ pp}}$. [ABSTRACT FROM AUTHOR]

We demonstrate a flexible face-up 2.5 D packaging technique for a hybrid electro-photonic integration. The process is based on an aerosol-jet technology to print the high-speed electrical interconnects between electronic and photonic chips as a potential alternative for the traditional bonding wires. The technology is realized by creating a transparent mechanical polymer support to bridge the gap between the photonic and electronic chips and subsequently printing the electrical interconnects on top. First, the daisy-chain test chips were used to prove the functionality of the technology by printing the electrical interconnects between the test chips. Then, a standard 85 ° C/85 RH test was performed to investigate the reliability of the printed interconnects and no failure or degradation was observed over 700 h. Afterwards, the technology was successfully applied on functional chips. An optical transmitter based on vertical cavity surface emitting lasers (VCSELs) was demonstrated at 50 Gb/s by printing 200-μm-long high-speed silver interconnects between a 4-channel SiGe BiCMOS driver and four VCSELs. In addition, the technology showed the potential to interconnect silicon photonics chips. An assembly of an electro-absorption modulator (EAM) and a CMOS driver was successfully demonstrated. Clear open eye diagrams were obtained at 40, 50, and 56 Gb/s for the EAM-driver assembly even after 2 km of a standard single-mode fiber. [ABSTRACT FROM AUTHOR]

This paper presents an efficient wavelet based numerical method for analyzing functional and dynamic crosstalk of CMOS driven coupled copper (Cu) interconnects known as Multi-Resolution Time Domain (MRTD), wherein, the CMOS drivers are modeled using nth-power law model. The performance of the proposed MRTD method is evaluated through recursive simulations in HSPICE environment and compared with the conventional Finite Difference Time Domain (FDTD) method at 32-nm technology node for global interconnects of length 1mm, where the computations of the proposed model and conventional FDTD are carried out using MATLAB. For different number of test cases, the proposed MRTD method gives an average error of 0.14% and 1.9 % for peak crosstalk noise and peak noise timing, respectively, with respect to HSPICE results. Also, the dynamic crosstalk noise on victim line of the proposed MRTD method are in close agreement with those of HSPICE. The results show the dominance of the proposed MRTD method over the conventional FDTD method regarding accuracy. The proposed MRTD method is also extended for three-mutuallycoupled interconnect lines for crosstalk analysis, with an average error less than 1 % when compared to that of more than 3 % using the conventional FDTD method. Moreover, for the transient analysis, the MRTD method is more time efficient than HSPICE. [ABSTRACT FROM AUTHOR]

A highly power-efficient silicon (Si) photonic PAM4 transmitter was developed by integrating a Si segmented Mach- Zehnder modulator and a CMOS driver chip. Si p-i-n-type phase shifters are directly driven with a CMOS inverter driver array to realize a low power operation. A passive RC equalizing technique was adopted to extend the modulation bandwidth up to 20 GHz while maintaining a low power consumption. By integrating a passive RC filter within the photonics chip, we achieved a very compact foot print for the transmitter (450 x 950 µm). The fabricated modulator exhibited a low VπL of 0.19 V⋅cm and a moderate insertion loss of 23.7 dB/cm. The transmitter successfully demonstrated clear eye openings of PAM4 signal up to 56 Gbps together with a record-high-efficiency of 1.59 mW/Gbps. A low bit-error- rate below KP4 FEC limit (< 2.0 x 10-4) was also confirmed at 50-Gbps PAM4 operation even with an unequalized receiver. [ABSTRACT FROM AUTHOR]

This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire.

The authors used 65‐nm CMOS technology to develop a linear four‐channel driver IC with low temperature dependence and ultra‐low power dissipation for 64‐Gbaud coherent optical transmitters. The driver showed more than a 48‐GHz 3‐dB electrical bandwidth and less than 1‐W power consumption in four‐channel operation. By employing a circuit that suppresses the temperature dependence, they achieved 3‐dB electrical bandwidth variation of 3.0 GHz and the gain variation of 1.5 dB under the −5 to 75°C and ±5% supply voltage variation conditions. The CMOS driver has all the necessary functions for a high‐bandwidth coherent driver modulator such as a gain control, peaking control, peak detection and temperature monitoring, all of which functions can be controlled by a serial peripheral interface. A fabricated sub‐assembly consisting of the CMOS driver and an InP modulator showed a 48‐GHz 3‐dB electro‐optic bandwidth. [ABSTRACT FROM AUTHOR]

An integrated 0.35- \mu \textm HV-CMOS driver has been designed for a gain-switched quantum well laser diode to generate short, energetic (100 ps/ $\sim 0.5$ nJ) optical pulses for a pulsed time-of-flight (TOF) laser radar, operating on the single-photon detection principle. The driver can produce a current pulse with a peak amplitude of $\sim 2$ A, a pulsewidth of 1 ns, and a pulsing rate of 500 kHz. The peak optical power and pulsewidth of the transmitter output with these parameters are 3 W and 100 ps, respectively. A single-shot precision of 2–3 cm is achieved in the TOF measurements of a non-cooperative target at 25 m with a reflectivity of 8% and a receiver aperture of 18 mm using a CMOS SPAD as the receiver. [ABSTRACT FROM PUBLISHER]

In the modern era of nano-electronics, the performance of Cu interconnects degrades with the technology node advancement, thus the hybrid copper carbon nanotubes (Cu-CNTs) have motivated researchers to use them as copper substitutes. Especially, the Cu-CNT line presents a better immunity to the crosstalk in comparison to Cu and CNT interconnects. In this way, an accurate FDTD based method has been developed and validated by the PSPICE results for the crosstalk effect analysis of coupled Cu-CNT interconnect lines at 22 nm and 14 nm technology nodes. The results achieved in this work employing the proposed method have shown better performance compared with the conventional FDTD and more accurate results compared with PSPICE. The simplicity, and accuracy of using the proposed model ensure several applications in the VLSI design tools. [ABSTRACT FROM AUTHOR]

This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%-50% and a falling-delay improvement of 25%-47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%-43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire. [ABSTRACT FROM AUTHOR]

This paper presents design options and transistor-level solutions for implementing, in CMOS processes without triple-well, drivers suitable for MEMS body biasing. The output voltage of the driver envisaged here can be set to positive or negative levels, programmable between (+10 ​V to +20 ​V), respectively (−20 ​V to −10 ​V), with a resolution of 100 ​mV. Also, the driver can ground its output terminal, as well as leave it open/floating, all under digital control. The key parts of such a driver are the voltage generators that provide positive and negative voltages several times larger than the supply voltage and the output stage that delivers the voltage required to bias the MEMS body terminal, V MEMS. Three solutions, which consist of driver topology and circuit implementation of key elements, are proposed and analyzed comparatively. The first solution requires the development of one ASIC that comprises a 9-bit DAC, as well as drivers for the digitally-programmable voltage generators – a boost DC-DC converter and an inverting (negative output voltage) charge pump – which provide directly the wanted positive or negative V MEMS voltage levels, while the output stage is a voltage multiplexer implemented with high-voltage external transistors. The second solution requires two ICs that operate at different substrate voltage levels: an ASIC comprising the same DAC but simpler drivers for more compact, but less accurate, voltage generators. This time, the large positive and negative voltages are only used to supply the output stage of the system. Two options are presented for the later: an off-the-shelf IC and an ASIC that implements a single-OpAmp differential amplifier with positive/negative gain set digitally. The third solution is a more versatile version of the same approach, whereby the first ASIC implements only the positive and negative voltage generators that supply the second ASIC, which comprises a 7-bit DAC and a digitally configurable amplifier. One instance of the first ASIC can supply multiple instances of the second ASIC that operate in parallel, under common or individual control. Proof-of-concept implementations of the proposed ASICs were designed in a high-voltage 0.18 ​ ​μm CMOS process without triple well; schematics of key blocks are presented in the paper. Simulation results validate the design, demonstrating that it is indeed possible to implement in standard CMOS all the circuit functions mentioned above, while reducing the number of external components to a minimum. [ABSTRACT FROM AUTHOR]