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105 results on '"Cai, Xiaowu"'

22. A Radiation-Hardened Overtemperature Protection Circuit Using a Dynamic Comparison Technique

Author

Dang, Jianying, Cai, Xiaowu, Xie, Yafei, Wang, Xupeng, Lu, Yu, Wang, Shiping, and Li, Bo

Abstract

The total-ionizing-dose (TID) effect has different influences on bipolar junction transistors (BJTs), resistors, and MOSFETs, which leads to significant drifts in the overtemperature threshold in the traditional overtemperature protection circuit (OTPC). An OTPC with a dynamic comparison technique is proposed to improve the radiation-hardened capability. The proposed radiation-hardened OTPC employs two identical sensors to monitor the temperature and convert it into voltage for comparison to determine if overtemperature occurs. The voltage drifts caused by TID effects on two sensors vary dynamically and offset each other, so the overtemperature threshold will not drift theoretically. The normalization method is used to process measurement results to get a visual comparison. The measurement results show that the threshold drift of the proposed OTPC is 5.0% lower than that of traditional OTPC at 30 krad(Si), 7.1% lower at 50 krad(Si), and 10.3% lower at 100 krad(Si). Therefore, the proposed OTPC reduces the threshold voltage drifts effectively and has a good radiation-hardened effect.

Published
2024
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34. Evolution and Mechanism of P-GaN Films Under Proton Irradiation and Its Influence on Electronic Device.

Author

Tang, Yun, Wang, Lei, Zhu, Huiping, Cai, Xiaowu, Zhang, Xuewen, Gao, Jiantou, Liu, Ningyang, Li, Xingji, Yang, Jianqun, Zhao, Fazhan, and Li, Bo

Subjects
ELECTRONIC equipment, SCHOTTKY barrier diodes, PIN diodes, CHARGE carrier mobility, CARRIER density, PROTONS, IRRADIATION
Abstract

Electrical and optical properties deterioration of P-GaN films under 150 keV proton irradiation were investigated. Through the Hall measurement method, as the irradiation fluence increasing, the carrier concentration of P-GaN films decreases from 1.23 $\times \,\,10^{{17}}$ to $-8.24\,\,\times \,\,10^{{16}}$ cm−3, and the carrier mobility change from 5.64 to 295.84 cm2/V/s. And through the circular transmission line model method, the sheet resistance and specific contact resistance for P-GaN films increased first and then decreased slightly under the proton irradiation. Radiation-induced $\text{V}_{\mathrm {N}}$ , $\text{Ga}_{\mathrm {i}}$ , $\text{V}_{\mathrm {Ga}}$ , and $\text{N}_{\mathrm {i}}$ were found to be responsible for the degradation of P-GaN films. It was confirmed that P-GaN has been transformed into N-GaN under the fluence of 1 $\times \,\,10^{15}$ p/cm2. The optical properties of the P-GaN films were characterized by examining changes in the photoluminescence spectrum. In addition, the electrical characteristics of Schottky barrier diode (SBD) and p-i-n diodes with the same structure (except for 0.5 $\mu \text{m}$ P-GaN of p-i-n diode) were used to study the effect of P-GaN degradation on electronic device performance. When P-GaN was transformed into N-GaN, p-i-n diodes lost the electrical characteristics of the p-n junction and the ${I}$ – ${V}$ curves of p-i-n diode are similar to that with SBD. [ABSTRACT FROM AUTHOR]

Published
2022
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36. A low leakage current Tunneling-FET based on SOI

Author

Li Duoli, Jiajun Luo, Jianhui Bu, Cai Xiaowu, Gaobo Xu, Zhengsheng Han, and Yong Kuang

Subjects
010302 applied physics, Materials science, business.industry, Doping, Silicon on insulator, Low leakage, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Ion, Logic gate, 0103 physical sciences, MOSFET, Optoelectronics, Current (fluid), 0210 nano-technology, business, Quantum tunnelling
Abstract

In this paper, we present a new structure of Tunneling-FET(TFET) based on SOI to reduce the leakage current. A thin oxide is inserted in the interface of Drain and Bulk near the gate-oxide side. The thin oxide eliminated the tunneling current between Drain and Bulk completely. This new TFET shows a superior performance with lower leakage current (1.1e-14 A/um) and larger ION/IOFF ratio $( 3 \times 10^{8})$.

Published
2018

42. Analysis of the area efficient transmission gate power clamp in 65nm CMOS process

Author

Gao Zhe, Liang Chao, Lv Chuan, Yan Ming, Lv Kai, Cai Xiaowu, and Wei Jun-xiu

Subjects
010302 applied physics, Engineering, Hardware_MEMORYSTRUCTURES, business.industry, Electrical engineering, Time constant, 020206 networking & telecommunications, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, law.invention, Capacitor, Clamp, CMOS, Transmission gate, law, Logic gate, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Timer, business, Hardware_LOGICDESIGN, Leakage (electronics)
Abstract

an area efficient clamp is presented and validated in 65nm low leakage CMOS process. With this novel design, only a very short time constant RC timer is required for triggering and keeping the clamp turning on for shunting the ESD current. And the leakage is greatly reduced in normal operation because of the small capacitor. Robust ESD protection capability and no risk of power on mis-triggering problems are also studied in the paper.

Published
2016

44. Investigation of high voltage SCR-LDMOS ESD device for 150V SOI BCD process

Author

Lv Chuan, Liang Chao, Cai Xiaowu, Zhe Gao, and Wei Junxiu

Subjects
LDMOS, Materials science, business.industry, Process (computing), Electrical engineering, Silicon on insulator, High voltage, Condensed Matter Physics, Chip, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Power (physics), Holding current, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, business, Voltage
Abstract

In this paper, two types of ESD devices, LDMOS and SCR-LDMOS (SCR embedded in LDMOS), are investigated for 150 V HV SOI BCD process. The results show that the SCR-LDMOS structures have better ESD protection capability than LDMOS. The SCR-LDMOS structure is achieved by inserting P+ diffusion in the drain of LDMOS structure with different N+/P+ ratios. Impact of different N+/P+ ratios’ on Ron (on-resistance), holding voltage and holding current is studied. Considering the tradeoff between holding current and Ron, one optimized SCR-LDMOS structure is presented and adopted for the full chip high voltage power clamp, which indicates 3500 V (HBM) ESD withstand voltage without latch up risk.

Published
2013

45. Stabilization criterion of fractional-order PDμcontrollers for interval fractional-order plants with one fractional-order term

Author

Liu Ting, Lirong Zhai, Cai Xiaowu, and Gao Zhe

Subjects
Characteristic function (convex analysis), 0209 industrial biotechnology, 020208 electrical & electronic engineering, Zero (complex analysis), 02 engineering and technology, Function (mathematics), Interval (mathematics), Minkowski addition, Vertex (geometry), Term (time), 020901 industrial engineering & automation, Control theory, 0202 electrical engineering, electronic engineering, information engineering, Order (group theory), Mathematics
Abstract

This study proposes a stabilization criterion of fractional-order PDμ controllers for interval fractional-order plants with one fractional-order term. By the Minkowski sum method, the value set of the disturbance function is determined by dividing the characteristic function of the closed loop system into the nominal function and disturbance function. The calculation approach of vertices and edges of the value set in term of a characteristic function are provided to avoid the calculation of redundant vertices. The switching frequencies are offered to determined the shape of value set with the increase of the frequency. Moreover, the finite test frequency interval is offered. By supposing that the vertex functions are not equal to zero and the closed loop nominal system is stable, the sufficient and necessary condition of stabilization criterion of fractional-order PDμ controllers are given. Finally, the stabilization problems of the numerical examples are analyzed to verify the effectiveness of the proposed stabilization criterion.

Published
2016

48. Enhancing the High-Temperature and High-Rate Properties of Nickel Hydroxide Electrode for Nickel-Based Secondary Batteries by Using Nanoscale Ca(OH)2 and ?-CoOOH

Author

Li, Jing, Zhang, Huijie, Wu, Chengke, Cai, Xiaowu, Wang, Mingyu, Li, Quanmin, Chang, Zhaorong, and Shangguan, Enbo

Abstract

Nanoscale Ca(OH)2 particles as a novel cathode additive for nickel-based secondary batteries are synthesized by a homogeneous precipitation method. The influence of Ca(OH)2 additive on the electrochemical performance of two types of nickel electrode (using spherical Ni(OH)2 and g-CoOOH@Ni(OH)2) were evaluated. It is interestingly discovered that nano-Ca(OH)2 additives can efficiently improve the charge acceptance of both nickel electrodes. Especially, the charge acceptance of the 1.0 wt% nano-Ca(OH)2@g-CoOOH@Ni(OH)2 electrode at 70degC at 5C is over 90% and the discharge capacity can reach about 218 mAh g[?]1. These performance enhancements of nickel electrode mainly result from the combined coating with Ca(OH)2 and g-CoOOH. The modification of oxygen evolution reaction on the nickel electrode is primarily resulting from the use of Ca(OH)2 by increasing its potential and suppressing its rate. The observably lower charge transfer resistance of nickel electrode is mainly due to the high conductivity coating of g-CoOOH. Consequently, the proposed cathode additive is promising for the high-temperature property enhancement of nickel-based rechargeable batteries.

Published
2019

49. Investigation of ESD second breakdown TCAD simulation

Author

Han Xiaoyong, Cai Xiaowu, and Yan Beiping

Subjects
Engineering, Electrostatic discharge, business.industry, Load modeling, Computation, Hardware_PERFORMANCEANDRELIABILITY, Breakdown point, law.invention, Snapback, CMOS, law, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Resistor, business, Hardware_LOGICDESIGN
Abstract

This paper presents the methodology to obtain the snapback curves and second breakdown point of an ESD stressed device through TCAD simulation. This method allows an excellent ESD simulation convergence and then good ESD prediction with a significantly reduced computation time. One 0.5um CMOS technology has been simulated for experimental support.

Published
2010

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