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The oxidation characteristics of TiAlN films integrated in the bottom electrode (BE) stack of three-dimensional SrBi2Ta2O9-based (SBT) ferroelectric capacitors are investigated in the range of 650–800 °C. The patterned TiAlN\Ir\IrO2\Pt BE is encapsulated by a thin ferroelectric SBT film deposited by metal organic chemical vapor deposition and then crystallized ex situ at temperatures higher than 650 °C in oxygen. During this annealing step the TiAlN film oxidizes from the lateral side of the patterned BE mesas. Compared to the vertical oxidation in blanket TiAlN layers, the lateral oxidation rate in our capped patterned films is much larger for similar oxidation conditions. This lateral oxidation of the TiAlN is strongly correlated with the in-film SBT stress that depends upon the deposition temperature and the thickness of the SBT film: the higher the tensile stress in the SBT, the larger the TiAlN oxidation length induced. From a kinetic study, the lateral oxygen diffusion was found to be a self-limited process with activation energy of about 2.2 eV and a preexponential factor D0 of 7×10-3 cm2/s. This factor, one to two orders of magnitude higher than the one obtained in blanket TiAlN layers, is indicative of interfacial diffusion. The mechanism of the increased lateral oxidation can be understood by the high tensile stress of the SBT film at the sidewall of the ferroelectric capacitors that tends to tear apart the Ir/TiAlN interface and causes enlarged interfacial oxygen diffusion. The limiting step of the oxidation mechanism is identified as oxygen diffusion in the Al-depleted/Ti-rich TiAlN layer that lies beyond the Al-rich film found at the very edge of the capacitors, whereas on blanket films the oxygen diffusion is limited in the Al-rich surface layer region. [ABSTRACT FROM AUTHOR]

Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35 μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18 μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures. [ABSTRACT FROM AUTHOR]

Different aspects of the integration of strontium bismuth tantalate (SBT)-based high-density ferroelectric random access memory (FeRAM) is discussed in relation to the fabrication of pseudo-three-dimensional (3D) cell structure. The excellent electrical and reliability properties of the small integrated FeCAP prove the feasibility of the technology, while the verification of the potential electrical 3D effect confirms the basic scaling potential of the concept beyond that of the single-mask capacitor.

A simplified TiAlN\Ir bottom electrode (BE) has been applied for the integration of stacked SrBi 2 Ta 2 O 9 (SBT) ferroelectric capacitors on W-plugs. In order that the W-plugs are less exposed to oxygen during the high thermal budget used for the SBT crystallization (700°C/1 h), the implementation of low O 2 partial pressures was investigated. The optimization of the annealing conditions (O 2 flow) was attained by using planar TiAlN\Ir\ SBT FeCAP's. It was found that the optimal O 2 content was ∼⃒20 ppm (∼⃒10 -3 Torr), attaining polarization values (P r ) as high as 7 μ C/cm 2 . Higher O 2 partial pressures leads to SBT with inferior ferroelectric characteristics (Pr ∼⃒ 3 μ C/cm 2 in full O 2 atmosphere), which correlated well with the formation of IrO 2 at the Ir-SBT interface. If patterned TiAlN\ Ir BE structures are used and SBT is crystallized at the optimal O 2 partial pressure, the system is no longer stable due to extended lateral oxidation of the TiAlN film, buckling of the Ir film and subsequent W-plug oxidation. These results will be explained taking into consideration the combination of high tensile stress in the SBT and the Ir films when annealed in atmospheres close to pure N 2 . [ABSTRACT FROM AUTHOR]

This paper reports on the integration of MOCVD SBT based stacked ferroelectric capacitors in a 0.35 μm CMOS technology for embedded FeRAM, using a ferroelectric capacitor (FeCap) that is scalable to a 3D configuration. The electrical parameters of the CMOS devices with and without FeCap integration are presented. No significant shifts of the CMOS characteristics are noticed after FeCap integration. Also the effects of the CMOS processing on the FeCaps are discussed. There is no degradation of the hysteresis loops of the FeCaps throughout the CMOS back-end-of-line processing, which proves that the integrated encapsulation layer effectively prevents any hydrogen induced damage. Another key element in the successful integration of stacked ferroelectric devices is the conductive oxygen barrier, which protects the plugs from oxidation. A low contact resistance and a high yield are obtained on plug contacts covered by the oxygen barrier. Also damage free etching is a critical issue in FeRAM integration. Excellent results are presented for the etch process to form the contacts to the electrodes. [ABSTRACT FROM AUTHOR]