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36 results on '"Chaver, Daniel"'

1. Reuse Detector: Improving the Management of STT-RAM SLLCs

Author

RodrÍguez-RodrÍguez, Roberto, DÍaz, Javier, Castro, Fernando, IbÁÑez, Pablo, Chaver, Daniel, ViÑals, Víctor, Saez, Juan Carlos, Prieto-Matias, Manuel, Pinuel, Luis, Monreal, Teresa, and LlaberÍa, Jose María

Subjects
Computer Science - Hardware Architecture
Abstract

Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime contender due to its better energy efficiency, smaller die footprint and higher scalability. However, STT-RAM also exhibits some drawbacks, like slow and energy-hungry write operations, that need to be mitigated. In this work we address these shortcomings by leveraging a new management mechanism for STT-RAM SLLCs. This approach is based on the previous observation that the stream of references arriving at the SLLC of a Chip MultiProcessor (CMP) exhibits reuse locality, i.e., those blocks referenced several times manifest high probability of forthcoming reuse. In this paper, we employ a cache management mechanism that selects the contents of the SLLC aimed to exploit reuse locality instead of temporal locality. Specifically, our proposal consists in the inclusion of a Reuse Detector between private cache levels and the STT-RAM SLLC to detect blocks that do not exhibit reuse, in order to avoid their insertion in the SLLC, hence reducing the number of write operations and the energy consumption in the STT-RAM. Our evaluation reveals that our scheme reports on average, energy reductions in the SLLC in the range of 37-30\%, additional energy savings in the main memory in the range of 6-8\% and performance improvements of 3\% up to 14\% (16-core) compared to an STT-RAM SLLC baseline where no reuse detector is employed. More importantly, our approach outperforms DASCA, the state-of-the-art STT-RAM SLLC management, reporting SLLC energy savings in the range of 4-11\% higher than those of DASCA, delivering higher performance in the range of 1.5-14\%, and additional improvements in DRAM energy consumption in the range of 2-9\% higher than DASCA.

Published
2024
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3. An OS-Oriented Performance Monitoring Tool for Multicore Systems

Author

Saez, Juan Carlos, Casas, Jorge, Serrano, Abel, Rodríguez-Rodríguez, Roberto, Castro, Fernando, Chaver, Daniel, Prieto-Matias, Manuel, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Hunold, Sascha, editor, Costan, Alexandru, editor, Giménez, Domingo, editor, Iosup, Alexandru, editor, Ricci, Laura, editor, Gómez Requena, María Engracia, editor, Scarano, Vittorio, editor, Varbanescu, Ana Lucia, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, Weidendorfer, Josef, editor, and Alexander, Michael, editor

Published
2015
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4. Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems

Author

Saez, Juan Carlos, Pousa, Adrian, Castro, Fernando, Chaver, Daniel, Prieto-Matías, Manuel, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Lopes, Luís, editor, Žilinskas, Julius, editor, Costan, Alexandru, editor, Cascella, Roberto G., editor, Kecskemeti, Gabor, editor, Jeannot, Emmanuel, editor, Cannataro, Mario, editor, Ricci, Laura, editor, Benkner, Siegfried, editor, Petit, Salvador, editor, Scarano, Vittorio, editor, Gracia, José, editor, Hunold, Sascha, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, Lengauer, Christian, editor, Carretero, Jesús, editor, Breitbart, Jens, editor, and Alexander, Michael, editor

Published
2014
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5. A Power-Efficient and Scalable Load-Store Queue Design

Author

Castro, Fernando, Chaver, Daniel, Pinuel, Luis, Prieto, Manuel, Huang, Michael C., Tirado, Francisco, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Paliouras, Vassilis, editor, Vounckx, Johan, editor, and Verkest, Diederik, editor

Published
2005
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10. Replacing associative load queues: a timing-centric approach

Author

Castro, Fernando, Noor, Regana, Garg, Alok, Chaver, Daniel, Huang, Michael C., Pinuel, Luis, Prieto, Manuel, and Tirado, Francisco

Subjects
Microprocessor, Microprocessor upgrade, Load balancing, Performance improvement, Central processing units -- Design and construction, Microprocessors -- Design and construction, Load balancing (Computers) -- Analysis
Published
2009

14. Practical experiences based on MIPSfpga

Author

Chaver, Daniel, primary, Panchul, Yuri, additional, Sedano, Enrique, additional, Harris, David M., additional, Owen, Robert, additional, Kakakhel, Zubair L., additional, Ableidinger, Bruce, additional, and Harris, Sarah L., additional

Published
2017
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17. ACFS

Author

Saez, Juan Carlos, primary, Pousa, Adrian, additional, Castro, Fernando, additional, Chaver, Daniel, additional, and Prieto-Matias, Manuel, additional

Published
2015
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18. Reducing the LSQ and L1 Data Cache Power Consuption

Author

Apolloni, Rubén, Carazo Minguela, Pablo, Castro, Fernando, Chaver, Daniel, Pinuel, Luis, and Tirado, Francisco

Subjects
Informática
Abstract

In most modern processor designs, the HW dedicated to store data and instructions (memory hierarchy) has become a major consumer of power. In order to reduce this power consumption, we propose in this paper two techniques, one to filter accesses to the LSQ (Load-Store Queue) based on both timing and address information, and the other to filter accesses to the first level data cache based on a forwarding predictor. Our simulation results show that the power consumption decreases in 30-40% in each structure, with a negligible performance penalty of less than 0.1%.

Published
2010

19. Reducción de consumo en la caché de datos de nivel 1 utilizando un predictor de forwarding

Author

Carazo Minguela, Pablo, Apolloni, Rubén, Chaver, Daniel, Castro, Fernando, Pinuel, Luis, and Tirado, Francisco

Subjects
Informática
Abstract

En la mayoría de los diseños de los procesadores actuales, el acceso a la caché de datos de nivel 1 (L1D) se ha convertido en uno de los componentes de mayor consumo debido a su incremento de tamaño y elevadas frecuencias de acceso. Para reducir este consumo, proponemos una sencilla técnica de filtrado. Nuestra idea se basa en un predictor de forwarding de alta precisión que determina si una instrucción de load tomará su dato vía forwarding a través de la LSQ –evitando en este caso el acceso a la L1D- o si debe ir a por él a la caché de datos. Nuestros resultados de simulación muestran que podemos ahorrar de media un 35% del consumo de la L1D, con una degradación despreciable de rendimiento

Published
2010

24. OpenIRS-UCM

Author

Garcia Sanchez, Carlos, primary, Castro, Fernando, additional, Gomez, Jose Ignacio, additional, Tenllado, Christian, additional, Chaver, Daniel, additional, and Lopez-Orozco, Jose Antonio, additional

Published
2012
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30. Energy-aware fetch mechanism

Author

Chaver, Daniel, primary, Rojas, Miguel A., additional, Pinuel, Luis, additional, Prieto, Manuel, additional, Tirado, Francisco, additional, and Huang, Michael C., additional

Published
2005
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31. Branch prediction on demand

Author

Chaver, Daniel, primary, Piñuel, Luis, additional, Prieto, Manuel, additional, Tirado, Francisco, additional, and Huang, Michael C., additional

Published
2003
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32. DMDC.

Author

Castro, Fernando, Pinuel, Luis, Chaver, Daniel, Prieto, Manuel, Huang, Michael, and Tirado, Francisco

Published
2006
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34. A Power-Efficient and Scalable Load-Store Queue Design.

Author

Paliouras, Vassilis, Vounckx, Johan, Verkest, Diederik, Castro, Fernando, Chaver, Daniel, Pinuel, Luis, Prieto, Manuel, Huang, Michael C., and Tirado, Francisco

Abstract

The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%. [ABSTRACT FROM AUTHOR]

Published
2005
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