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In this paper, the proposed multi-phase (MP) bidirectional dual Gallium-Nitride (GaN) controlled rectifier (GCR) uses dual GCR with the pre-charge technique to reduce third quadrant operation by minimizing dead time to 0.12ns and 0.13ns, and lowering the negative VDS to −0.6V and −0.8V in buck and boost operation, respectively. This work is the first research for monolithic bidirectional energy transfer with a two-switch-only topology. With the help of MP-accelerated current control and the GCR dynamic ramp generator, the voltage variation on the high-voltage (HV) side and low-voltage (LV) side can be reduced to less than 50mV and to 40mV, respectively, during buck and boost operation transitions. Moreover, the recovery time is effectively reduced and current balance between the four phases can be achieved within 7 cycles (=350ns). The peak efficiency is as high as 95.5% and 94.2% in buck and boost operation, respectively.

The single-mode avalanche energy ( ${E}_{\text {as}}\text {)}$ evaluated from the unclamped inductive-switching (UIS) test has been used in many application notes and literature as the ruggedness index of a transistor. The inductance is the key parameter for ${E}_{\text {as}}$ calculation. From the in-circuit measurement, the inductance at the channel turn-off time ( ${t}_{\text {off}}\text {)}$ is found smaller than the default inductance for the power transistor under the UIS test. However, most UIS testers still use the default inductance to calculate ${E}_{\text {as}}$ . In this article, whether the inductance can keep constant during ${t}_{\text {off}}$ for any transistor under any test condition of UIS and why it is smaller than the default inductance during ${t}_{\text {off}}$ for air core inductors is investigated. Without the ferrite core, the magnetization (M) of the air core inductor during the UIS test is caused by the eddy currents, which increase with increasing current and decrease with decreasing current linearly. Therefore, the differential magnetization (dM/dH) is constant, resulting in two different inductances during channel turn-on time ( ${t}_{\text {on}}\text {)}$ and turn-off time ${t}_{\text {off}}$ .

The proposed LLC flyback converter converts the 1200 V of the electric vehicle supply equipment (EVSE) into a 48 V battery system. The triple step-down converter with one inductor (TSDC-OL) technique converts 1200–400 V, and the transformer steps it down to 48 V. The zero-voltage switching (ZVS) mechanism is used for each switching operation and the equivalent on-resistance $R_{\text {ON}}$ is reduced to 1/4.5 times that of the existing technology. The proposed reference voltage compensator (RVC) can accurately maintain the charging current at 25 A. Since the left half-plane zero error amplifier (LZEA) contributes to the LHP zero, it ensures the stability of the RVC and prevents periodic variations. When the battery charges to 48 V, the operation switches to constant voltage (CV) mode via burst operation control (BOC) comparison with a leakage-based ultralow $I_{Q}$ comparator (LUC) with 2 nA $I_{Q}$ leakage. Finally, the proposed LLC flyback converter meets EVSE level 1 requirements in constant current (CC) mode and achieves 98.7% efficiency.

Although power supply stressed with respect to another supply is one test items of the electrostatic-discharge (ESD) qualification. However, a current path still exists that has not been reported earlier. From the failure analysis result, the damage is located at the high-voltage N-Well (HVNW) guard-ring of the zapped power domain. Based on the TCAD simulation, the failure mechanism is identified, and shows good agreement with silicon. It proves that the ESD current can only flow through the internal circuit of the zapped power domain and P+ guard-ring (VSS) to become a quiescent current before the power clamp device turns on. So, the internal circuit of the zapped power domain and P+ guard-ring become a substrate triggering circuit to turn on the parasitic npn bipolar between two different power domains, resulting in most ESD current flowing through HVNW guard-rings to induce the damage.

This paper proposes a two-phase hybrid buck-boost converter, which meets the criteria of USB PD 3.1, with an auxiliary inductor LAUX to achieve soft switching by the zero voltage switching (ZVS) technique at light loads. Besides, two interleaving phases can reduce the inductor current to half of that conventional design. Benefiting from a coupled inductor with a negative mutual inductance (M<0), the equivalent I $_{\mathrm {L(AC)}}$ becomes small to achieve low output voltage ripple due to large equivalent inductance Leq in a steady state. Based on the loading current, the phase shedding can change the number of driving phases for high efficiency. Moreover, a transient enhancement circuit is proposed to speed up transient response time. The proposed circuit achieves the maximum inductor current ripple reduction of 9.09% and the maximum P $_{\mathrm {AC\_loss}}$ reduction of 17.36% at D=0.5. Experimental results show 96.1% peak efficiency. In the case of the load step 0.5A to 5A, the recovery time and undershoot are reduced to $10.7\mu $ s and 133mV, respectively, and in the case of the load step 5A to 0.5A, the recovery time and overshoot are reduced to $9.4\mu $ s and 147mV, respectively.

This article proposes a gallium nitride (GaN)-based isolated silicon carbide (SiC) MOSFET gate driver with an on-chip metal–insulator–metal (MIM) capacitor that has high data rate and low propagation delay. The improved common-mode transient immunity (CMTI) envelope detection technique eliminates the common-mode current ( $I_{\mathrm {CM}}$ ) to improve the CMTI. In addition, the proposed isolated gate driver (IGD) with quad-drive control (QDC) technique reduces power loss and gate ringing effect. Experimental results show that the proposed IGD can achieve a slew rate of 109 kV/ $\mu \text{s}$ . At a switching frequency of 100 kHz, the efficiency of the half-bridge isolated dc–dc converter can be kept higher than 90% when $V_{\mathrm {IN}}$ changes from 800 to 1700 V, and the peak efficiency is 98.6% when $V_{\mathrm {IN}}$ = 800 V.

The discontinuous energy transfer characteristics of traditional single-inductor dual-output converters can lead to large output voltage ripple and cross-regulation. Thus, this article presents a double step-down dual-output converter implemented in a 0.15 μm bipolar-CMOS-DMOS (BCD) process, adopting hybrid sum and deviation control to achieve a small output voltage ripple of 25 mV and minimize cross-regulation to 0.025 mV/mA. The timing balance mechanism generates the replicated on-time and calibrates by sensing inductor current mismatch, which improves current balance by 90%. The proposed pulse-based highly robust high-speed low stress level shifter enhances transition speed during load transients while reducing the voltage stress on low voltage device.

From the Joules–Atherton (J-A) model, the sign of magnetization energy loss due to hysteresis at the positive-going magnetic field $H$ is opposite to that at the negative-going magnetic field $H$ , which is +1 if $dH/dt > 0$ and is −1 if $dH/dt &lt; 0$ . This implies that an inductor has different inductances at the current ramp-up time due to $dH/dt>0$ and ramp-down time due to $dH/dt &lt; 0$ . However, this phenomenon is never reported until now. In this article, the inductance of an inductor is found which is larger than the intrinsic inductance at the current ramp-up time ( $t_{\text {up}}$ ) and smaller than the intrinsic inductance at the current ramp-down time ( $t_{\text {dn}}$ ) for a boost converter during the continuous conduction mode (CCM) voltage converter. Moreover, hysteresis also makes the classical model of the voltage conversion ratio for boost converter design, $V_{\text {OUT}}/V_{\text {IN}}= 1/(1-D)$ , invalid since $D(t_{\text {up}}/T$ ) is not a constant caused by the $t_{\text {up}}$ and $t_{\text {dn}}$ varied with the output current of boost converter, where $t_{\text {up}} + t_{\text {dn}}= T$ . The hysteresis model aids designers in estimating the behavior of inductor current variations more accurately without having to wait for chip manufacturing and measurement to reveal the actual behavior.

The gallium nitride (GaN)-on-Si low-side gate driver proposed in this article has four main features: First, the self-pumped drive enhance (SPDE) technique achieves fast transients. Second, short-period negative voltage (SPNV) technique avoids the Miller coupling effect and improves efficiency. Third, a dual-mode Voltage regulator ensures sufficient current and minimizes power dissipation. Finally, monolithic low-side gate drivers provide robust drive capability. This work can suppress the ringing caused by high dV / dt of $V_{\mathrm {DS}}$ , thereby minimizing the tail time $T_{\mathrm {tail}}$ , achieving a $14.7\times $ reduction in tailing current loss, suppressing abnormal conduction, and reducing reverse conduction loss by 37.0%.